2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include "skeleton.dtsi"
15 #include "imx50-pinfunc.h"
16 #include <dt-bindings/clock/imx5-clock.h>
39 compatible = "arm,cortex-a8";
44 tzic: tz-interrupt-controller@0fffc000 {
45 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
47 #interrupt-cells = <1>;
48 reg = <0x0fffc000 0x4000>;
56 compatible = "fsl,imx-ckil", "fixed-clock";
58 clock-frequency = <32768>;
62 compatible = "fsl,imx-ckih1", "fixed-clock";
64 clock-frequency = <22579200>;
68 compatible = "fsl,imx-ckih2", "fixed-clock";
70 clock-frequency = <0>;
74 compatible = "fsl,imx-osc", "fixed-clock";
76 clock-frequency = <24000000>;
83 compatible = "simple-bus";
84 interrupt-parent = <&tzic>;
87 aips@50000000 { /* AIPS1 */
88 compatible = "fsl,aips-bus", "simple-bus";
91 reg = <0x50000000 0x10000000>;
95 compatible = "fsl,spba-bus", "simple-bus";
98 reg = <0x50000000 0x40000>;
101 esdhc1: esdhc@50004000 {
102 compatible = "fsl,imx50-esdhc";
103 reg = <0x50004000 0x4000>;
105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
108 clock-names = "ipg", "ahb", "per";
113 esdhc2: esdhc@50008000 {
114 compatible = "fsl,imx50-esdhc";
115 reg = <0x50008000 0x4000>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
120 clock-names = "ipg", "ahb", "per";
125 uart3: serial@5000c000 {
126 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
127 reg = <0x5000c000 0x4000>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
131 clock-names = "ipg", "per";
135 ecspi1: ecspi@50010000 {
136 #address-cells = <1>;
138 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
139 reg = <0x50010000 0x4000>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
143 clock-names = "ipg", "per";
148 #sound-dai-cells = <0>;
149 compatible = "fsl,imx50-ssi",
152 reg = <0x50014000 0x4000>;
154 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
155 dmas = <&sdma 24 1 0>,
157 dma-names = "rx", "tx";
158 fsl,fifo-depth = <15>;
162 esdhc3: esdhc@50020000 {
163 compatible = "fsl,imx50-esdhc";
164 reg = <0x50020000 0x4000>;
166 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
169 clock-names = "ipg", "ahb", "per";
174 esdhc4: esdhc@50024000 {
175 compatible = "fsl,imx50-esdhc";
176 reg = <0x50024000 0x4000>;
178 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
179 <&clks IMX5_CLK_DUMMY>,
180 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
181 clock-names = "ipg", "ahb", "per";
187 usbotg: usb@53f80000 {
188 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
189 reg = <0x53f80000 0x0200>;
191 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
195 usbh1: usb@53f80200 {
196 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
197 reg = <0x53f80200 0x0200>;
199 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
204 usbh2: usb@53f80400 {
205 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
206 reg = <0x53f80400 0x0200>;
208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
213 usbh3: usb@53f80600 {
214 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
215 reg = <0x53f80600 0x0200>;
217 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
222 gpio1: gpio@53f84000 {
223 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
224 reg = <0x53f84000 0x4000>;
225 interrupts = <50 51>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 gpio-ranges = <&iomuxc 0 151 28>;
233 gpio2: gpio@53f88000 {
234 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
235 reg = <0x53f88000 0x4000>;
236 interrupts = <52 53>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
242 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
243 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
244 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
247 gpio3: gpio@53f8c000 {
248 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
249 reg = <0x53f8c000 0x4000>;
250 interrupts = <54 55>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 gpio-ranges = <&iomuxc 0 108 32>;
258 gpio4: gpio@53f90000 {
259 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
260 reg = <0x53f90000 0x4000>;
261 interrupts = <56 57>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
270 wdog1: wdog@53f98000 {
271 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
272 reg = <0x53f98000 0x4000>;
274 clocks = <&clks IMX5_CLK_DUMMY>;
277 gpt: timer@53fa0000 {
278 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
279 reg = <0x53fa0000 0x4000>;
281 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
282 <&clks IMX5_CLK_GPT_HF_GATE>;
283 clock-names = "ipg", "per";
286 iomuxc: iomuxc@53fa8000 {
287 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
288 reg = <0x53fa8000 0x4000>;
291 gpr: iomuxc-gpr@53fa8000 {
292 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
293 reg = <0x53fa8000 0xc>;
298 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
299 reg = <0x53fb4000 0x4000>;
300 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
301 <&clks IMX5_CLK_PWM1_HF_GATE>;
302 clock-names = "ipg", "per";
308 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
309 reg = <0x53fb8000 0x4000>;
310 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
311 <&clks IMX5_CLK_PWM2_HF_GATE>;
312 clock-names = "ipg", "per";
316 uart1: serial@53fbc000 {
317 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
318 reg = <0x53fbc000 0x4000>;
320 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
321 <&clks IMX5_CLK_UART1_PER_GATE>;
322 clock-names = "ipg", "per";
326 uart2: serial@53fc0000 {
327 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
328 reg = <0x53fc0000 0x4000>;
330 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
331 <&clks IMX5_CLK_UART2_PER_GATE>;
332 clock-names = "ipg", "per";
337 compatible = "fsl,imx50-src", "fsl,imx51-src";
338 reg = <0x53fd0000 0x4000>;
343 compatible = "fsl,imx50-ccm";
344 reg = <0x53fd4000 0x4000>;
345 interrupts = <0 71 0x04 0 72 0x04>;
349 gpio5: gpio@53fdc000 {
350 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
351 reg = <0x53fdc000 0x4000>;
352 interrupts = <103 104>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
360 gpio6: gpio@53fe0000 {
361 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
362 reg = <0x53fe0000 0x4000>;
363 interrupts = <105 106>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
372 #address-cells = <1>;
374 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
375 reg = <0x53fec000 0x4000>;
377 clocks = <&clks IMX5_CLK_I2C3_GATE>;
381 uart4: serial@53ff0000 {
382 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
383 reg = <0x53ff0000 0x4000>;
385 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
386 <&clks IMX5_CLK_UART4_PER_GATE>;
387 clock-names = "ipg", "per";
392 aips@60000000 { /* AIPS2 */
393 compatible = "fsl,aips-bus", "simple-bus";
394 #address-cells = <1>;
396 reg = <0x60000000 0x10000000>;
399 uart5: serial@63f90000 {
400 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
401 reg = <0x63f90000 0x4000>;
403 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
404 <&clks IMX5_CLK_UART5_PER_GATE>;
405 clock-names = "ipg", "per";
409 owire: owire@63fa4000 {
410 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
411 reg = <0x63fa4000 0x4000>;
412 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
416 ecspi2: ecspi@63fac000 {
417 #address-cells = <1>;
419 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
420 reg = <0x63fac000 0x4000>;
422 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
423 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
424 clock-names = "ipg", "per";
428 sdma: sdma@63fb0000 {
429 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
430 reg = <0x63fb0000 0x4000>;
432 clocks = <&clks IMX5_CLK_SDMA_GATE>,
433 <&clks IMX5_CLK_SDMA_GATE>;
434 clock-names = "ipg", "ahb";
435 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
438 cspi: cspi@63fc0000 {
439 #address-cells = <1>;
441 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
442 reg = <0x63fc0000 0x4000>;
444 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
445 <&clks IMX5_CLK_CSPI_IPG_GATE>;
446 clock-names = "ipg", "per";
451 #address-cells = <1>;
453 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
454 reg = <0x63fc4000 0x4000>;
456 clocks = <&clks IMX5_CLK_I2C2_GATE>;
461 #address-cells = <1>;
463 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
464 reg = <0x63fc8000 0x4000>;
466 clocks = <&clks IMX5_CLK_I2C1_GATE>;
471 #sound-dai-cells = <0>;
472 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
474 reg = <0x63fcc000 0x4000>;
476 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
477 dmas = <&sdma 28 0 0>,
479 dma-names = "rx", "tx";
480 fsl,fifo-depth = <15>;
484 audmux: audmux@63fd0000 {
485 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
486 reg = <0x63fd0000 0x4000>;
490 fec: ethernet@63fec000 {
491 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
492 reg = <0x63fec000 0x4000>;
494 clocks = <&clks IMX5_CLK_FEC_GATE>,
495 <&clks IMX5_CLK_FEC_GATE>,
496 <&clks IMX5_CLK_FEC_GATE>;
497 clock-names = "ipg", "ahb", "ptp";