arch/arm/boot/dts/imx50.dtsi

   1 /*
   2  * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
   3  * Copyright 2011 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include "imx50-pinfunc.h"
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/clock/imx5-clock.h>
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         /*
  22          * The decompressor and also some bootloaders rely on a
  23          * pre-existing /chosen node to be available to insert the
  24          * command line and merge other ATAGS info.
  25          */
  26         chosen {};
  27
  28         aliases {
  29                 ethernet0 = &fec;
  30                 gpio0 = &gpio1;
  31                 gpio1 = &gpio2;
  32                 gpio2 = &gpio3;
  33                 gpio3 = &gpio4;
  34                 gpio4 = &gpio5;
  35                 gpio5 = &gpio6;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a8";
  49                         reg = <0x0>;
  50                 };
  51         };
  52
  53         tzic: tz-interrupt-controller@fffc000 {
  54                 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <1>;
  57                 reg = <0x0fffc000 0x4000>;
  58         };
  59
  60         clocks {
  61                 ckil {
  62                         compatible = "fsl,imx-ckil", "fixed-clock";
  63                         #clock-cells = <0>;
  64                         clock-frequency = <32768>;
  65                 };
  66
  67                 ckih1 {
  68                         compatible = "fsl,imx-ckih1", "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <22579200>;
  71                 };
  72
  73                 ckih2 {
  74                         compatible = "fsl,imx-ckih2", "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <0>;
  77                 };
  78
  79                 osc {
  80                         compatible = "fsl,imx-osc", "fixed-clock";
  81                         #clock-cells = <0>;
  82                         clock-frequency = <24000000>;
  83                 };
  84         };
  85
  86         soc {
  87                 #address-cells = <1>;
  88                 #size-cells = <1>;
  89                 compatible = "simple-bus";
  90                 interrupt-parent = <&tzic>;
  91                 ranges;
  92
  93                 aips@50000000 { /* AIPS1 */
  94                         compatible = "fsl,aips-bus", "simple-bus";
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         reg = <0x50000000 0x10000000>;
  98                         ranges;
  99
 100                         spba@50000000 {
 101                                 compatible = "fsl,spba-bus", "simple-bus";
 102                                 #address-cells = <1>;
 103                                 #size-cells = <1>;
 104                                 reg = <0x50000000 0x40000>;
 105                                 ranges;
 106
 107                                 esdhc1: esdhc@50004000 {
 108                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 109                                         reg = <0x50004000 0x4000>;
 110                                         interrupts = <1>;
 111                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 112                                                  <&clks IMX5_CLK_DUMMY>,
 113                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 114                                         clock-names = "ipg", "ahb", "per";
 115                                         bus-width = <4>;
 116                                         status = "disabled";
 117                                 };
 118
 119                                 esdhc2: esdhc@50008000 {
 120                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 121                                         reg = <0x50008000 0x4000>;
 122                                         interrupts = <2>;
 123                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 124                                                  <&clks IMX5_CLK_DUMMY>,
 125                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 126                                         clock-names = "ipg", "ahb", "per";
 127                                         bus-width = <4>;
 128                                         status = "disabled";
 129                                 };
 130
 131                                 uart3: serial@5000c000 {
 132                                         compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 133                                         reg = <0x5000c000 0x4000>;
 134                                         interrupts = <33>;
 135                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 136                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 137                                         clock-names = "ipg", "per";
 138                                         status = "disabled";
 139                                 };
 140
 141                                 ecspi1: ecspi@50010000 {
 142                                         #address-cells = <1>;
 143                                         #size-cells = <0>;
 144                                         compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 145                                         reg = <0x50010000 0x4000>;
 146                                         interrupts = <36>;
 147                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 148                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 149                                         clock-names = "ipg", "per";
 150                                         status = "disabled";
 151                                 };
 152
 153                                 ssi2: ssi@50014000 {
 154                                         #sound-dai-cells = <0>;
 155                                         compatible = "fsl,imx50-ssi",
 156                                                         "fsl,imx51-ssi",
 157                                                         "fsl,imx21-ssi";
 158                                         reg = <0x50014000 0x4000>;
 159                                         interrupts = <30>;
 160                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 161                                         dmas = <&sdma 24 1 0>,
 162                                                <&sdma 25 1 0>;
 163                                         dma-names = "rx", "tx";
 164                                         fsl,fifo-depth = <15>;
 165                                         status = "disabled";
 166                                 };
 167
 168                                 esdhc3: esdhc@50020000 {
 169                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 170                                         reg = <0x50020000 0x4000>;
 171                                         interrupts = <3>;
 172                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 173                                                  <&clks IMX5_CLK_DUMMY>,
 174                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 175                                         clock-names = "ipg", "ahb", "per";
 176                                         bus-width = <4>;
 177                                         status = "disabled";
 178                                 };
 179
 180                                 esdhc4: esdhc@50024000 {
 181                                         compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
 182                                         reg = <0x50024000 0x4000>;
 183                                         interrupts = <4>;
 184                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 185                                                  <&clks IMX5_CLK_DUMMY>,
 186                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 187                                         clock-names = "ipg", "ahb", "per";
 188                                         bus-width = <4>;
 189                                         status = "disabled";
 190                                 };
 191                         };
 192
 193                         usbotg: usb@53f80000 {
 194                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 195                                 reg = <0x53f80000 0x0200>;
 196                                 interrupts = <18>;
 197                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 198                                 status = "disabled";
 199                         };
 200
 201                         usbh1: usb@53f80200 {
 202                                 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
 203                                 reg = <0x53f80200 0x0200>;
 204                                 interrupts = <14>;
 205                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 206                                 dr_mode = "host";
 207                                 status = "disabled";
 208                         };
 209
 210                         gpio1: gpio@53f84000 {
 211                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 212                                 reg = <0x53f84000 0x4000>;
 213                                 interrupts = <50 51>;
 214                                 gpio-controller;
 215                                 #gpio-cells = <2>;
 216                                 interrupt-controller;
 217                                 #interrupt-cells = <2>;
 218                                 gpio-ranges = <&iomuxc 0 151 28>;
 219                         };
 220
 221                         gpio2: gpio@53f88000 {
 222                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 223                                 reg = <0x53f88000 0x4000>;
 224                                 interrupts = <52 53>;
 225                                 gpio-controller;
 226                                 #gpio-cells = <2>;
 227                                 interrupt-controller;
 228                                 #interrupt-cells = <2>;
 229                                 gpio-ranges = <&iomuxc  0 75 8>, <&iomuxc 8 100 8>,
 230                                               <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
 231                                               <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
 232                                               <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
 233                         };
 234
 235                         gpio3: gpio@53f8c000 {
 236                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 237                                 reg = <0x53f8c000 0x4000>;
 238                                 interrupts = <54 55>;
 239                                 gpio-controller;
 240                                 #gpio-cells = <2>;
 241                                 interrupt-controller;
 242                                 #interrupt-cells = <2>;
 243                                 gpio-ranges = <&iomuxc 0 108 32>;
 244                         };
 245
 246                         gpio4: gpio@53f90000 {
 247                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 248                                 reg = <0x53f90000 0x4000>;
 249                                 interrupts = <56 57>;
 250                                 gpio-controller;
 251                                 #gpio-cells = <2>;
 252                                 interrupt-controller;
 253                                 #interrupt-cells = <2>;
 254                                 gpio-ranges = <&iomuxc  0   8  8>, <&iomuxc 8 45 12>,
 255                                               <&iomuxc 20 140 11>;
 256                         };
 257
 258                         wdog1: wdog@53f98000 {
 259                                 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
 260                                 reg = <0x53f98000 0x4000>;
 261                                 interrupts = <58>;
 262                                 clocks = <&clks IMX5_CLK_DUMMY>;
 263                         };
 264
 265                         gpt: timer@53fa0000 {
 266                                 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
 267                                 reg = <0x53fa0000 0x4000>;
 268                                 interrupts = <39>;
 269                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 270                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 271                                 clock-names = "ipg", "per";
 272                         };
 273
 274                         iomuxc: iomuxc@53fa8000 {
 275                                 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
 276                                 reg = <0x53fa8000 0x4000>;
 277                         };
 278
 279                         gpr: iomuxc-gpr@53fa8000 {
 280                                 compatible = "fsl,imx50-iomuxc-gpr", "syscon";
 281                                 reg = <0x53fa8000 0xc>;
 282                         };
 283
 284                         pwm1: pwm@53fb4000 {
 285                                 #pwm-cells = <2>;
 286                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 287                                 reg = <0x53fb4000 0x4000>;
 288                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 289                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 290                                 clock-names = "ipg", "per";
 291                                 interrupts = <61>;
 292                         };
 293
 294                         pwm2: pwm@53fb8000 {
 295                                 #pwm-cells = <2>;
 296                                 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
 297                                 reg = <0x53fb8000 0x4000>;
 298                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 299                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 300                                 clock-names = "ipg", "per";
 301                                 interrupts = <94>;
 302                         };
 303
 304                         uart1: serial@53fbc000 {
 305                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 306                                 reg = <0x53fbc000 0x4000>;
 307                                 interrupts = <31>;
 308                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 309                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 310                                 clock-names = "ipg", "per";
 311                                 status = "disabled";
 312                         };
 313
 314                         uart2: serial@53fc0000 {
 315                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 316                                 reg = <0x53fc0000 0x4000>;
 317                                 interrupts = <32>;
 318                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 319                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 320                                 clock-names = "ipg", "per";
 321                                 status = "disabled";
 322                         };
 323
 324                         src: src@53fd0000 {
 325                                 compatible = "fsl,imx50-src", "fsl,imx51-src";
 326                                 reg = <0x53fd0000 0x4000>;
 327                                 #reset-cells = <1>;
 328                         };
 329
 330                         clks: ccm@53fd4000{
 331                                 compatible = "fsl,imx50-ccm";
 332                                 reg = <0x53fd4000 0x4000>;
 333                                 interrupts = <0 71 0x04 0 72 0x04>;
 334                                 #clock-cells = <1>;
 335                         };
 336
 337                         gpio5: gpio@53fdc000 {
 338                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x53fdc000 0x4000>;
 340                                 interrupts = <103 104>;
 341                                 gpio-controller;
 342                                 #gpio-cells = <2>;
 343                                 interrupt-controller;
 344                                 #interrupt-cells = <2>;
 345                                 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
 346                         };
 347
 348                         gpio6: gpio@53fe0000 {
 349                                 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
 350                                 reg = <0x53fe0000 0x4000>;
 351                                 interrupts = <105 106>;
 352                                 gpio-controller;
 353                                 #gpio-cells = <2>;
 354                                 interrupt-controller;
 355                                 #interrupt-cells = <2>;
 356                                 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
 357                         };
 358
 359                         i2c3: i2c@53fec000 {
 360                                 #address-cells = <1>;
 361                                 #size-cells = <0>;
 362                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 363                                 reg = <0x53fec000 0x4000>;
 364                                 interrupts = <64>;
 365                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 366                                 status = "disabled";
 367                         };
 368
 369                         uart4: serial@53ff0000 {
 370                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 371                                 reg = <0x53ff0000 0x4000>;
 372                                 interrupts = <13>;
 373                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 374                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 375                                 clock-names = "ipg", "per";
 376                                 status = "disabled";
 377                         };
 378                 };
 379
 380                 aips@60000000 { /* AIPS2 */
 381                         compatible = "fsl,aips-bus", "simple-bus";
 382                         #address-cells = <1>;
 383                         #size-cells = <1>;
 384                         reg = <0x60000000 0x10000000>;
 385                         ranges;
 386
 387                         uart5: serial@63f90000 {
 388                                 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
 389                                 reg = <0x63f90000 0x4000>;
 390                                 interrupts = <86>;
 391                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 392                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 393                                 clock-names = "ipg", "per";
 394                                 status = "disabled";
 395                         };
 396
 397                         owire: owire@63fa4000 {
 398                                 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
 399                                 reg = <0x63fa4000 0x4000>;
 400                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 401                                 status = "disabled";
 402                         };
 403
 404                         ecspi2: ecspi@63fac000 {
 405                                 #address-cells = <1>;
 406                                 #size-cells = <0>;
 407                                 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
 408                                 reg = <0x63fac000 0x4000>;
 409                                 interrupts = <37>;
 410                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 411                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 412                                 clock-names = "ipg", "per";
 413                                 status = "disabled";
 414                         };
 415
 416                         sdma: sdma@63fb0000 {
 417                                 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
 418                                 reg = <0x63fb0000 0x4000>;
 419                                 interrupts = <6>;
 420                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 421                                          <&clks IMX5_CLK_AHB>;
 422                                 clock-names = "ipg", "ahb";
 423                                 #dma-cells = <3>;
 424                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 425                         };
 426
 427                         cspi: cspi@63fc0000 {
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430                                 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
 431                                 reg = <0x63fc0000 0x4000>;
 432                                 interrupts = <38>;
 433                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 434                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 435                                 clock-names = "ipg", "per";
 436                                 status = "disabled";
 437                         };
 438
 439                         i2c2: i2c@63fc4000 {
 440                                 #address-cells = <1>;
 441                                 #size-cells = <0>;
 442                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 443                                 reg = <0x63fc4000 0x4000>;
 444                                 interrupts = <63>;
 445                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 446                                 status = "disabled";
 447                         };
 448
 449                         i2c1: i2c@63fc8000 {
 450                                 #address-cells = <1>;
 451                                 #size-cells = <0>;
 452                                 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
 453                                 reg = <0x63fc8000 0x4000>;
 454                                 interrupts = <62>;
 455                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 456                                 status = "disabled";
 457                         };
 458
 459                         ssi1: ssi@63fcc000 {
 460                                 #sound-dai-cells = <0>;
 461                                 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
 462                                                         "fsl,imx21-ssi";
 463                                 reg = <0x63fcc000 0x4000>;
 464                                 interrupts = <29>;
 465                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 466                                 dmas = <&sdma 28 0 0>,
 467                                        <&sdma 29 0 0>;
 468                                 dma-names = "rx", "tx";
 469                                 fsl,fifo-depth = <15>;
 470                                 status = "disabled";
 471                         };
 472
 473                         audmux: audmux@63fd0000 {
 474                                 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
 475                                 reg = <0x63fd0000 0x4000>;
 476                                 status = "disabled";
 477                         };
 478
 479                         fec: ethernet@63fec000 {
 480                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 481                                 reg = <0x63fec000 0x4000>;
 482                                 interrupts = <87>;
 483                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 484                                          <&clks IMX5_CLK_FEC_GATE>,
 485                                          <&clks IMX5_CLK_FEC_GATE>;
 486                                 clock-names = "ipg", "ahb", "ptp";
 487                                 status = "disabled";
 488                         };
 489                 };
 490         };
 491 };