arch/arm/boot/dts/hi3519.dtsi

   1 /*
   2  * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute  it and/or modify it
   5  * under  the terms of  the GNU General  Public License as published by the
   6  * Free Software Foundation;  either version 2 of the  License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  */
  18
  19 #include <dt-bindings/clock/hi3519-clock.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21 / {
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24         chosen { };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a7";
  33                         reg = <0>;
  34                 };
  35         };
  36
  37         gic: interrupt-controller@10300000 {
  38                 compatible = "arm,cortex-a7-gic";
  39                 #interrupt-cells = <3>;
  40                 interrupt-controller;
  41                 reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
  42         };
  43
  44         clk_3m: clk_3m {
  45                 compatible = "fixed-clock";
  46                 #clock-cells = <0>;
  47                 clock-frequency = <3000000>;
  48         };
  49
  50         crg: clock-reset-controller@12010000 {
  51                 compatible = "hisilicon,hi3519-crg";
  52                 #clock-cells = <1>;
  53                 #reset-cells = <2>;
  54                 reg = <0x12010000 0x10000>;
  55         };
  56
  57         soc {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 compatible = "simple-bus";
  61                 interrupt-parent = <&gic>;
  62                 ranges;
  63
  64                 uart0: serial@12100000 {
  65                         compatible = "arm,pl011", "arm,primecell";
  66                         reg = <0x12100000 0x1000>;
  67                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  68                         clocks = <&crg HI3519_UART0_CLK>;
  69                         clock-names = "apb_pclk";
  70                         status = "disable";
  71                 };
  72
  73                 uart1: serial@12101000 {
  74                         compatible = "arm,pl011", "arm,primecell";
  75                         reg = <0x12101000 0x1000>;
  76                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  77                         clocks = <&crg HI3519_UART1_CLK>;
  78                         clock-names = "apb_pclk";
  79                         status = "disable";
  80                 };
  81
  82                 uart2: serial@12102000 {
  83                         compatible = "arm,pl011", "arm,primecell";
  84                         reg = <0x12102000 0x1000>;
  85                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  86                         clocks = <&crg HI3519_UART2_CLK>;
  87                         clock-names = "apb_pclk";
  88                         status = "disable";
  89                 };
  90
  91                 uart3: serial@12103000 {
  92                         compatible = "arm,pl011", "arm,primecell";
  93                         reg = <0x12103000 0x1000>;
  94                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  95                         clocks = <&crg HI3519_UART3_CLK>;
  96                         clock-names = "apb_pclk";
  97                         status = "disable";
  98                 };
  99
 100                 uart4: serial@12104000 {
 101                         compatible = "arm,pl011", "arm,primecell";
 102                         reg = <0x12104000 0x1000>;
 103                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&crg HI3519_UART4_CLK>;
 105                         clock-names = "apb_pclk";
 106                         status = "disable";
 107                 };
 108
 109                 dual_timer0: timer@12000000 {
 110                         compatible = "arm,sp804", "arm,primecell";
 111                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 112                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 113                         reg = <0x12000000 0x1000>;
 114                         clocks = <&clk_3m>;
 115                         clock-names = "apb_pclk";
 116                         status = "disable";
 117                 };
 118
 119                 dual_timer1: timer@12001000 {
 120                         compatible = "arm,sp804", "arm,primecell";
 121                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 123                         reg = <0x12001000 0x1000>;
 124                         clocks = <&clk_3m>;
 125                         clock-names = "apb_pclk";
 126                         status = "disable";
 127                 };
 128
 129                 dual_timer2: timer@12002000 {
 130                         compatible = "arm,sp804", "arm,primecell";
 131                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 133                         reg = <0x12002000 0x1000>;
 134                         clocks = <&clk_3m>;
 135                         clock-names = "apb_pclk";
 136                         status = "disable";
 137                 };
 138
 139                 spi_bus0: spi@12120000 {
 140                         compatible = "arm,pl022", "arm,primecell";
 141                         reg = <0x12120000 0x1000>;
 142                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 143                         clocks = <&crg HI3519_SPI0_CLK>;
 144                         clock-names = "apb_pclk";
 145                         num-cs = <1>;
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         status = "disable";
 149                 };
 150
 151                 spi_bus1: spi@12121000 {
 152                         compatible = "arm,pl022", "arm,primecell";
 153                         reg = <0x12121000 0x1000>;
 154                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&crg HI3519_SPI1_CLK>;
 156                         clock-names = "apb_pclk";
 157                         num-cs = <1>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         status = "disable";
 161                 };
 162
 163                 spi_bus2: spi@12122000 {
 164                         compatible = "arm,pl022", "arm,primecell";
 165                         reg = <0x12122000 0x1000>;
 166                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 167                         clocks = <&crg HI3519_SPI2_CLK>;
 168                         clock-names = "apb_pclk";
 169                         num-cs = <1>;
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                         status = "disable";
 173                 };
 174
 175                 sysctrl: system-controller@12020000 {
 176                         compatible = "hisilicon,hi3519-sysctrl", "syscon";
 177                         reg = <0x12020000 0x1000>;
 178                 };
 179
 180                 reboot {
 181                         compatible = "syscon-reboot";
 182                         regmap = <&sysctrl>;
 183                         offset = <0x4>;
 184                         mask = <0xdeadbeef>;
 185                 };
 186         };
 187 };