1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for ITian Square One SQ201 NAS
9 #include <dt-bindings/input/input.h>
12 model = "ITian Square One SQ201";
13 compatible = "itian,sq201", "cortina,gemini";
17 memory@0 { /* 128 MB */
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
28 compatible = "gpio-keys";
31 debounce-interval = <50>;
33 linux,code = <KEY_SETUP>;
34 label = "factory reset";
35 /* Conflict with NAND flash */
36 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
41 compatible = "gpio-leds";
43 label = "sq201:green:info";
44 /* Conflict with parallel flash */
45 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
47 linux,default-trigger = "heartbeat";
50 label = "sq201:green:usb";
51 /* Conflict with parallel and NAND flash */
52 gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
53 default-state = "off";
54 linux,default-trigger = "usb-host";
59 compatible = "virtual,mdio-gpio";
60 /* Uses MDC and MDIO */
61 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
62 <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
66 /* This is a Marvell 88E1111 ethernet transciever */
67 phy0: ethernet-phy@1 {
73 compatible = "spi-gpio";
76 /* Check pin collisions */
77 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
78 gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
79 gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
80 cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
81 num-chipselects = <1>;
84 compatible = "vitesse,vsc7395";
86 /* Specified for 2.5 MHz or below */
87 spi-max-frequency = <2500000>;
130 * Flash access can be enabled, with the side effect
131 * of disabling access to GPIO LED on GPIO0[20] which
132 * reuse one of the parallel flash chip select lines.
133 * Also the default firmware on the machine has the
134 * problem that since it uses the flash, the two LEDS
135 * on the right become numb.
137 /* status = "okay"; */
139 reg = <0x30000000 0x01000000>;
142 compatible = "redboot-fis";
143 /* Eraseblock at 0xfe0000 */
144 fis-index-block = <0x1fc>;
148 syscon: syscon@40000000 {
151 * gpio0fgrp cover line 18 used by reset button
152 * gpio0ggrp cover line 20 used by info LED
153 * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
154 * gpio0kgrp cover line 31 used by USB LED
156 gpio0_default_pins: pinctrl-gpio0 {
159 groups = "gpio0fgrp",
166 * gpio0dgrp cover lines used by the SPI
167 * to the Vitesse G5x chip.
169 gpio1_default_pins: pinctrl-gpio1 {
172 groups = "gpio1dgrp";
178 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
180 /* Settings come from memory dump in PLATO */
182 pins = "V8 GMAC0 RXDV";
186 pins = "Y7 GMAC0 RXC";
190 pins = "T8 GMAC0 TXEN";
194 pins = "U8 GMAC0 TXC";
198 pins = "T10 GMAC1 RXDV";
202 pins = "Y11 GMAC1 RXC";
206 pins = "W11 GMAC1 TXEN";
210 pins = "V11 GMAC1 TXC";
214 /* The data lines all have default skew */
215 pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
216 "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
217 "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
218 "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
219 "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
220 "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
221 "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
222 "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
225 /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
227 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
228 drive-strength = <16>;
234 sata: sata@46000000 {
235 cortina,gemini-ata-muxmode = <0>;
236 cortina,gemini-enable-sata-bridge;
240 gpio0: gpio@4d000000 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&gpio0_default_pins>;
245 gpio1: gpio@4e000000 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&gpio1_default_pins>;
252 interrupt-map-mask = <0xf800 0 0 7>;
254 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
255 <0x4800 0 0 2 &pci_intc 1>,
256 <0x4800 0 0 3 &pci_intc 2>,
257 <0x4800 0 0 4 &pci_intc 3>,
258 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
259 <0x5000 0 0 2 &pci_intc 2>,
260 <0x5000 0 0 3 &pci_intc 3>,
261 <0x5000 0 0 4 &pci_intc 0>,
262 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
263 <0x5800 0 0 2 &pci_intc 3>,
264 <0x5800 0 0 3 &pci_intc 0>,
265 <0x5800 0 0 4 &pci_intc 1>,
266 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
267 <0x6000 0 0 2 &pci_intc 0>,
268 <0x6000 0 0 3 &pci_intc 1>,
269 <0x6000 0 0 4 &pci_intc 2>;
277 phy-handle = <&phy0>;