2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
23 bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait";
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
31 debounce-interval = <50>;
33 linux,code = <KEY_ESC>;
35 /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
36 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
39 debounce-interval = <50>;
41 linux,code = <KEY_EJECTCD>;
43 /* Collides with LPC LFRAME, UART RTS, SSP TXD */
44 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
49 compatible = "regulator-fixed";
50 regulator-name = "display-power";
51 regulator-min-microvolt = <3600000>;
52 regulator-max-microvolt = <3600000>;
53 /* Collides with LCD E */
54 gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
59 compatible = "spi-gpio";
63 /* Collides with IDE pins, that's cool (we do not use them) */
64 gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
65 gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
66 gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
67 /* Collides with pflash CE1, not so cool */
68 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
69 num-chipselects = <1>;
72 compatible = "dlink,dir-685-panel", "ilitek,ili9322";
74 /* 50 ns min period = 20 MHz */
75 spi-max-frequency = <20000000>;
76 spi-cpol; /* Clock active low */
77 vcc-supply = <&vdisp>;
78 iovcc-supply = <&vdisp>;
79 vci-supply = <&vdisp>;
83 remote-endpoint = <&display_out>;
90 compatible = "gpio-leds";
92 label = "dir685:blue:WPS";
93 /* Collides with ICE */
94 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
96 linux,default-trigger = "heartbeat";
99 * These two LEDs are on the side of the device.
100 * For electrical reasons, both LEDs cannot be active
101 * at the same time so only blue or orange can be on at
102 * one time. Enabling both makes the LED go dark.
103 * The LEDs both sit inside the unmount button and the
104 * label on the case says "unmount".
107 label = "dir685:blue:HD";
108 /* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
109 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
110 default-state = "off";
111 linux,default-trigger = "disk-read";
114 label = "dir685:orange:HD";
115 /* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
116 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
117 default-state = "off";
118 linux,default-trigger = "disk-write";
123 * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
124 * Since the platform has no temperature sensor, this is controlled
125 * from userspace by using the hard disks S.M.A.R.T. temperature
126 * sensor. It is turned on when the temperature exceeds 46 degrees
127 * and turned off when the temperatures goes below 41 degrees
131 compatible = "gpio-fan";
132 /* Collides with IDE */
133 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
134 gpio-fan,speed-map = <0 0>, <10000 1>;
135 #cooling-cells = <2>;
139 * The touchpad input is connected to a GPIO bit-banged
143 compatible = "i2c-gpio";
144 /* Collides with ICE */
145 sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
146 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
147 #address-cells = <1>;
151 compatible = "dlink,dir685-touchkeys";
153 interrupt-parent = <&gpio0>;
154 /* Collides with NAND flash */
155 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
159 /* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
161 compatible = "realtek,rtl8366rb";
162 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
163 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
164 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
165 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
166 realtek,disable-leds;
168 switch_intc: interrupt-controller {
169 /* GPIO 15 provides the interrupt */
170 interrupt-parent = <&gpio0>;
171 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
172 interrupt-controller;
173 #address-cells = <0>;
174 #interrupt-cells = <1>;
178 #address-cells = <1>;
184 phy-handle = <&phy0>;
189 phy-handle = <&phy1>;
194 phy-handle = <&phy2>;
199 phy-handle = <&phy3>;
204 phy-handle = <&phy4>;
206 rtl8366rb_cpu_port: port@5 {
221 compatible = "realtek,smi-mdio";
222 #address-cells = <1>;
227 interrupt-parent = <&switch_intc>;
232 interrupt-parent = <&switch_intc>;
237 interrupt-parent = <&switch_intc>;
242 interrupt-parent = <&switch_intc>;
247 interrupt-parent = <&switch_intc>;
256 * Flash access is by default disabled, because it
257 * collides with the Chip Enable signal for the display
258 * panel, that reuse the parallel flash Chip Select 1
259 * (CS1). Enabling flash makes graphics stop working.
261 * We might be able to hack around this by letting
262 * GPIO poke around in the flash controller registers.
264 /* status = "okay"; */
266 reg = <0x30000000 0x02000000>;
269 * This "RedBoot" is the Storlink derivative.
273 reg = <0x00000000 0x00040000>;
277 * This firmware image contains the kernel catenated
278 * with the squashfs root filesystem. For some reason
279 * this is called "upgrade" on the vendor system.
283 reg = <0x00040000 0x01f40000>;
286 /* RGDB, Residental Gateway Database? */
289 reg = <0x01f80000 0x00040000>;
293 * This partition contains MAC addresses for WAN,
294 * WLAN and LAN, and the country code (for wireless
299 reg = <0x01fc0000 0x00020000>;
304 reg = <0x01fe0000 0x00020000>;
309 syscon: syscon@40000000 {
312 * gpio0bgrp cover line 5, 6 used by TK I2C
313 * gpio0bgrp cover line 7 used by WPS LED
314 * gpio0cgrp cover line 8, 13 used by keys
315 * and 11, 12 used by the HD LEDs
316 * and line 14, 15 used by RTL8366
317 * RESET and phy ready
318 * gpio0egrp cover line 16 used by VDISP
319 * gpio0fgrp cover line 17 used by TK IRQ
320 * gpio0ggrp cover line 20 used by panel CS
321 * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
323 gpio0_default_pins: pinctrl-gpio0 {
326 groups = "gpio0bgrp",
335 * gpio1bgrp cover line 5,8,7 used by panel SPI
336 * also line 6 used by the fan
339 gpio1_default_pins: pinctrl-gpio1 {
342 groups = "gpio1bgrp";
348 groups = "gmii_gmac0_grp";
351 pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
352 "Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
353 "T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
354 "U8 GMAC0 TXC", "V11 GMAC1 TXC",
355 "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
356 "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
357 "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
358 "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
359 "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
360 "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
361 "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
362 "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
365 /* Set up drive strength on GMAC0 to 16 mA */
367 groups = "gmii_gmac0_grp";
368 drive-strength = <16>;
374 sata: sata@46000000 {
375 cortina,gemini-ata-muxmode = <0>;
376 cortina,gemini-enable-sata-bridge;
380 gpio0: gpio@4d000000 {
381 pinctrl-names = "default";
382 pinctrl-0 = <&gpio0_default_pins>;
385 gpio1: gpio@4e000000 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&gpio1_default_pins>;
392 interrupt-map-mask = <0xf800 0 0 7>;
394 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
395 <0x4800 0 0 2 &pci_intc 1>,
396 <0x4800 0 0 3 &pci_intc 2>,
397 <0x4800 0 0 4 &pci_intc 3>,
398 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
399 <0x5000 0 0 2 &pci_intc 2>,
400 <0x5000 0 0 3 &pci_intc 3>,
401 <0x5000 0 0 4 &pci_intc 0>,
402 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
403 <0x5800 0 0 2 &pci_intc 3>,
404 <0x5800 0 0 3 &pci_intc 0>,
405 <0x5800 0 0 4 &pci_intc 1>,
406 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
407 <0x6000 0 0 2 &pci_intc 0>,
408 <0x6000 0 0 3 &pci_intc 1>,
409 <0x6000 0 0 4 &pci_intc 2>;
424 /* Not used in this platform */
432 display-controller@6a000000 {
437 display_out: endpoint {
438 remote-endpoint = <&panel_in>;