1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos5800.dtsi"
14 #include "exynos5422-cpus.dtsi"
18 device_type = "memory";
19 reg = <0x40000000 0x7EA00000>;
23 stdout-path = "serial2:115200n8";
27 compatible = "samsung,secure-firmware";
28 reg = <0x02073000 0x1000>;
33 compatible = "samsung,exynos5420-oscclk";
34 clock-frequency = <24000000>;
38 bus_wcore_opp_table: opp-table2 {
39 compatible = "operating-points-v2";
41 /* derived from 532MHz MPLL */
43 opp-hz = /bits/ 64 <88700000>;
44 opp-microvolt = <925000 925000 1400000>;
47 opp-hz = /bits/ 64 <133000000>;
48 opp-microvolt = <950000 950000 1400000>;
51 opp-hz = /bits/ 64 <177400000>;
52 opp-microvolt = <950000 950000 1400000>;
55 opp-hz = /bits/ 64 <266000000>;
56 opp-microvolt = <950000 950000 1400000>;
59 opp-hz = /bits/ 64 <532000000>;
60 opp-microvolt = <1000000 1000000 1400000>;
64 bus_noc_opp_table: opp-table3 {
65 compatible = "operating-points-v2";
67 /* derived from 666MHz CPLL */
69 opp-hz = /bits/ 64 <66600000>;
72 opp-hz = /bits/ 64 <74000000>;
75 opp-hz = /bits/ 64 <83250000>;
78 opp-hz = /bits/ 64 <111000000>;
82 bus_fsys_apb_opp_table: opp-table4 {
83 compatible = "operating-points-v2";
85 /* derived from 666MHz CPLL */
87 opp-hz = /bits/ 64 <111000000>;
90 opp-hz = /bits/ 64 <222000000>;
94 bus_fsys2_opp_table: opp-table5 {
95 compatible = "operating-points-v2";
97 /* derived from 600MHz DPLL */
99 opp-hz = /bits/ 64 <75000000>;
102 opp-hz = /bits/ 64 <120000000>;
105 opp-hz = /bits/ 64 <200000000>;
109 bus_mfc_opp_table: opp-table6 {
110 compatible = "operating-points-v2";
112 /* derived from 666MHz CPLL */
114 opp-hz = /bits/ 64 <83250000>;
117 opp-hz = /bits/ 64 <111000000>;
120 opp-hz = /bits/ 64 <166500000>;
123 opp-hz = /bits/ 64 <222000000>;
126 opp-hz = /bits/ 64 <333000000>;
130 bus_gen_opp_table: opp-table7 {
131 compatible = "operating-points-v2";
133 /* derived from 532MHz MPLL */
135 opp-hz = /bits/ 64 <88700000>;
138 opp-hz = /bits/ 64 <133000000>;
141 opp-hz = /bits/ 64 <178000000>;
144 opp-hz = /bits/ 64 <266000000>;
148 bus_peri_opp_table: opp-table8 {
149 compatible = "operating-points-v2";
151 /* derived from 666MHz CPLL */
153 opp-hz = /bits/ 64 <66600000>;
157 bus_g2d_opp_table: opp-table9 {
158 compatible = "operating-points-v2";
160 /* derived from 666MHz CPLL */
162 opp-hz = /bits/ 64 <83250000>;
165 opp-hz = /bits/ 64 <111000000>;
168 opp-hz = /bits/ 64 <166500000>;
171 opp-hz = /bits/ 64 <222000000>;
174 opp-hz = /bits/ 64 <333000000>;
178 bus_g2d_acp_opp_table: opp-table10 {
179 compatible = "operating-points-v2";
181 /* derived from 532MHz MPLL */
183 opp-hz = /bits/ 64 <66500000>;
186 opp-hz = /bits/ 64 <133000000>;
189 opp-hz = /bits/ 64 <178000000>;
192 opp-hz = /bits/ 64 <266000000>;
196 bus_jpeg_opp_table: opp-table11 {
197 compatible = "operating-points-v2";
199 /* derived from 600MHz DPLL */
201 opp-hz = /bits/ 64 <75000000>;
204 opp-hz = /bits/ 64 <150000000>;
207 opp-hz = /bits/ 64 <200000000>;
210 opp-hz = /bits/ 64 <300000000>;
214 bus_jpeg_apb_opp_table: opp-table12 {
215 compatible = "operating-points-v2";
217 /* derived from 666MHz CPLL */
219 opp-hz = /bits/ 64 <83250000>;
222 opp-hz = /bits/ 64 <111000000>;
225 opp-hz = /bits/ 64 <133000000>;
228 opp-hz = /bits/ 64 <166500000>;
232 bus_disp1_fimd_opp_table: opp-table13 {
233 compatible = "operating-points-v2";
235 /* derived from 600MHz DPLL */
237 opp-hz = /bits/ 64 <120000000>;
240 opp-hz = /bits/ 64 <200000000>;
244 bus_disp1_opp_table: opp-table14 {
245 compatible = "operating-points-v2";
247 /* derived from 600MHz DPLL */
249 opp-hz = /bits/ 64 <120000000>;
252 opp-hz = /bits/ 64 <200000000>;
255 opp-hz = /bits/ 64 <300000000>;
259 bus_gscl_opp_table: opp-table15 {
260 compatible = "operating-points-v2";
262 /* derived from 600MHz DPLL */
264 opp-hz = /bits/ 64 <150000000>;
267 opp-hz = /bits/ 64 <200000000>;
270 opp-hz = /bits/ 64 <300000000>;
274 bus_mscl_opp_table: opp-table16 {
275 compatible = "operating-points-v2";
277 /* derived from 666MHz CPLL */
279 opp-hz = /bits/ 64 <84000000>;
282 opp-hz = /bits/ 64 <167000000>;
285 opp-hz = /bits/ 64 <222000000>;
288 opp-hz = /bits/ 64 <333000000>;
291 opp-hz = /bits/ 64 <666000000>;
295 dmc_opp_table: opp-table17 {
296 compatible = "operating-points-v2";
299 opp-hz = /bits/ 64 <165000000>;
300 opp-microvolt = <875000>;
303 opp-hz = /bits/ 64 <206000000>;
304 opp-microvolt = <875000>;
307 opp-hz = /bits/ 64 <275000000>;
308 opp-microvolt = <875000>;
311 opp-hz = /bits/ 64 <413000000>;
312 opp-microvolt = <887500>;
315 opp-hz = /bits/ 64 <543000000>;
316 opp-microvolt = <937500>;
319 opp-hz = /bits/ 64 <633000000>;
320 opp-microvolt = <1012500>;
323 opp-hz = /bits/ 64 <728000000>;
324 opp-microvolt = <1037500>;
327 opp-hz = /bits/ 64 <825000000>;
328 opp-microvolt = <1050000>;
332 samsung_K3QF2F20DB: lpddr3 {
333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
347 tW2W-C2C-min-tck = <0>;
348 tR2R-C2C-min-tck = <0>;
350 tDQSCK-min-tck = <5>;
356 tCKESR-min-tck = <2>;
359 timings_samsung_K3QF2F20DB_800mhz: timings {
360 compatible = "jedec,lpddr3-timings";
361 max-freq = <800000000>;
362 min-freq = <100000000>;
386 vdd-supply = <&ldo4_reg>;
391 operating-points-v2 = <&bus_wcore_opp_table>;
392 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
393 <&nocp_mem1_0>, <&nocp_mem1_1>;
394 vdd-supply = <&buck3_reg>;
395 exynos,saturation-ratio = <100>;
400 operating-points-v2 = <&bus_noc_opp_table>;
401 devfreq = <&bus_wcore>;
406 operating-points-v2 = <&bus_fsys_apb_opp_table>;
407 devfreq = <&bus_wcore>;
412 operating-points-v2 = <&bus_fsys2_opp_table>;
413 devfreq = <&bus_wcore>;
418 operating-points-v2 = <&bus_mfc_opp_table>;
419 devfreq = <&bus_wcore>;
424 operating-points-v2 = <&bus_gen_opp_table>;
425 devfreq = <&bus_wcore>;
430 operating-points-v2 = <&bus_peri_opp_table>;
431 devfreq = <&bus_wcore>;
436 operating-points-v2 = <&bus_g2d_opp_table>;
437 devfreq = <&bus_wcore>;
442 operating-points-v2 = <&bus_g2d_acp_opp_table>;
443 devfreq = <&bus_wcore>;
448 operating-points-v2 = <&bus_jpeg_opp_table>;
449 devfreq = <&bus_wcore>;
454 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
455 devfreq = <&bus_wcore>;
460 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
461 devfreq = <&bus_wcore>;
466 operating-points-v2 = <&bus_disp1_opp_table>;
467 devfreq = <&bus_wcore>;
472 operating-points-v2 = <&bus_gscl_opp_table>;
473 devfreq = <&bus_wcore>;
478 operating-points-v2 = <&bus_mscl_opp_table>;
479 devfreq = <&bus_wcore>;
484 cpu-supply = <&buck6_reg>;
488 cpu-supply = <&buck2_reg>;
492 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
493 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
494 device-handle = <&samsung_K3QF2F20DB>;
495 operating-points-v2 = <&dmc_opp_table>;
496 vdd-supply = <&buck1_reg>;
504 compatible = "samsung,s2mps11-pmic";
506 samsung,s2mps11-acokb-ground;
508 interrupt-parent = <&gpx0>;
509 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&s2mps11_irq>;
514 s2mps11_osc: clocks {
515 compatible = "samsung,s2mps11-clk";
517 clock-output-names = "s2mps11_ap",
518 "s2mps11_cp", "s2mps11_bt";
523 regulator-name = "vdd_ldo1";
524 regulator-min-microvolt = <1000000>;
525 regulator-max-microvolt = <1000000>;
530 regulator-name = "vdd_ldo2";
531 regulator-min-microvolt = <1800000>;
532 regulator-max-microvolt = <1800000>;
537 regulator-name = "vddq_mmc0";
538 regulator-min-microvolt = <1800000>;
539 regulator-max-microvolt = <1800000>;
543 regulator-name = "vdd_adc";
544 regulator-min-microvolt = <1800000>;
545 regulator-max-microvolt = <1800000>;
547 regulator-state-mem {
548 regulator-off-in-suspend;
553 regulator-name = "vdd_ldo5";
554 regulator-min-microvolt = <1800000>;
555 regulator-max-microvolt = <1800000>;
558 regulator-state-mem {
559 regulator-off-in-suspend;
564 regulator-name = "vdd_ldo6";
565 regulator-min-microvolt = <1000000>;
566 regulator-max-microvolt = <1000000>;
569 regulator-state-mem {
570 regulator-off-in-suspend;
575 regulator-name = "vdd_ldo7";
576 regulator-min-microvolt = <1800000>;
577 regulator-max-microvolt = <1800000>;
580 regulator-state-mem {
581 regulator-off-in-suspend;
586 regulator-name = "vdd_ldo8";
587 regulator-min-microvolt = <1800000>;
588 regulator-max-microvolt = <1800000>;
591 regulator-state-mem {
592 regulator-off-in-suspend;
597 regulator-name = "vdd_ldo9";
598 regulator-min-microvolt = <3000000>;
599 regulator-max-microvolt = <3000000>;
602 regulator-state-mem {
603 regulator-off-in-suspend;
608 regulator-name = "vdd_ldo10";
609 regulator-min-microvolt = <1800000>;
610 regulator-max-microvolt = <1800000>;
613 regulator-state-mem {
614 regulator-off-in-suspend;
619 regulator-name = "vdd_ldo11";
620 regulator-min-microvolt = <1000000>;
621 regulator-max-microvolt = <1000000>;
624 regulator-state-mem {
625 regulator-off-in-suspend;
631 regulator-name = "vdd_ldo12";
632 regulator-min-microvolt = <800000>;
633 regulator-max-microvolt = <2375000>;
637 regulator-name = "vddq_mmc2";
638 regulator-min-microvolt = <1800000>;
639 regulator-max-microvolt = <2800000>;
641 regulator-state-mem {
642 regulator-off-in-suspend;
648 regulator-name = "vdd_ldo14";
649 regulator-min-microvolt = <800000>;
650 regulator-max-microvolt = <3950000>;
654 regulator-name = "vdd_ldo15";
655 regulator-min-microvolt = <3300000>;
656 regulator-max-microvolt = <3300000>;
659 regulator-state-mem {
660 regulator-off-in-suspend;
666 regulator-name = "vdd_ldo16";
667 regulator-min-microvolt = <800000>;
668 regulator-max-microvolt = <3950000>;
672 regulator-name = "vdd_ldo17";
673 regulator-min-microvolt = <3300000>;
674 regulator-max-microvolt = <3300000>;
677 regulator-state-mem {
678 regulator-off-in-suspend;
683 regulator-name = "vdd_emmc_1V8";
684 regulator-min-microvolt = <1800000>;
685 regulator-max-microvolt = <1800000>;
687 regulator-state-mem {
688 regulator-off-in-suspend;
693 regulator-name = "vdd_sd";
694 regulator-min-microvolt = <2800000>;
695 regulator-max-microvolt = <2800000>;
697 regulator-state-mem {
698 regulator-off-in-suspend;
704 regulator-name = "vdd_ldo20";
705 regulator-min-microvolt = <800000>;
706 regulator-max-microvolt = <3950000>;
711 regulator-name = "vdd_ldo21";
712 regulator-min-microvolt = <800000>;
713 regulator-max-microvolt = <3950000>;
718 regulator-name = "vdd_ldo22";
719 regulator-min-microvolt = <800000>;
720 regulator-max-microvolt = <2375000>;
724 regulator-name = "vdd_mifs";
725 regulator-min-microvolt = <1100000>;
726 regulator-max-microvolt = <1100000>;
729 regulator-state-mem {
730 regulator-off-in-suspend;
736 regulator-name = "vdd_ldo24";
737 regulator-min-microvolt = <800000>;
738 regulator-max-microvolt = <3950000>;
743 regulator-name = "vdd_ldo25";
744 regulator-min-microvolt = <800000>;
745 regulator-max-microvolt = <3950000>;
749 /* Used on XU3, XU3-Lite and XU4 */
750 regulator-name = "vdd_ldo26";
751 regulator-min-microvolt = <800000>;
752 regulator-max-microvolt = <3950000>;
754 regulator-state-mem {
755 regulator-off-in-suspend;
760 regulator-name = "vdd_g3ds";
761 regulator-min-microvolt = <1000000>;
762 regulator-max-microvolt = <1000000>;
765 regulator-state-mem {
766 regulator-off-in-suspend;
772 regulator-name = "vdd_ldo28";
773 regulator-min-microvolt = <800000>;
774 regulator-max-microvolt = <3950000>;
776 regulator-state-mem {
777 regulator-off-in-suspend;
783 regulator-name = "vdd_ldo29";
784 regulator-min-microvolt = <800000>;
785 regulator-max-microvolt = <3950000>;
790 regulator-name = "vdd_ldo30";
791 regulator-min-microvolt = <800000>;
792 regulator-max-microvolt = <3950000>;
797 regulator-name = "vdd_ldo31";
798 regulator-min-microvolt = <800000>;
799 regulator-max-microvolt = <3950000>;
804 regulator-name = "vdd_ldo32";
805 regulator-min-microvolt = <800000>;
806 regulator-max-microvolt = <3950000>;
811 regulator-name = "vdd_ldo33";
812 regulator-min-microvolt = <800000>;
813 regulator-max-microvolt = <3950000>;
818 regulator-name = "vdd_ldo34";
819 regulator-min-microvolt = <800000>;
820 regulator-max-microvolt = <3950000>;
825 regulator-name = "vdd_ldo35";
826 regulator-min-microvolt = <800000>;
827 regulator-max-microvolt = <2375000>;
832 regulator-name = "vdd_ldo36";
833 regulator-min-microvolt = <800000>;
834 regulator-max-microvolt = <3950000>;
839 regulator-name = "vdd_ldo37";
840 regulator-min-microvolt = <800000>;
841 regulator-max-microvolt = <3950000>;
846 regulator-name = "vdd_ldo38";
847 regulator-min-microvolt = <800000>;
848 regulator-max-microvolt = <3950000>;
852 regulator-name = "vdd_mif";
853 regulator-min-microvolt = <800000>;
854 regulator-max-microvolt = <1300000>;
858 regulator-state-mem {
859 regulator-off-in-suspend;
864 regulator-name = "vdd_arm";
865 regulator-min-microvolt = <800000>;
866 regulator-max-microvolt = <1500000>;
869 regulator-coupled-with = <&buck3_reg>;
870 regulator-coupled-max-spread = <300000>;
872 regulator-state-mem {
873 regulator-off-in-suspend;
878 regulator-name = "vdd_int";
879 regulator-min-microvolt = <800000>;
880 regulator-max-microvolt = <1400000>;
883 regulator-coupled-with = <&buck2_reg>;
884 regulator-coupled-max-spread = <300000>;
886 regulator-state-mem {
887 regulator-off-in-suspend;
892 regulator-name = "vdd_g3d";
893 regulator-min-microvolt = <800000>;
894 regulator-max-microvolt = <1400000>;
898 regulator-state-mem {
899 regulator-off-in-suspend;
904 regulator-name = "vdd_mem";
905 regulator-min-microvolt = <800000>;
906 regulator-max-microvolt = <1400000>;
912 regulator-name = "vdd_kfc";
913 regulator-min-microvolt = <800000>;
914 regulator-max-microvolt = <1500000>;
918 regulator-state-mem {
919 regulator-off-in-suspend;
924 regulator-name = "vdd_1.35v_ldo";
925 regulator-min-microvolt = <1200000>;
926 regulator-max-microvolt = <1500000>;
932 regulator-name = "vdd_2.0v_ldo";
933 regulator-min-microvolt = <1800000>;
934 regulator-max-microvolt = <2100000>;
940 regulator-name = "vdd_2.8v_ldo";
941 regulator-min-microvolt = <3000000>;
942 regulator-max-microvolt = <3750000>;
946 regulator-state-mem {
947 regulator-off-in-suspend;
952 regulator-name = "vdd_vmem";
953 regulator-min-microvolt = <2850000>;
954 regulator-max-microvolt = <2850000>;
956 regulator-state-mem {
957 regulator-off-in-suspend;
966 card-detect-delay = <200>;
967 samsung,dw-mshc-ciu-div = <3>;
968 samsung,dw-mshc-sdr-timing = <0 4>;
969 samsung,dw-mshc-ddr-timing = <0 2>;
970 pinctrl-names = "default";
971 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
974 max-frequency = <200000000>;
975 vmmc-supply = <&ldo19_reg>;
976 vqmmc-supply = <&ldo13_reg>;
999 s2mps11_irq: s2mps11-irq-pins {
1000 samsung,pins = "gpx0-4";
1001 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1002 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1003 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1024 vtmu-supply = <&ldo7_reg>;
1028 vtmu-supply = <&ldo7_reg>;
1032 vtmu-supply = <&ldo7_reg>;
1036 vtmu-supply = <&ldo7_reg>;
1040 vtmu-supply = <&ldo7_reg>;
1044 mali-supply = <&buck4_reg>;
1050 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1051 clock-names = "rtc", "rtc_src";
1058 /* usbdrd_dwc3_1 mode customized in each board */
1061 vdd33-supply = <&ldo9_reg>;
1062 vdd10-supply = <&ldo11_reg>;
1066 vdd33-supply = <&ldo9_reg>;
1067 vdd10-supply = <&ldo11_reg>;