1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5420 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
9 * EXYNOS5420 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5420", "samsung,exynos5";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
45 cluster_a15_opp_table: opp_table0 {
46 compatible = "operating-points-v2";
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000>;
52 clock-latency-ns = <140000>;
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500>;
57 clock-latency-ns = <140000>;
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000>;
62 clock-latency-ns = <140000>;
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500>;
67 clock-latency-ns = <140000>;
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500>;
72 clock-latency-ns = <140000>;
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500>;
77 clock-latency-ns = <140000>;
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500>;
82 clock-latency-ns = <140000>;
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500>;
87 clock-latency-ns = <140000>;
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500>;
92 clock-latency-ns = <140000>;
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500>;
97 clock-latency-ns = <140000>;
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500>;
102 clock-latency-ns = <140000>;
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp_table1 {
112 compatible = "operating-points-v2";
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
168 reg = <0x4000 0x1000>;
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
173 reg = <0x5000 0x1000>;
177 clock: clock-controller@10010000 {
178 compatible = "samsung,exynos5420-clock";
179 reg = <0x10010000 0x30000>;
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
185 reg = <0x03810000 0x0C>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
193 mfc: codec@11000000 {
194 compatible = "samsung,mfc-v7";
195 reg = <0x11000000 0x10000>;
196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clock CLK_MFC>;
199 power-domains = <&mfc_pd>;
200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
201 iommu-names = "left", "right";
204 mmc_0: mmc@12200000 {
205 compatible = "samsung,exynos5420-dw-mshc-smu";
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
209 reg = <0x12200000 0x2000>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
216 mmc_1: mmc@12210000 {
217 compatible = "samsung,exynos5420-dw-mshc-smu";
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
221 reg = <0x12210000 0x2000>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
228 mmc_2: mmc@12220000 {
229 compatible = "samsung,exynos5420-dw-mshc";
230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
233 reg = <0x12220000 0x1000>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
240 nocp_mem0_0: nocp@10ca1000 {
241 compatible = "samsung,exynos5420-nocp";
242 reg = <0x10CA1000 0x200>;
246 nocp_mem0_1: nocp@10ca1400 {
247 compatible = "samsung,exynos5420-nocp";
248 reg = <0x10CA1400 0x200>;
252 nocp_mem1_0: nocp@10ca1800 {
253 compatible = "samsung,exynos5420-nocp";
254 reg = <0x10CA1800 0x200>;
258 nocp_mem1_1: nocp@10ca1c00 {
259 compatible = "samsung,exynos5420-nocp";
260 reg = <0x10CA1C00 0x200>;
264 nocp_g3d_0: nocp@11a51000 {
265 compatible = "samsung,exynos5420-nocp";
266 reg = <0x11A51000 0x200>;
270 nocp_g3d_1: nocp@11a51400 {
271 compatible = "samsung,exynos5420-nocp";
272 reg = <0x11A51400 0x200>;
276 gsc_pd: power-domain@10044000 {
277 compatible = "samsung,exynos4210-pd";
278 reg = <0x10044000 0x20>;
279 #power-domain-cells = <0>;
283 isp_pd: power-domain@10044020 {
284 compatible = "samsung,exynos4210-pd";
285 reg = <0x10044020 0x20>;
286 #power-domain-cells = <0>;
290 mfc_pd: power-domain@10044060 {
291 compatible = "samsung,exynos4210-pd";
292 reg = <0x10044060 0x20>;
293 #power-domain-cells = <0>;
297 g3d_pd: power-domain@10044080 {
298 compatible = "samsung,exynos4210-pd";
299 reg = <0x10044080 0x20>;
300 #power-domain-cells = <0>;
304 disp_pd: power-domain@100440c0 {
305 compatible = "samsung,exynos4210-pd";
306 reg = <0x100440C0 0x20>;
307 #power-domain-cells = <0>;
311 mau_pd: power-domain@100440e0 {
312 compatible = "samsung,exynos4210-pd";
313 reg = <0x100440E0 0x20>;
314 #power-domain-cells = <0>;
318 msc_pd: power-domain@10044120 {
319 compatible = "samsung,exynos4210-pd";
320 reg = <0x10044120 0x20>;
321 #power-domain-cells = <0>;
325 pinctrl_0: pinctrl@13400000 {
326 compatible = "samsung,exynos5420-pinctrl";
327 reg = <0x13400000 0x1000>;
328 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
330 wakeup-interrupt-controller {
331 compatible = "samsung,exynos4210-wakeup-eint";
332 interrupt-parent = <&gic>;
333 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
337 pinctrl_1: pinctrl@13410000 {
338 compatible = "samsung,exynos5420-pinctrl";
339 reg = <0x13410000 0x1000>;
340 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
343 pinctrl_2: pinctrl@14000000 {
344 compatible = "samsung,exynos5420-pinctrl";
345 reg = <0x14000000 0x1000>;
346 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
349 pinctrl_3: pinctrl@14010000 {
350 compatible = "samsung,exynos5420-pinctrl";
351 reg = <0x14010000 0x1000>;
352 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
355 pinctrl_4: pinctrl@3860000 {
356 compatible = "samsung,exynos5420-pinctrl";
357 reg = <0x03860000 0x1000>;
358 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
359 power-domains = <&mau_pd>;
363 #address-cells = <1>;
365 compatible = "simple-bus";
366 interrupt-parent = <&gic>;
370 compatible = "arm,pl330", "arm,primecell";
371 reg = <0x03880000 0x1000>;
372 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&clock_audss EXYNOS_ADMA>;
374 clock-names = "apb_pclk";
377 #dma-requests = <16>;
378 power-domains = <&mau_pd>;
381 pdma0: pdma@121a0000 {
382 compatible = "arm,pl330", "arm,primecell";
383 reg = <0x121A0000 0x1000>;
384 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clock CLK_PDMA0>;
386 clock-names = "apb_pclk";
389 #dma-requests = <32>;
392 pdma1: pdma@121b0000 {
393 compatible = "arm,pl330", "arm,primecell";
394 reg = <0x121B0000 0x1000>;
395 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clock CLK_PDMA1>;
397 clock-names = "apb_pclk";
400 #dma-requests = <32>;
403 mdma0: mdma@10800000 {
404 compatible = "arm,pl330", "arm,primecell";
405 reg = <0x10800000 0x1000>;
406 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clock CLK_MDMA0>;
408 clock-names = "apb_pclk";
414 mdma1: mdma@11c10000 {
415 compatible = "arm,pl330", "arm,primecell";
416 reg = <0x11C10000 0x1000>;
417 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clock CLK_MDMA1>;
419 clock-names = "apb_pclk";
424 * MDMA1 can support both secure and non-secure
425 * AXI transactions. When this is enabled in
426 * the kernel for boards that run in secure
427 * mode, we are getting imprecise external
428 * aborts causing the kernel to oops.
435 compatible = "samsung,exynos5420-i2s";
436 reg = <0x03830000 0x100>;
440 dma-names = "tx", "rx", "tx-sec";
441 clocks = <&clock_audss EXYNOS_I2S_BUS>,
442 <&clock_audss EXYNOS_I2S_BUS>,
443 <&clock_audss EXYNOS_SCLK_I2S>;
444 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
446 clock-output-names = "i2s_cdclk0";
447 #sound-dai-cells = <1>;
448 samsung,idma-addr = <0x03000000>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&i2s0_bus>;
451 power-domains = <&mau_pd>;
456 compatible = "samsung,exynos5420-i2s";
457 reg = <0x12D60000 0x100>;
460 dma-names = "tx", "rx";
461 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
462 clock-names = "iis", "i2s_opclk0";
464 clock-output-names = "i2s_cdclk1";
465 #sound-dai-cells = <1>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2s1_bus>;
472 compatible = "samsung,exynos5420-i2s";
473 reg = <0x12D70000 0x100>;
476 dma-names = "tx", "rx";
477 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
478 clock-names = "iis", "i2s_opclk0";
480 clock-output-names = "i2s_cdclk2";
481 #sound-dai-cells = <1>;
482 pinctrl-names = "default";
483 pinctrl-0 = <&i2s2_bus>;
487 spi_0: spi@12d20000 {
488 compatible = "samsung,exynos4210-spi";
489 reg = <0x12d20000 0x100>;
490 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
493 dma-names = "tx", "rx";
494 #address-cells = <1>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&spi0_bus>;
498 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
499 clock-names = "spi", "spi_busclk0";
503 spi_1: spi@12d30000 {
504 compatible = "samsung,exynos4210-spi";
505 reg = <0x12d30000 0x100>;
506 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
509 dma-names = "tx", "rx";
510 #address-cells = <1>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&spi1_bus>;
514 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
515 clock-names = "spi", "spi_busclk0";
519 spi_2: spi@12d40000 {
520 compatible = "samsung,exynos4210-spi";
521 reg = <0x12d40000 0x100>;
522 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
525 dma-names = "tx", "rx";
526 #address-cells = <1>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&spi2_bus>;
530 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
531 clock-names = "spi", "spi_busclk0";
535 dp_phy: dp-video-phy {
536 compatible = "samsung,exynos5420-dp-video-phy";
537 samsung,pmu-syscon = <&pmu_system_controller>;
541 mipi_phy: mipi-video-phy {
542 compatible = "samsung,exynos5420-mipi-video-phy";
543 syscon = <&pmu_system_controller>;
548 compatible = "samsung,exynos5410-mipi-dsi";
549 reg = <0x14500000 0x10000>;
550 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
551 phys = <&mipi_phy 1>;
553 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
554 clock-names = "bus_clk", "pll_clk";
555 #address-cells = <1>;
560 hsi2c_8: i2c@12e00000 {
561 compatible = "samsung,exynos5250-hsi2c";
562 reg = <0x12E00000 0x1000>;
563 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c8_hs_bus>;
568 clocks = <&clock CLK_USI4>;
569 clock-names = "hsi2c";
573 hsi2c_9: i2c@12e10000 {
574 compatible = "samsung,exynos5250-hsi2c";
575 reg = <0x12E10000 0x1000>;
576 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c9_hs_bus>;
581 clocks = <&clock CLK_USI5>;
582 clock-names = "hsi2c";
586 hsi2c_10: i2c@12e20000 {
587 compatible = "samsung,exynos5250-hsi2c";
588 reg = <0x12E20000 0x1000>;
589 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
590 #address-cells = <1>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c10_hs_bus>;
594 clocks = <&clock CLK_USI6>;
595 clock-names = "hsi2c";
599 hdmi: hdmi@14530000 {
600 compatible = "samsung,exynos5420-hdmi";
601 reg = <0x14530000 0x70000>;
602 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
604 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
605 <&clock CLK_MOUT_HDMI>;
606 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
607 "sclk_hdmiphy", "mout_hdmi";
609 samsung,syscon-phandle = <&pmu_system_controller>;
611 power-domains = <&disp_pd>;
612 #sound-dai-cells = <0>;
615 hdmiphy: hdmiphy@145d0000 {
616 reg = <0x145D0000 0x20>;
619 hdmicec: cec@101b0000 {
620 compatible = "samsung,s5p-cec";
621 reg = <0x101B0000 0x200>;
622 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clock CLK_HDMI_CEC>;
624 clock-names = "hdmicec";
625 samsung,syscon-phandle = <&pmu_system_controller>;
626 hdmi-phandle = <&hdmi>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&hdmi_cec>;
632 mixer: mixer@14450000 {
633 compatible = "samsung,exynos5420-mixer";
634 reg = <0x14450000 0x10000>;
635 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
637 <&clock CLK_SCLK_HDMI>;
638 clock-names = "mixer", "hdmi", "sclk_hdmi";
639 power-domains = <&disp_pd>;
640 iommus = <&sysmmu_tv>;
644 rotator: rotator@11c00000 {
645 compatible = "samsung,exynos5250-rotator";
646 reg = <0x11C00000 0x64>;
647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clock CLK_ROTATOR>;
649 clock-names = "rotator";
650 iommus = <&sysmmu_rotator>;
653 gsc_0: video-scaler@13e00000 {
654 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
655 reg = <0x13e00000 0x1000>;
656 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clock CLK_GSCL0>;
658 clock-names = "gscl";
659 power-domains = <&gsc_pd>;
660 iommus = <&sysmmu_gscl0>;
663 gsc_1: video-scaler@13e10000 {
664 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
665 reg = <0x13e10000 0x1000>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&clock CLK_GSCL1>;
668 clock-names = "gscl";
669 power-domains = <&gsc_pd>;
670 iommus = <&sysmmu_gscl1>;
673 scaler_0: scaler@12800000 {
674 compatible = "samsung,exynos5420-scaler";
675 reg = <0x12800000 0x1294>;
676 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clock CLK_MSCL0>;
678 clock-names = "mscl";
679 power-domains = <&msc_pd>;
680 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
683 scaler_1: scaler@12810000 {
684 compatible = "samsung,exynos5420-scaler";
685 reg = <0x12810000 0x1294>;
686 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clock CLK_MSCL1>;
688 clock-names = "mscl";
689 power-domains = <&msc_pd>;
690 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
693 scaler_2: scaler@12820000 {
694 compatible = "samsung,exynos5420-scaler";
695 reg = <0x12820000 0x1294>;
696 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&clock CLK_MSCL2>;
698 clock-names = "mscl";
699 power-domains = <&msc_pd>;
700 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
703 jpeg_0: jpeg@11f50000 {
704 compatible = "samsung,exynos5420-jpeg";
705 reg = <0x11F50000 0x1000>;
706 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
707 clock-names = "jpeg";
708 clocks = <&clock CLK_JPEG>;
709 iommus = <&sysmmu_jpeg0>;
712 jpeg_1: jpeg@11f60000 {
713 compatible = "samsung,exynos5420-jpeg";
714 reg = <0x11F60000 0x1000>;
715 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
716 clock-names = "jpeg";
717 clocks = <&clock CLK_JPEG2>;
718 iommus = <&sysmmu_jpeg1>;
721 pmu_system_controller: system-controller@10040000 {
722 compatible = "samsung,exynos5420-pmu", "syscon";
723 reg = <0x10040000 0x5000>;
724 clock-names = "clkout16";
725 clocks = <&clock CLK_FIN_PLL>;
727 interrupt-controller;
728 #interrupt-cells = <3>;
729 interrupt-parent = <&gic>;
732 tmu_cpu0: tmu@10060000 {
733 compatible = "samsung,exynos5420-tmu";
734 reg = <0x10060000 0x100>;
735 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clock CLK_TMU>;
737 clock-names = "tmu_apbif";
738 #thermal-sensor-cells = <0>;
741 tmu_cpu1: tmu@10064000 {
742 compatible = "samsung,exynos5420-tmu";
743 reg = <0x10064000 0x100>;
744 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clock CLK_TMU>;
746 clock-names = "tmu_apbif";
747 #thermal-sensor-cells = <0>;
750 tmu_cpu2: tmu@10068000 {
751 compatible = "samsung,exynos5420-tmu-ext-triminfo";
752 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
753 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
755 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
756 #thermal-sensor-cells = <0>;
759 tmu_cpu3: tmu@1006c000 {
760 compatible = "samsung,exynos5420-tmu-ext-triminfo";
761 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
762 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
764 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
765 #thermal-sensor-cells = <0>;
768 tmu_gpu: tmu@100a0000 {
769 compatible = "samsung,exynos5420-tmu-ext-triminfo";
770 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
771 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
773 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
774 #thermal-sensor-cells = <0>;
777 sysmmu_g2dr: sysmmu@10a60000 {
778 compatible = "samsung,exynos-sysmmu";
779 reg = <0x10A60000 0x1000>;
780 interrupt-parent = <&combiner>;
782 clock-names = "sysmmu", "master";
783 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
787 sysmmu_g2dw: sysmmu@10a70000 {
788 compatible = "samsung,exynos-sysmmu";
789 reg = <0x10A70000 0x1000>;
790 interrupt-parent = <&combiner>;
792 clock-names = "sysmmu", "master";
793 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
797 sysmmu_tv: sysmmu@14650000 {
798 compatible = "samsung,exynos-sysmmu";
799 reg = <0x14650000 0x1000>;
800 interrupt-parent = <&combiner>;
802 clock-names = "sysmmu", "master";
803 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
804 power-domains = <&disp_pd>;
808 sysmmu_gscl0: sysmmu@13e80000 {
809 compatible = "samsung,exynos-sysmmu";
810 reg = <0x13E80000 0x1000>;
811 interrupt-parent = <&combiner>;
813 clock-names = "sysmmu", "master";
814 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
815 power-domains = <&gsc_pd>;
819 sysmmu_gscl1: sysmmu@13e90000 {
820 compatible = "samsung,exynos-sysmmu";
821 reg = <0x13E90000 0x1000>;
822 interrupt-parent = <&combiner>;
824 clock-names = "sysmmu", "master";
825 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
826 power-domains = <&gsc_pd>;
830 sysmmu_scaler0r: sysmmu@12880000 {
831 compatible = "samsung,exynos-sysmmu";
832 reg = <0x12880000 0x1000>;
833 interrupt-parent = <&combiner>;
835 clock-names = "sysmmu", "master";
836 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
837 power-domains = <&msc_pd>;
841 sysmmu_scaler1r: sysmmu@12890000 {
842 compatible = "samsung,exynos-sysmmu";
843 reg = <0x12890000 0x1000>;
844 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "sysmmu", "master";
846 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
847 power-domains = <&msc_pd>;
851 sysmmu_scaler2r: sysmmu@128a0000 {
852 compatible = "samsung,exynos-sysmmu";
853 reg = <0x128A0000 0x1000>;
854 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
855 clock-names = "sysmmu", "master";
856 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
857 power-domains = <&msc_pd>;
861 sysmmu_scaler0w: sysmmu@128c0000 {
862 compatible = "samsung,exynos-sysmmu";
863 reg = <0x128C0000 0x1000>;
864 interrupt-parent = <&combiner>;
866 clock-names = "sysmmu", "master";
867 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
868 power-domains = <&msc_pd>;
872 sysmmu_scaler1w: sysmmu@128d0000 {
873 compatible = "samsung,exynos-sysmmu";
874 reg = <0x128D0000 0x1000>;
875 interrupt-parent = <&combiner>;
877 clock-names = "sysmmu", "master";
878 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
879 power-domains = <&msc_pd>;
883 sysmmu_scaler2w: sysmmu@128e0000 {
884 compatible = "samsung,exynos-sysmmu";
885 reg = <0x128E0000 0x1000>;
886 interrupt-parent = <&combiner>;
888 clock-names = "sysmmu", "master";
889 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
890 power-domains = <&msc_pd>;
894 sysmmu_rotator: sysmmu@11d40000 {
895 compatible = "samsung,exynos-sysmmu";
896 reg = <0x11D40000 0x1000>;
897 interrupt-parent = <&combiner>;
899 clock-names = "sysmmu", "master";
900 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
904 sysmmu_jpeg0: sysmmu@11f10000 {
905 compatible = "samsung,exynos-sysmmu";
906 reg = <0x11F10000 0x1000>;
907 interrupt-parent = <&combiner>;
909 clock-names = "sysmmu", "master";
910 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
914 sysmmu_jpeg1: sysmmu@11f20000 {
915 compatible = "samsung,exynos-sysmmu";
916 reg = <0x11F20000 0x1000>;
917 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
918 clock-names = "sysmmu", "master";
919 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
923 sysmmu_mfc_l: sysmmu@11200000 {
924 compatible = "samsung,exynos-sysmmu";
925 reg = <0x11200000 0x1000>;
926 interrupt-parent = <&combiner>;
928 clock-names = "sysmmu", "master";
929 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
930 power-domains = <&mfc_pd>;
934 sysmmu_mfc_r: sysmmu@11210000 {
935 compatible = "samsung,exynos-sysmmu";
936 reg = <0x11210000 0x1000>;
937 interrupt-parent = <&combiner>;
939 clock-names = "sysmmu", "master";
940 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
941 power-domains = <&mfc_pd>;
945 sysmmu_fimd1_0: sysmmu@14640000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x14640000 0x1000>;
948 interrupt-parent = <&combiner>;
950 clock-names = "sysmmu", "master";
951 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
952 power-domains = <&disp_pd>;
956 sysmmu_fimd1_1: sysmmu@14680000 {
957 compatible = "samsung,exynos-sysmmu";
958 reg = <0x14680000 0x1000>;
959 interrupt-parent = <&combiner>;
961 clock-names = "sysmmu", "master";
962 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
963 power-domains = <&disp_pd>;
967 bus_wcore: bus_wcore {
968 compatible = "samsung,exynos-bus";
969 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
971 operating-points-v2 = <&bus_wcore_opp_table>;
976 compatible = "samsung,exynos-bus";
977 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
979 operating-points-v2 = <&bus_noc_opp_table>;
983 bus_fsys_apb: bus_fsys_apb {
984 compatible = "samsung,exynos-bus";
985 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
987 operating-points-v2 = <&bus_fsys_apb_opp_table>;
992 compatible = "samsung,exynos-bus";
993 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
995 operating-points-v2 = <&bus_fsys_apb_opp_table>;
999 bus_fsys2: bus_fsys2 {
1000 compatible = "samsung,exynos-bus";
1001 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1002 clock-names = "bus";
1003 operating-points-v2 = <&bus_fsys2_opp_table>;
1004 status = "disabled";
1008 compatible = "samsung,exynos-bus";
1009 clocks = <&clock CLK_DOUT_ACLK333>;
1010 clock-names = "bus";
1011 operating-points-v2 = <&bus_mfc_opp_table>;
1012 status = "disabled";
1016 compatible = "samsung,exynos-bus";
1017 clocks = <&clock CLK_DOUT_ACLK266>;
1018 clock-names = "bus";
1019 operating-points-v2 = <&bus_gen_opp_table>;
1020 status = "disabled";
1023 bus_peri: bus_peri {
1024 compatible = "samsung,exynos-bus";
1025 clocks = <&clock CLK_DOUT_ACLK66>;
1026 clock-names = "bus";
1027 operating-points-v2 = <&bus_peri_opp_table>;
1028 status = "disabled";
1032 compatible = "samsung,exynos-bus";
1033 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1034 clock-names = "bus";
1035 operating-points-v2 = <&bus_g2d_opp_table>;
1036 status = "disabled";
1039 bus_g2d_acp: bus_g2d_acp {
1040 compatible = "samsung,exynos-bus";
1041 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1042 clock-names = "bus";
1043 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1044 status = "disabled";
1047 bus_jpeg: bus_jpeg {
1048 compatible = "samsung,exynos-bus";
1049 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1050 clock-names = "bus";
1051 operating-points-v2 = <&bus_jpeg_opp_table>;
1052 status = "disabled";
1055 bus_jpeg_apb: bus_jpeg_apb {
1056 compatible = "samsung,exynos-bus";
1057 clocks = <&clock CLK_DOUT_ACLK166>;
1058 clock-names = "bus";
1059 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1060 status = "disabled";
1063 bus_disp1_fimd: bus_disp1_fimd {
1064 compatible = "samsung,exynos-bus";
1065 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1066 clock-names = "bus";
1067 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1068 status = "disabled";
1071 bus_disp1: bus_disp1 {
1072 compatible = "samsung,exynos-bus";
1073 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1074 clock-names = "bus";
1075 operating-points-v2 = <&bus_disp1_opp_table>;
1076 status = "disabled";
1079 bus_gscl_scaler: bus_gscl_scaler {
1080 compatible = "samsung,exynos-bus";
1081 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1082 clock-names = "bus";
1083 operating-points-v2 = <&bus_gscl_opp_table>;
1084 status = "disabled";
1087 bus_mscl: bus_mscl {
1088 compatible = "samsung,exynos-bus";
1089 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1090 clock-names = "bus";
1091 operating-points-v2 = <&bus_mscl_opp_table>;
1092 status = "disabled";
1095 bus_wcore_opp_table: opp_table2 {
1096 compatible = "operating-points-v2";
1099 opp-hz = /bits/ 64 <84000000>;
1100 opp-microvolt = <925000>;
1103 opp-hz = /bits/ 64 <111000000>;
1104 opp-microvolt = <950000>;
1107 opp-hz = /bits/ 64 <222000000>;
1108 opp-microvolt = <950000>;
1111 opp-hz = /bits/ 64 <333000000>;
1112 opp-microvolt = <950000>;
1115 opp-hz = /bits/ 64 <400000000>;
1116 opp-microvolt = <987500>;
1120 bus_noc_opp_table: opp_table3 {
1121 compatible = "operating-points-v2";
1124 opp-hz = /bits/ 64 <67000000>;
1127 opp-hz = /bits/ 64 <75000000>;
1130 opp-hz = /bits/ 64 <86000000>;
1133 opp-hz = /bits/ 64 <100000000>;
1137 bus_fsys_apb_opp_table: opp_table4 {
1138 compatible = "operating-points-v2";
1142 opp-hz = /bits/ 64 <100000000>;
1145 opp-hz = /bits/ 64 <200000000>;
1149 bus_fsys2_opp_table: opp_table5 {
1150 compatible = "operating-points-v2";
1153 opp-hz = /bits/ 64 <75000000>;
1156 opp-hz = /bits/ 64 <100000000>;
1159 opp-hz = /bits/ 64 <150000000>;
1163 bus_mfc_opp_table: opp_table6 {
1164 compatible = "operating-points-v2";
1167 opp-hz = /bits/ 64 <96000000>;
1170 opp-hz = /bits/ 64 <111000000>;
1173 opp-hz = /bits/ 64 <167000000>;
1176 opp-hz = /bits/ 64 <222000000>;
1179 opp-hz = /bits/ 64 <333000000>;
1183 bus_gen_opp_table: opp_table7 {
1184 compatible = "operating-points-v2";
1187 opp-hz = /bits/ 64 <89000000>;
1190 opp-hz = /bits/ 64 <133000000>;
1193 opp-hz = /bits/ 64 <178000000>;
1196 opp-hz = /bits/ 64 <267000000>;
1200 bus_peri_opp_table: opp_table8 {
1201 compatible = "operating-points-v2";
1204 opp-hz = /bits/ 64 <67000000>;
1208 bus_g2d_opp_table: opp_table9 {
1209 compatible = "operating-points-v2";
1212 opp-hz = /bits/ 64 <84000000>;
1215 opp-hz = /bits/ 64 <167000000>;
1218 opp-hz = /bits/ 64 <222000000>;
1221 opp-hz = /bits/ 64 <300000000>;
1224 opp-hz = /bits/ 64 <333000000>;
1228 bus_g2d_acp_opp_table: opp_table10 {
1229 compatible = "operating-points-v2";
1232 opp-hz = /bits/ 64 <67000000>;
1235 opp-hz = /bits/ 64 <133000000>;
1238 opp-hz = /bits/ 64 <178000000>;
1241 opp-hz = /bits/ 64 <267000000>;
1245 bus_jpeg_opp_table: opp_table11 {
1246 compatible = "operating-points-v2";
1249 opp-hz = /bits/ 64 <75000000>;
1252 opp-hz = /bits/ 64 <150000000>;
1255 opp-hz = /bits/ 64 <200000000>;
1258 opp-hz = /bits/ 64 <300000000>;
1262 bus_jpeg_apb_opp_table: opp_table12 {
1263 compatible = "operating-points-v2";
1266 opp-hz = /bits/ 64 <84000000>;
1269 opp-hz = /bits/ 64 <111000000>;
1272 opp-hz = /bits/ 64 <134000000>;
1275 opp-hz = /bits/ 64 <167000000>;
1279 bus_disp1_fimd_opp_table: opp_table13 {
1280 compatible = "operating-points-v2";
1283 opp-hz = /bits/ 64 <120000000>;
1286 opp-hz = /bits/ 64 <200000000>;
1290 bus_disp1_opp_table: opp_table14 {
1291 compatible = "operating-points-v2";
1294 opp-hz = /bits/ 64 <120000000>;
1297 opp-hz = /bits/ 64 <200000000>;
1300 opp-hz = /bits/ 64 <300000000>;
1304 bus_gscl_opp_table: opp_table15 {
1305 compatible = "operating-points-v2";
1308 opp-hz = /bits/ 64 <150000000>;
1311 opp-hz = /bits/ 64 <200000000>;
1314 opp-hz = /bits/ 64 <300000000>;
1318 bus_mscl_opp_table: opp_table16 {
1319 compatible = "operating-points-v2";
1322 opp-hz = /bits/ 64 <84000000>;
1325 opp-hz = /bits/ 64 <167000000>;
1328 opp-hz = /bits/ 64 <222000000>;
1331 opp-hz = /bits/ 64 <333000000>;
1334 opp-hz = /bits/ 64 <400000000>;
1340 cpu0_thermal: cpu0-thermal {
1341 thermal-sensors = <&tmu_cpu0>;
1342 #include "exynos5420-trip-points.dtsi"
1344 cpu1_thermal: cpu1-thermal {
1345 thermal-sensors = <&tmu_cpu1>;
1346 #include "exynos5420-trip-points.dtsi"
1348 cpu2_thermal: cpu2-thermal {
1349 thermal-sensors = <&tmu_cpu2>;
1350 #include "exynos5420-trip-points.dtsi"
1352 cpu3_thermal: cpu3-thermal {
1353 thermal-sensors = <&tmu_cpu3>;
1354 #include "exynos5420-trip-points.dtsi"
1356 gpu_thermal: gpu-thermal {
1357 thermal-sensors = <&tmu_gpu>;
1358 #include "exynos5420-trip-points.dtsi"
1364 clocks = <&clock CLK_TSADC>;
1365 clock-names = "adc";
1366 samsung,syscon-phandle = <&pmu_system_controller>;
1370 clocks = <&clock CLK_DP1>;
1374 power-domains = <&disp_pd>;
1378 compatible = "samsung,exynos5420-fimd";
1379 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1380 clock-names = "sclk_fimd", "fimd";
1381 power-domains = <&disp_pd>;
1382 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1383 iommu-names = "m0", "m1";
1387 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1388 clocks = <&clock CLK_G2D>;
1389 clock-names = "fimg2d";
1394 clocks = <&clock CLK_I2C0>;
1395 clock-names = "i2c";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&i2c0_bus>;
1401 clocks = <&clock CLK_I2C1>;
1402 clock-names = "i2c";
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&i2c1_bus>;
1408 clocks = <&clock CLK_I2C2>;
1409 clock-names = "i2c";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&i2c2_bus>;
1415 clocks = <&clock CLK_I2C3>;
1416 clock-names = "i2c";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&i2c3_bus>;
1422 clocks = <&clock CLK_USI0>;
1423 clock-names = "hsi2c";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&i2c4_hs_bus>;
1429 clocks = <&clock CLK_USI1>;
1430 clock-names = "hsi2c";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&i2c5_hs_bus>;
1436 clocks = <&clock CLK_USI2>;
1437 clock-names = "hsi2c";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&i2c6_hs_bus>;
1443 clocks = <&clock CLK_USI3>;
1444 clock-names = "hsi2c";
1445 pinctrl-names = "default";
1446 pinctrl-0 = <&i2c7_hs_bus>;
1450 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1451 clock-names = "fin_pll", "mct";
1455 clocks = <&clock CLK_SSS>;
1456 clock-names = "secss";
1460 clocks = <&clock CLK_PWM>;
1461 clock-names = "timers";
1465 clocks = <&clock CLK_RTC>;
1466 clock-names = "rtc";
1467 interrupt-parent = <&pmu_system_controller>;
1468 status = "disabled";
1472 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1473 clock-names = "uart", "clk_uart_baud0";
1474 dmas = <&pdma0 13>, <&pdma0 14>;
1475 dma-names = "rx", "tx";
1479 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1480 clock-names = "uart", "clk_uart_baud0";
1481 dmas = <&pdma1 15>, <&pdma1 16>;
1482 dma-names = "rx", "tx";
1486 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1487 clock-names = "uart", "clk_uart_baud0";
1488 dmas = <&pdma0 15>, <&pdma0 16>;
1489 dma-names = "rx", "tx";
1493 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1494 clock-names = "uart", "clk_uart_baud0";
1495 dmas = <&pdma1 17>, <&pdma1 18>;
1496 dma-names = "rx", "tx";
1500 clocks = <&clock CLK_SSS>;
1501 clock-names = "secss";
1505 clocks = <&clock CLK_SSS>;
1506 clock-names = "secss";
1510 clocks = <&clock CLK_USBD300>;
1511 clock-names = "usbdrd30";
1515 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1516 clock-names = "phy", "ref";
1517 samsung,pmu-syscon = <&pmu_system_controller>;
1521 clocks = <&clock CLK_USBD301>;
1522 clock-names = "usbdrd30";
1526 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1531 clock-names = "phy", "ref";
1532 samsung,pmu-syscon = <&pmu_system_controller>;
1536 clocks = <&clock CLK_USBH20>;
1537 clock-names = "usbhost";
1541 clocks = <&clock CLK_USBH20>;
1542 clock-names = "usbhost";
1546 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1547 clock-names = "phy", "ref";
1548 samsung,sysreg-phandle = <&sysreg_system_controller>;
1549 samsung,pmureg-phandle = <&pmu_system_controller>;
1553 clocks = <&clock CLK_WDT>;
1554 clock-names = "watchdog";
1555 samsung,syscon-phandle = <&pmu_system_controller>;
1558 #include "exynos5420-pinctrl.dtsi"
1559 #include "exynos-syscon-restart.dtsi"