2 * SAMSUNG EXYNOS5420 SoC cpu device tree source
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This file provides desired ordering for Exynos5420 and Exynos5800
8 * boards: CPU[0123] being the A15.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
11 * but particular boards choose different booting order.
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
30 compatible = "arm,cortex-a15";
32 clocks = <&clock CLK_ARM_CLK>;
33 clock-frequency = <1800000000>;
34 cci-control-port = <&cci_control1>;
35 operating-points-v2 = <&cluster_a15_opp_table>;
36 #cooling-cells = <2>; /* min followed by max */
41 compatible = "arm,cortex-a15";
43 clock-frequency = <1800000000>;
44 cci-control-port = <&cci_control1>;
45 operating-points-v2 = <&cluster_a15_opp_table>;
46 #cooling-cells = <2>; /* min followed by max */
51 compatible = "arm,cortex-a15";
53 clock-frequency = <1800000000>;
54 cci-control-port = <&cci_control1>;
55 operating-points-v2 = <&cluster_a15_opp_table>;
56 #cooling-cells = <2>; /* min followed by max */
61 compatible = "arm,cortex-a15";
63 clock-frequency = <1800000000>;
64 cci-control-port = <&cci_control1>;
65 operating-points-v2 = <&cluster_a15_opp_table>;
66 #cooling-cells = <2>; /* min followed by max */
71 compatible = "arm,cortex-a7";
73 clocks = <&clock CLK_KFC_CLK>;
74 clock-frequency = <1000000000>;
75 cci-control-port = <&cci_control0>;
76 operating-points-v2 = <&cluster_a7_opp_table>;
77 #cooling-cells = <2>; /* min followed by max */
82 compatible = "arm,cortex-a7";
84 clock-frequency = <1000000000>;
85 cci-control-port = <&cci_control0>;
86 operating-points-v2 = <&cluster_a7_opp_table>;
87 #cooling-cells = <2>; /* min followed by max */
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
96 operating-points-v2 = <&cluster_a7_opp_table>;
97 #cooling-cells = <2>; /* min followed by max */
102 compatible = "arm,cortex-a7";
104 clock-frequency = <1000000000>;
105 cci-control-port = <&cci_control0>;
106 operating-points-v2 = <&cluster_a7_opp_table>;
107 #cooling-cells = <2>; /* min followed by max */