arch/arm/boot/dts/exynos5410.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5410 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5410 SoC device nodes are listed in this file.
   9  * Exynos5410 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include <dt-bindings/clock/exynos5410.h>
  15 #include <dt-bindings/clock/exynos-audss-clk.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "samsung,exynos5410", "samsung,exynos5";
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 pinctrl0 = &pinctrl_0;
  24                 pinctrl1 = &pinctrl_1;
  25                 pinctrl2 = &pinctrl_2;
  26                 pinctrl3 = &pinctrl_3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0x0>;
  37                         clock-frequency = <1600000000>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x1>;
  44                         clock-frequency = <1600000000>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0x2>;
  51                         clock-frequency = <1600000000>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a15";
  57                         reg = <0x3>;
  58                         clock-frequency = <1600000000>;
  59                 };
  60         };
  61
  62         soc: soc {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67
  68                 pmu_system_controller: system-controller@10040000 {
  69                         compatible = "samsung,exynos5410-pmu", "syscon";
  70                         reg = <0x10040000 0x5000>;
  71                         clock-names = "clkout16";
  72                         clocks = <&fin_pll>;
  73                         #clock-cells = <1>;
  74                 };
  75
  76                 clock: clock-controller@10010000 {
  77                         compatible = "samsung,exynos5410-clock";
  78                         reg = <0x10010000 0x30000>;
  79                         #clock-cells = <1>;
  80                 };
  81
  82                 clock_audss: audss-clock-controller@3810000 {
  83                         compatible = "samsung,exynos5410-audss-clock";
  84                         reg = <0x03810000 0x0C>;
  85                         #clock-cells = <1>;
  86                         clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
  87                         clock-names = "pll_ref", "pll_in";
  88                 };
  89
  90                 tmu_cpu0: tmu@10060000 {
  91                         compatible = "samsung,exynos5420-tmu";
  92                         reg = <0x10060000 0x100>;
  93                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  94                         clocks = <&clock CLK_TMU>;
  95                         clock-names = "tmu_apbif";
  96                         #thermal-sensor-cells = <0>;
  97                 };
  98
  99                 tmu_cpu1: tmu@10064000 {
 100                         compatible = "samsung,exynos5420-tmu";
 101                         reg = <0x10064000 0x100>;
 102                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&clock CLK_TMU>;
 104                         clock-names = "tmu_apbif";
 105                         #thermal-sensor-cells = <0>;
 106                 };
 107
 108                 tmu_cpu2: tmu@10068000 {
 109                         compatible = "samsung,exynos5420-tmu";
 110                         reg = <0x10068000 0x100>;
 111                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&clock CLK_TMU>;
 113                         clock-names = "tmu_apbif";
 114                         #thermal-sensor-cells = <0>;
 115                 };
 116
 117                 tmu_cpu3: tmu@1006c000 {
 118                         compatible = "samsung,exynos5420-tmu";
 119                         reg = <0x1006c000 0x100>;
 120                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&clock CLK_TMU>;
 122                         clock-names = "tmu_apbif";
 123                         #thermal-sensor-cells = <0>;
 124                 };
 125
 126                 mmc_0: mmc@12200000 {
 127                         compatible = "samsung,exynos5250-dw-mshc";
 128                         reg = <0x12200000 0x1000>;
 129                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 133                         clock-names = "biu", "ciu";
 134                         fifo-depth = <0x80>;
 135                         status = "disabled";
 136                 };
 137
 138                 mmc_1: mmc@12210000 {
 139                         compatible = "samsung,exynos5250-dw-mshc";
 140                         reg = <0x12210000 0x1000>;
 141                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 145                         clock-names = "biu", "ciu";
 146                         fifo-depth = <0x80>;
 147                         status = "disabled";
 148                 };
 149
 150                 mmc_2: mmc@12220000 {
 151                         compatible = "samsung,exynos5250-dw-mshc";
 152                         reg = <0x12220000 0x1000>;
 153                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 157                         clock-names = "biu", "ciu";
 158                         fifo-depth = <0x80>;
 159                         status = "disabled";
 160                 };
 161
 162                 pinctrl_0: pinctrl@13400000 {
 163                         compatible = "samsung,exynos5410-pinctrl";
 164                         reg = <0x13400000 0x1000>;
 165                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 166
 167                         wakeup-interrupt-controller {
 168                                 compatible = "samsung,exynos4210-wakeup-eint";
 169                                 interrupt-parent = <&gic>;
 170                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 171                         };
 172                 };
 173
 174                 pinctrl_1: pinctrl@14000000 {
 175                         compatible = "samsung,exynos5410-pinctrl";
 176                         reg = <0x14000000 0x1000>;
 177                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 178                 };
 179
 180                 pinctrl_2: pinctrl@10d10000 {
 181                         compatible = "samsung,exynos5410-pinctrl";
 182                         reg = <0x10d10000 0x1000>;
 183                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 184                 };
 185
 186                 pinctrl_3: pinctrl@3860000 {
 187                         compatible = "samsung,exynos5410-pinctrl";
 188                         reg = <0x03860000 0x1000>;
 189                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 190                 };
 191
 192                 pdma0: dma-controller@121a0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x121a0000 0x1000>;
 195                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&clock CLK_PDMA0>;
 197                         clock-names = "apb_pclk";
 198                         #dma-cells = <1>;
 199                 };
 200
 201                 pdma1: dma-controller@121b0000 {
 202                         compatible = "arm,pl330", "arm,primecell";
 203                         reg = <0x121b0000 0x1000>;
 204                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 205                         clocks = <&clock CLK_PDMA1>;
 206                         clock-names = "apb_pclk";
 207                         #dma-cells = <1>;
 208                 };
 209
 210                 audi2s0: i2s@3830000 {
 211                         compatible = "samsung,exynos5420-i2s";
 212                         reg = <0x03830000 0x100>;
 213                         dmas = <&pdma0 10>,
 214                                 <&pdma0 9>,
 215                                 <&pdma0 8>;
 216                         dma-names = "tx", "rx", "tx-sec";
 217                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 218                                 <&clock_audss EXYNOS_I2S_BUS>,
 219                                 <&clock_audss EXYNOS_SCLK_I2S>;
 220                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 221                         #clock-cells = <1>;
 222                         clock-output-names = "i2s_cdclk0";
 223                         #sound-dai-cells = <1>;
 224                         samsung,idma-addr = <0x03000000>;
 225                         pinctrl-names = "default";
 226                         pinctrl-0 = <&audi2s0_bus>;
 227                         status = "disabled";
 228                 };
 229         };
 230
 231         thermal-zones {
 232                 cpu0_thermal: cpu0-thermal {
 233                         thermal-sensors = <&tmu_cpu0>;
 234                         #include "exynos5420-trip-points.dtsi"
 235                 };
 236                 cpu1_thermal: cpu1-thermal {
 237                         thermal-sensors = <&tmu_cpu1>;
 238                         #include "exynos5420-trip-points.dtsi"
 239                 };
 240                 cpu2_thermal: cpu2-thermal {
 241                         thermal-sensors = <&tmu_cpu2>;
 242                         #include "exynos5420-trip-points.dtsi"
 243                 };
 244                 cpu3_thermal: cpu3-thermal {
 245                         thermal-sensors = <&tmu_cpu3>;
 246                         #include "exynos5420-trip-points.dtsi"
 247                 };
 248         };
 249 };
 250
 251 &adc {
 252         clocks = <&clock CLK_TSADC>;
 253         clock-names = "adc";
 254         samsung,syscon-phandle = <&pmu_system_controller>;
 255 };
 256
 257 &arm_a15_pmu {
 258         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 259         status = "okay";
 260 };
 261
 262 &i2c_0 {
 263         clocks = <&clock CLK_I2C0>;
 264         clock-names = "i2c";
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&i2c0_bus>;
 267 };
 268
 269 &i2c_1 {
 270         clocks = <&clock CLK_I2C1>;
 271         clock-names = "i2c";
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&i2c1_bus>;
 274 };
 275
 276 &i2c_2 {
 277         clocks = <&clock CLK_I2C2>;
 278         clock-names = "i2c";
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&i2c2_bus>;
 281 };
 282
 283 &i2c_3 {
 284         clocks = <&clock CLK_I2C3>;
 285         clock-names = "i2c";
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&i2c3_bus>;
 288 };
 289
 290 &hsi2c_4 {
 291         clocks = <&clock CLK_USI0>;
 292         clock-names = "hsi2c";
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&i2c4_hs_bus>;
 295 };
 296
 297 &hsi2c_5 {
 298         clocks = <&clock CLK_USI1>;
 299         clock-names = "hsi2c";
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&i2c5_hs_bus>;
 302 };
 303
 304 &hsi2c_6 {
 305         clocks = <&clock CLK_USI2>;
 306         clock-names = "hsi2c";
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&i2c6_hs_bus>;
 309 };
 310
 311 &hsi2c_7 {
 312         clocks = <&clock CLK_USI3>;
 313         clock-names = "hsi2c";
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&i2c7_hs_bus>;
 316 };
 317
 318 &mct {
 319         clocks = <&fin_pll>, <&clock CLK_MCT>;
 320         clock-names = "fin_pll", "mct";
 321 };
 322
 323 &prng {
 324         clocks = <&clock CLK_SSS>;
 325         clock-names = "secss";
 326 };
 327
 328 &pwm {
 329         clocks = <&clock CLK_PWM>;
 330         clock-names = "timers";
 331 };
 332
 333 &rtc {
 334         clocks = <&clock CLK_RTC>;
 335         clock-names = "rtc";
 336         status = "disabled";
 337 };
 338
 339 &serial_0 {
 340         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 341         clock-names = "uart", "clk_uart_baud0";
 342         dmas = <&pdma0 13>, <&pdma0 14>;
 343         dma-names = "rx", "tx";
 344 };
 345
 346 &serial_1 {
 347         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 348         clock-names = "uart", "clk_uart_baud0";
 349         dmas = <&pdma1 15>, <&pdma1 16>;
 350         dma-names = "rx", "tx";
 351 };
 352
 353 &serial_2 {
 354         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 355         clock-names = "uart", "clk_uart_baud0";
 356         dmas = <&pdma0 15>, <&pdma0 16>;
 357         dma-names = "rx", "tx";
 358 };
 359
 360 &serial_3 {
 361         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 362         clock-names = "uart", "clk_uart_baud0";
 363         dmas = <&pdma1 17>, <&pdma1 18>;
 364         dma-names = "rx", "tx";
 365 };
 366
 367 &sss {
 368         clocks = <&clock CLK_SSS>;
 369         clock-names = "secss";
 370 };
 371
 372 &sromc {
 373         #address-cells = <2>;
 374         #size-cells = <1>;
 375         ranges = <0 0 0x04000000 0x20000
 376                   1 0 0x05000000 0x20000
 377                   2 0 0x06000000 0x20000
 378                   3 0 0x07000000 0x20000>;
 379 };
 380
 381 &trng {
 382         clocks = <&clock CLK_SSS>;
 383         clock-names = "secss";
 384 };
 385
 386 &usbdrd3_0 {
 387         clocks = <&clock CLK_USBD300>;
 388         clock-names = "usbdrd30";
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
 391 };
 392
 393 &usbdrd_phy0 {
 394         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 395         clock-names = "phy", "ref";
 396         samsung,pmu-syscon = <&pmu_system_controller>;
 397 };
 398
 399 &usbdrd3_1 {
 400         clocks = <&clock CLK_USBD301>;
 401         clock-names = "usbdrd30";
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
 404 };
 405
 406 &usbdrd_dwc3_1 {
 407         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 408 };
 409
 410 &usbdrd_phy1 {
 411         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 412         clock-names = "phy", "ref";
 413         samsung,pmu-syscon = <&pmu_system_controller>;
 414 };
 415
 416 &usbhost1 {
 417         clocks = <&clock CLK_USBH20>;
 418         clock-names = "usbhost";
 419 };
 420
 421 &usbhost2 {
 422         clocks = <&clock CLK_USBH20>;
 423         clock-names = "usbhost";
 424 };
 425
 426 &usb2_phy {
 427         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 428         clock-names = "phy", "ref";
 429         samsung,sysreg-phandle = <&sysreg_system_controller>;
 430         samsung,pmureg-phandle = <&pmu_system_controller>;
 431 };
 432
 433 &watchdog {
 434         clocks = <&clock CLK_WDT>;
 435         clock-names = "watchdog";
 436         samsung,syscon-phandle = <&pmu_system_controller>;
 437 };
 438
 439 #include "exynos5410-pinctrl.dtsi"
 440 #include "exynos-syscon-restart.dtsi"