arch/arm/boot/dts/exynos5260.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5260 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  */
   8
   9 #include <dt-bindings/clock/exynos5260-clk.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         compatible = "samsung,exynos5260", "samsung,exynos5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 i2c0 = &hsi2c_0;
  21                 i2c1 = &hsi2c_1;
  22                 i2c2 = &hsi2c_2;
  23                 i2c3 = &hsi2c_3;
  24                 pinctrl0 = &pinctrl_0;
  25                 pinctrl1 = &pinctrl_1;
  26                 pinctrl2 = &pinctrl_2;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu-map {
  38                         cluster0 {
  39                                 core0 {
  40                                         cpu = <&cpu0>;
  41                                 };
  42                                 core1 {
  43                                         cpu = <&cpu1>;
  44                                 };
  45                         };
  46
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&cpu2>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&cpu3>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&cpu4>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&cpu5>;
  59                                 };
  60                         };
  61                 };
  62
  63                 cpu0: cpu@0 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a15";
  66                         reg = <0x0>;
  67                         cci-control-port = <&cci_control1>;
  68                 };
  69
  70                 cpu1: cpu@1 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a15";
  73                         reg = <0x1>;
  74                         cci-control-port = <&cci_control1>;
  75                 };
  76
  77                 cpu2: cpu@100 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0x100>;
  81                         cci-control-port = <&cci_control0>;
  82                 };
  83
  84                 cpu3: cpu@101 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0x101>;
  88                         cci-control-port = <&cci_control0>;
  89                 };
  90
  91                 cpu4: cpu@102 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a7";
  94                         reg = <0x102>;
  95                         cci-control-port = <&cci_control0>;
  96                 };
  97
  98                 cpu5: cpu@103 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x103>;
 102                         cci-control-port = <&cci_control0>;
 103                 };
 104         };
 105
 106         soc: soc {
 107                 compatible = "simple-bus";
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 ranges;
 111
 112                 clock_top: clock-controller@10010000 {
 113                         compatible = "samsung,exynos5260-clock-top";
 114                         reg = <0x10010000 0x10000>;
 115                         #clock-cells = <1>;
 116                         clocks = <&fin_pll>,
 117                                  <&clock_mif MIF_DOUT_MEM_PLL>,
 118                                  <&clock_mif MIF_DOUT_BUS_PLL>,
 119                                  <&clock_mif MIF_DOUT_MEDIA_PLL>;
 120                         clock-names = "fin_pll",
 121                                       "dout_mem_pll",
 122                                       "dout_bus_pll",
 123                                       "dout_media_pll";
 124                 };
 125
 126                 clock_peri: clock-controller@10200000 {
 127                         compatible = "samsung,exynos5260-clock-peri";
 128                         reg = <0x10200000 0x10000>;
 129                         #clock-cells = <1>;
 130                         clocks = <&fin_pll>,
 131                                  <&ioclk_pcm>,
 132                                  <&ioclk_i2s>,
 133                                  <&ioclk_spdif>,
 134                                  <&fin_pll>,
 135                                  <&clock_top TOP_DOUT_ACLK_PERI_66>,
 136                                  <&clock_top TOP_DOUT_SCLK_PERI_UART0>,
 137                                  <&clock_top TOP_DOUT_SCLK_PERI_UART1>,
 138                                  <&clock_top TOP_DOUT_SCLK_PERI_UART2>,
 139                                  <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
 140                                  <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
 141                                  <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
 142                                  <&clock_top TOP_DOUT_ACLK_PERI_AUD>;
 143                         clock-names = "fin_pll",
 144                                       "ioclk_pcm_extclk",
 145                                       "ioclk_i2s_cdclk",
 146                                       "ioclk_spdif_extclk",
 147                                       "phyclk_hdmi_phy_ref_cko",
 148                                       "dout_aclk_peri_66",
 149                                       "dout_sclk_peri_uart0",
 150                                       "dout_sclk_peri_uart1",
 151                                       "dout_sclk_peri_uart2",
 152                                       "dout_sclk_peri_spi0_b",
 153                                       "dout_sclk_peri_spi1_b",
 154                                       "dout_sclk_peri_spi2_b",
 155                                       "dout_aclk_peri_aud";
 156                 };
 157
 158                 clock_egl: clock-controller@10600000 {
 159                         compatible = "samsung,exynos5260-clock-egl";
 160                         reg = <0x10600000 0x10000>;
 161                         #clock-cells = <1>;
 162                         clocks = <&fin_pll>,
 163                                  <&clock_mif MIF_DOUT_BUS_PLL>;
 164                         clock-names = "fin_pll",
 165                                       "dout_bus_pll";
 166                 };
 167
 168                 clock_kfc: clock-controller@10700000 {
 169                         compatible = "samsung,exynos5260-clock-kfc";
 170                         reg = <0x10700000 0x10000>;
 171                         #clock-cells = <1>;
 172                         clocks = <&fin_pll>,
 173                                  <&clock_mif MIF_DOUT_MEDIA_PLL>;
 174                         clock-names = "fin_pll",
 175                                       "dout_media_pll";
 176                 };
 177
 178                 clock_g2d: clock-controller@10a00000 {
 179                         compatible = "samsung,exynos5260-clock-g2d";
 180                         reg = <0x10A00000 0x10000>;
 181                         #clock-cells = <1>;
 182                         clocks = <&fin_pll>,
 183                                  <&clock_top TOP_DOUT_ACLK_G2D_333>;
 184                         clock-names = "fin_pll",
 185                                       "dout_aclk_g2d_333";
 186                 };
 187
 188                 clock_mif: clock-controller@10ce0000 {
 189                         compatible = "samsung,exynos5260-clock-mif";
 190                         reg = <0x10CE0000 0x10000>;
 191                         #clock-cells = <1>;
 192                         clocks = <&fin_pll>;
 193                         clock-names = "fin_pll";
 194                 };
 195
 196                 clock_mfc: clock-controller@11090000 {
 197                         compatible = "samsung,exynos5260-clock-mfc";
 198                         reg = <0x11090000 0x10000>;
 199                         #clock-cells = <1>;
 200                         clocks = <&fin_pll>,
 201                                  <&clock_top TOP_DOUT_ACLK_MFC_333>;
 202                         clock-names = "fin_pll",
 203                                       "dout_aclk_mfc_333";
 204                 };
 205
 206                 clock_g3d: clock-controller@11830000 {
 207                         compatible = "samsung,exynos5260-clock-g3d";
 208                         reg = <0x11830000 0x10000>;
 209                         #clock-cells = <1>;
 210                         clocks = <&fin_pll>;
 211                         clock-names = "fin_pll";
 212                 };
 213
 214                 clock_fsys: clock-controller@122e0000 {
 215                         compatible = "samsung,exynos5260-clock-fsys";
 216                         reg = <0x122E0000 0x10000>;
 217                         #clock-cells = <1>;
 218                         clocks = <&fin_pll>,
 219                                  <&fin_pll>,
 220                                  <&fin_pll>,
 221                                  <&fin_pll>,
 222                                  <&fin_pll>,
 223                                  <&fin_pll>,
 224                                  <&clock_top TOP_DOUT_ACLK_FSYS_200>;
 225                         clock-names = "fin_pll",
 226                                       "phyclk_usbhost20_phy_phyclock",
 227                                       "phyclk_usbhost20_phy_freeclk",
 228                                       "phyclk_usbhost20_phy_clk48mohci",
 229                                       "phyclk_usbdrd30_udrd30_pipe_pclk",
 230                                       "phyclk_usbdrd30_udrd30_phyclock",
 231                                       "dout_aclk_fsys_200";
 232                 };
 233
 234                 clock_aud: clock-controller@128c0000 {
 235                         compatible = "samsung,exynos5260-clock-aud";
 236                         reg = <0x128C0000 0x10000>;
 237                         #clock-cells = <1>;
 238                         clocks = <&fin_pll>,
 239                                  <&clock_top TOP_FOUT_AUD_PLL>,
 240                                  <&ioclk_i2s>,
 241                                  <&ioclk_pcm>;
 242                         clock-names = "fin_pll",
 243                                       "fout_aud_pll",
 244                                       "ioclk_i2s_cdclk",
 245                                       "ioclk_pcm_extclk";
 246                 };
 247
 248                 clock_isp: clock-controller@133c0000 {
 249                         compatible = "samsung,exynos5260-clock-isp";
 250                         reg = <0x133C0000 0x10000>;
 251                         #clock-cells = <1>;
 252                         clocks = <&fin_pll>,
 253                                  <&clock_top TOP_DOUT_ACLK_ISP1_266>,
 254                                  <&clock_top TOP_DOUT_ACLK_ISP1_400>,
 255                                  <&clock_top TOP_MOUT_ACLK_ISP1_266>;
 256                         clock-names = "fin_pll",
 257                                       "dout_aclk_isp1_266",
 258                                       "dout_aclk_isp1_400",
 259                                       "mout_aclk_isp1_266";
 260                 };
 261
 262                 clock_gscl: clock-controller@13f00000 {
 263                         compatible = "samsung,exynos5260-clock-gscl";
 264                         reg = <0x13F00000 0x10000>;
 265                         #clock-cells = <1>;
 266                         clocks = <&fin_pll>,
 267                                  <&clock_top TOP_DOUT_ACLK_GSCL_400>,
 268                                  <&clock_top TOP_DOUT_ACLK_GSCL_333>;
 269                         clock-names = "fin_pll",
 270                                       "dout_aclk_gscl_400",
 271                                       "dout_aclk_gscl_333";
 272                 };
 273
 274                 clock_disp: clock-controller@14550000 {
 275                         compatible = "samsung,exynos5260-clock-disp";
 276                         reg = <0x14550000 0x10000>;
 277                         #clock-cells = <1>;
 278                         clocks = <&fin_pll>,
 279                                  <&fin_pll>,
 280                                  <&fin_pll>,
 281                                  <&fin_pll>,
 282                                  <&fin_pll>,
 283                                  <&fin_pll>,
 284                                  <&fin_pll>,
 285                                  <&fin_pll>,
 286                                  <&fin_pll>,
 287                                  <&fin_pll>,
 288                                  <&fin_pll>,
 289                                  <&fin_pll>,
 290                                  <&fin_pll>,
 291                                  <&fin_pll>,
 292                                  <&ioclk_spdif>,
 293                                  <&clock_top TOP_DOUT_ACLK_PERI_AUD>,
 294                                  <&clock_top TOP_DOUT_ACLK_DISP_222>,
 295                                  <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
 296                                  <&clock_top TOP_DOUT_ACLK_DISP_333>;
 297                         clock-names = "fin_pll",
 298                                       "phyclk_dptx_phy_ch3_txd_clk",
 299                                       "phyclk_dptx_phy_ch2_txd_clk",
 300                                       "phyclk_dptx_phy_ch1_txd_clk",
 301                                       "phyclk_dptx_phy_ch0_txd_clk",
 302                                       "phyclk_hdmi_phy_tmds_clko",
 303                                       "phyclk_hdmi_phy_ref_clko",
 304                                       "phyclk_hdmi_phy_pixel_clko",
 305                                       "phyclk_hdmi_link_o_tmds_clkhi",
 306                                       "phyclk_mipi_dphy_4l_m_txbyte_clkhs",
 307                                       "phyclk_dptx_phy_o_ref_clk_24m",
 308                                       "phyclk_dptx_phy_clk_div2",
 309                                       "phyclk_mipi_dphy_4l_m_rxclkesc0",
 310                                       "phyclk_hdmi_phy_ref_cko",
 311                                       "ioclk_spdif_extclk",
 312                                       "dout_aclk_peri_aud",
 313                                       "dout_aclk_disp_222",
 314                                       "dout_sclk_disp_pixel",
 315                                       "dout_aclk_disp_333";
 316                 };
 317
 318                 gic: interrupt-controller@10481000 {
 319                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 320                         #interrupt-cells = <3>;
 321                         interrupt-controller;
 322                         reg = <0x10481000 0x1000>,
 323                                 <0x10482000 0x2000>,
 324                                 <0x10484000 0x2000>,
 325                                 <0x10486000 0x2000>;
 326                         interrupts = <GIC_PPI 9
 327                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 328                 };
 329
 330                 chipid: chipid@10000000 {
 331                         compatible = "samsung,exynos4210-chipid";
 332                         reg = <0x10000000 0x100>;
 333                 };
 334
 335                 mct: timer@100b0000 {
 336                         compatible = "samsung,exynos5260-mct",
 337                                      "samsung,exynos4210-mct";
 338                         reg = <0x100B0000 0x1000>;
 339                         clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
 340                         clock-names = "fin_pll", "mct";
 341                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 353                 };
 354
 355                 cci: cci@10f00000 {
 356                         compatible = "arm,cci-400";
 357                         #address-cells = <1>;
 358                         #size-cells = <1>;
 359                         reg = <0x10F00000 0x1000>;
 360                         ranges = <0x0 0x10F00000 0x6000>;
 361
 362                         cci_control0: slave-if@4000 {
 363                                 compatible = "arm,cci-400-ctrl-if";
 364                                 interface-type = "ace";
 365                                 reg = <0x4000 0x1000>;
 366                         };
 367
 368                         cci_control1: slave-if@5000 {
 369                                 compatible = "arm,cci-400-ctrl-if";
 370                                 interface-type = "ace";
 371                                 reg = <0x5000 0x1000>;
 372                         };
 373                 };
 374
 375                 pinctrl_0: pinctrl@11600000 {
 376                         compatible = "samsung,exynos5260-pinctrl";
 377                         reg = <0x11600000 0x1000>;
 378                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 379
 380                         wakeup-interrupt-controller {
 381                                 compatible = "samsung,exynos4210-wakeup-eint";
 382                                 interrupt-parent = <&gic>;
 383                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 384                         };
 385                 };
 386
 387                 pinctrl_1: pinctrl@12290000 {
 388                         compatible = "samsung,exynos5260-pinctrl";
 389                         reg = <0x12290000 0x1000>;
 390                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 391                 };
 392
 393                 pinctrl_2: pinctrl@128b0000 {
 394                         compatible = "samsung,exynos5260-pinctrl";
 395                         reg = <0x128B0000 0x1000>;
 396                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 397                 };
 398
 399                 pmu_system_controller: system-controller@10d50000 {
 400                         compatible = "samsung,exynos5260-pmu", "syscon";
 401                         reg = <0x10D50000 0x10000>;
 402                 };
 403
 404                 uart0: serial@12c00000 {
 405                         compatible = "samsung,exynos4210-uart";
 406                         reg = <0x12C00000 0x100>;
 407                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
 409                         clock-names = "uart", "clk_uart_baud0";
 410                         status = "disabled";
 411                 };
 412
 413                 uart1: serial@12c10000 {
 414                         compatible = "samsung,exynos4210-uart";
 415                         reg = <0x12C10000 0x100>;
 416                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
 418                         clock-names = "uart", "clk_uart_baud0";
 419                         status = "disabled";
 420                 };
 421
 422                 uart2: serial@12c20000 {
 423                         compatible = "samsung,exynos4210-uart";
 424                         reg = <0x12C20000 0x100>;
 425                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
 427                         clock-names = "uart", "clk_uart_baud0";
 428                         status = "disabled";
 429                 };
 430
 431                 uart3: serial@12860000 {
 432                         compatible = "samsung,exynos4210-uart";
 433                         reg = <0x12860000 0x100>;
 434                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
 436                         clock-names = "uart", "clk_uart_baud0";
 437                         status = "disabled";
 438                 };
 439
 440                 mmc_0: mmc@12140000 {
 441                         compatible = "samsung,exynos5250-dw-mshc";
 442                         reg = <0x12140000 0x2000>;
 443                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
 447                         clock-names = "biu", "ciu";
 448                         assigned-clocks =
 449                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
 450                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
 451                                 <&clock_top TOP_SCLK_MMC0>;
 452                         assigned-clock-parents =
 453                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
 454                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
 455                         assigned-clock-rates = <0>, <0>, <800000000>;
 456                         fifo-depth = <64>;
 457                         status = "disabled";
 458                 };
 459
 460                 mmc_1: mmc@12150000 {
 461                         compatible = "samsung,exynos5250-dw-mshc";
 462                         reg = <0x12150000 0x2000>;
 463                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
 467                         clock-names = "biu", "ciu";
 468                         assigned-clocks =
 469                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
 470                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
 471                                 <&clock_top TOP_SCLK_MMC1>;
 472                         assigned-clock-parents =
 473                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
 474                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
 475                         assigned-clock-rates = <0>, <0>, <800000000>;
 476                         fifo-depth = <64>;
 477                         status = "disabled";
 478                 };
 479
 480                 mmc_2: mmc@12160000 {
 481                         compatible = "samsung,exynos5250-dw-mshc";
 482                         reg = <0x12160000 0x2000>;
 483                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
 487                         clock-names = "biu", "ciu";
 488                         assigned-clocks =
 489                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
 490                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
 491                                 <&clock_top TOP_SCLK_MMC2>;
 492                         assigned-clock-parents =
 493                                 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
 494                                 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
 495                         assigned-clock-rates = <0>, <0>, <800000000>;
 496                         fifo-depth = <64>;
 497                         status = "disabled";
 498                 };
 499
 500                 hsi2c_0: i2c@12da0000 {
 501                         compatible = "samsung,exynos5260-hsi2c";
 502                         reg = <0x12DA0000 0x1000>;
 503                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         pinctrl-names = "default";
 507                         pinctrl-0 = <&i2c0_hs_bus>;
 508                         clocks = <&clock_peri PERI_CLK_HSIC0>;
 509                         clock-names = "hsi2c";
 510                         status = "disabled";
 511                 };
 512
 513                 hsi2c_1: i2c@12db0000 {
 514                         compatible = "samsung,exynos5260-hsi2c";
 515                         reg = <0x12DB0000 0x1000>;
 516                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         pinctrl-names = "default";
 520                         pinctrl-0 = <&i2c1_hs_bus>;
 521                         clocks = <&clock_peri PERI_CLK_HSIC1>;
 522                         clock-names = "hsi2c";
 523                         status = "disabled";
 524                 };
 525
 526                 hsi2c_2: i2c@12dc0000 {
 527                         compatible = "samsung,exynos5260-hsi2c";
 528                         reg = <0x12DC0000 0x1000>;
 529                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         pinctrl-names = "default";
 533                         pinctrl-0 = <&i2c2_hs_bus>;
 534                         clocks = <&clock_peri PERI_CLK_HSIC2>;
 535                         clock-names = "hsi2c";
 536                         status = "disabled";
 537                 };
 538
 539                 hsi2c_3: i2c@12dd0000 {
 540                         compatible = "samsung,exynos5260-hsi2c";
 541                         reg = <0x12DD0000 0x1000>;
 542                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                         pinctrl-names = "default";
 546                         pinctrl-0 = <&i2c3_hs_bus>;
 547                         clocks = <&clock_peri PERI_CLK_HSIC3>;
 548                         clock-names = "hsi2c";
 549                         status = "disabled";
 550                 };
 551         };
 552 };
 553
 554 #include "exynos5260-pinctrl.dtsi"