1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5260 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "samsung,exynos5260", "samsung,exynos5";
15 interrupt-parent = <&gic>;
24 pinctrl0 = &pinctrl_0;
25 pinctrl1 = &pinctrl_1;
26 pinctrl2 = &pinctrl_2;
65 compatible = "arm,cortex-a15";
67 cci-control-port = <&cci_control1>;
72 compatible = "arm,cortex-a15";
74 cci-control-port = <&cci_control1>;
79 compatible = "arm,cortex-a7";
81 cci-control-port = <&cci_control0>;
86 compatible = "arm,cortex-a7";
88 cci-control-port = <&cci_control0>;
93 compatible = "arm,cortex-a7";
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 cci-control-port = <&cci_control0>;
107 compatible = "simple-bus";
108 #address-cells = <1>;
112 clock_top: clock-controller@10010000 {
113 compatible = "samsung,exynos5260-clock-top";
114 reg = <0x10010000 0x10000>;
118 clock_peri: clock-controller@10200000 {
119 compatible = "samsung,exynos5260-clock-peri";
120 reg = <0x10200000 0x10000>;
124 clock_egl: clock-controller@10600000 {
125 compatible = "samsung,exynos5260-clock-egl";
126 reg = <0x10600000 0x10000>;
130 clock_kfc: clock-controller@10700000 {
131 compatible = "samsung,exynos5260-clock-kfc";
132 reg = <0x10700000 0x10000>;
136 clock_g2d: clock-controller@10a00000 {
137 compatible = "samsung,exynos5260-clock-g2d";
138 reg = <0x10A00000 0x10000>;
142 clock_mif: clock-controller@10ce0000 {
143 compatible = "samsung,exynos5260-clock-mif";
144 reg = <0x10CE0000 0x10000>;
148 clock_mfc: clock-controller@11090000 {
149 compatible = "samsung,exynos5260-clock-mfc";
150 reg = <0x11090000 0x10000>;
154 clock_g3d: clock-controller@11830000 {
155 compatible = "samsung,exynos5260-clock-g3d";
156 reg = <0x11830000 0x10000>;
160 clock_fsys: clock-controller@122e0000 {
161 compatible = "samsung,exynos5260-clock-fsys";
162 reg = <0x122E0000 0x10000>;
166 clock_aud: clock-controller@128c0000 {
167 compatible = "samsung,exynos5260-clock-aud";
168 reg = <0x128C0000 0x10000>;
172 clock_isp: clock-controller@133c0000 {
173 compatible = "samsung,exynos5260-clock-isp";
174 reg = <0x133C0000 0x10000>;
178 clock_gscl: clock-controller@13f00000 {
179 compatible = "samsung,exynos5260-clock-gscl";
180 reg = <0x13F00000 0x10000>;
184 clock_disp: clock-controller@14550000 {
185 compatible = "samsung,exynos5260-clock-disp";
186 reg = <0x14550000 0x10000>;
190 gic: interrupt-controller@10481000 {
191 compatible = "arm,gic-400", "arm,cortex-a15-gic";
192 #interrupt-cells = <3>;
193 interrupt-controller;
194 reg = <0x10481000 0x1000>,
198 interrupts = <GIC_PPI 9
199 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
202 chipid: chipid@10000000 {
203 compatible = "samsung,exynos4210-chipid";
204 reg = <0x10000000 0x100>;
207 mct: timer@100b0000 {
208 compatible = "samsung,exynos4210-mct";
209 reg = <0x100B0000 0x1000>;
210 clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
211 clock-names = "fin_pll", "mct";
212 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
227 compatible = "arm,cci-400";
228 #address-cells = <1>;
230 reg = <0x10F00000 0x1000>;
231 ranges = <0x0 0x10F00000 0x6000>;
233 cci_control0: slave-if@4000 {
234 compatible = "arm,cci-400-ctrl-if";
235 interface-type = "ace";
236 reg = <0x4000 0x1000>;
239 cci_control1: slave-if@5000 {
240 compatible = "arm,cci-400-ctrl-if";
241 interface-type = "ace";
242 reg = <0x5000 0x1000>;
246 pinctrl_0: pinctrl@11600000 {
247 compatible = "samsung,exynos5260-pinctrl";
248 reg = <0x11600000 0x1000>;
249 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
251 wakeup-interrupt-controller {
252 compatible = "samsung,exynos4210-wakeup-eint";
253 interrupt-parent = <&gic>;
254 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
258 pinctrl_1: pinctrl@12290000 {
259 compatible = "samsung,exynos5260-pinctrl";
260 reg = <0x12290000 0x1000>;
261 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
264 pinctrl_2: pinctrl@128b0000 {
265 compatible = "samsung,exynos5260-pinctrl";
266 reg = <0x128B0000 0x1000>;
267 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
270 pmu_system_controller: system-controller@10d50000 {
271 compatible = "samsung,exynos5260-pmu", "syscon";
272 reg = <0x10D50000 0x10000>;
275 uart0: serial@12c00000 {
276 compatible = "samsung,exynos4210-uart";
277 reg = <0x12C00000 0x100>;
278 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
280 clock-names = "uart", "clk_uart_baud0";
284 uart1: serial@12c10000 {
285 compatible = "samsung,exynos4210-uart";
286 reg = <0x12C10000 0x100>;
287 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
289 clock-names = "uart", "clk_uart_baud0";
293 uart2: serial@12c20000 {
294 compatible = "samsung,exynos4210-uart";
295 reg = <0x12C20000 0x100>;
296 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
298 clock-names = "uart", "clk_uart_baud0";
302 uart3: serial@12860000 {
303 compatible = "samsung,exynos4210-uart";
304 reg = <0x12860000 0x100>;
305 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
307 clock-names = "uart", "clk_uart_baud0";
311 mmc_0: mmc@12140000 {
312 compatible = "samsung,exynos5250-dw-mshc";
313 reg = <0x12140000 0x2000>;
314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
317 clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
318 clock-names = "biu", "ciu";
320 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>,
321 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>,
322 <&clock_top TOP_SCLK_MMC0>;
323 assigned-clock-parents =
324 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
325 <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>;
326 assigned-clock-rates = <0>, <0>, <800000000>;
331 mmc_1: mmc@12150000 {
332 compatible = "samsung,exynos5250-dw-mshc";
333 reg = <0x12150000 0x2000>;
334 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
337 clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
338 clock-names = "biu", "ciu";
340 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>,
341 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>,
342 <&clock_top TOP_SCLK_MMC1>;
343 assigned-clock-parents =
344 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
345 <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>;
346 assigned-clock-rates = <0>, <0>, <800000000>;
351 mmc_2: mmc@12160000 {
352 compatible = "samsung,exynos5250-dw-mshc";
353 reg = <0x12160000 0x2000>;
354 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
357 clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
358 clock-names = "biu", "ciu";
360 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>,
361 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>,
362 <&clock_top TOP_SCLK_MMC2>;
363 assigned-clock-parents =
364 <&clock_top TOP_MOUT_BUSTOP_PLL_USER>,
365 <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>;
366 assigned-clock-rates = <0>, <0>, <800000000>;
371 hsi2c_0: hsi2c@12da0000 {
372 compatible = "samsung,exynos5260-hsi2c";
373 reg = <0x12DA0000 0x1000>;
374 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c0_hs_bus>;
379 clocks = <&clock_peri PERI_CLK_HSIC0>;
380 clock-names = "hsi2c";
384 hsi2c_1: hsi2c@12db0000 {
385 compatible = "samsung,exynos5260-hsi2c";
386 reg = <0x12DB0000 0x1000>;
387 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
390 pinctrl-names = "default";
391 pinctrl-0 = <&i2c1_hs_bus>;
392 clocks = <&clock_peri PERI_CLK_HSIC1>;
393 clock-names = "hsi2c";
397 hsi2c_2: hsi2c@12dc0000 {
398 compatible = "samsung,exynos5260-hsi2c";
399 reg = <0x12DC0000 0x1000>;
400 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c2_hs_bus>;
405 clocks = <&clock_peri PERI_CLK_HSIC2>;
406 clock-names = "hsi2c";
410 hsi2c_3: hsi2c@12dd0000 {
411 compatible = "samsung,exynos5260-hsi2c";
412 reg = <0x12DD0000 0x1000>;
413 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&i2c3_hs_bus>;
418 clocks = <&clock_peri PERI_CLK_HSIC3>;
419 clock-names = "hsi2c";
425 #include "exynos5260-pinctrl.dtsi"