2 * SAMSUNG EXYNOS5250 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
8 * EXYNOS5250 based board files can include this file and provide
9 * values for board specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13 * additional nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <dt-bindings/clock/exynos5250.h>
21 #include "exynos5.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
23 #include <dt-bindings/clock/exynos-audss-clk.h>
26 compatible = "samsung,exynos5250", "samsung,exynos5";
46 pinctrl0 = &pinctrl_0;
47 pinctrl1 = &pinctrl_1;
48 pinctrl2 = &pinctrl_2;
49 pinctrl3 = &pinctrl_3;
58 compatible = "arm,cortex-a15";
60 clocks = <&clock CLK_ARM_CLK>;
62 operating-points-v2 = <&cpu0_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
67 compatible = "arm,cortex-a15";
69 clocks = <&clock CLK_ARM_CLK>;
71 operating-points-v2 = <&cpu0_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
76 cpu0_opp_table: opp_table0 {
77 compatible = "operating-points-v2";
81 opp-hz = /bits/ 64 <200000000>;
82 opp-microvolt = <925000>;
83 clock-latency-ns = <140000>;
86 opp-hz = /bits/ 64 <300000000>;
87 opp-microvolt = <937500>;
88 clock-latency-ns = <140000>;
91 opp-hz = /bits/ 64 <400000000>;
92 opp-microvolt = <950000>;
93 clock-latency-ns = <140000>;
96 opp-hz = /bits/ 64 <500000000>;
97 opp-microvolt = <975000>;
98 clock-latency-ns = <140000>;
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <1000000>;
103 clock-latency-ns = <140000>;
106 opp-hz = /bits/ 64 <700000000>;
107 opp-microvolt = <1012500>;
108 clock-latency-ns = <140000>;
111 opp-hz = /bits/ 64 <800000000>;
112 opp-microvolt = <1025000>;
113 clock-latency-ns = <140000>;
116 opp-hz = /bits/ 64 <900000000>;
117 opp-microvolt = <1050000>;
118 clock-latency-ns = <140000>;
121 opp-hz = /bits/ 64 <1000000000>;
122 opp-microvolt = <1075000>;
123 clock-latency-ns = <140000>;
127 opp-hz = /bits/ 64 <1100000000>;
128 opp-microvolt = <1100000>;
129 clock-latency-ns = <140000>;
132 opp-hz = /bits/ 64 <1200000000>;
133 opp-microvolt = <1125000>;
134 clock-latency-ns = <140000>;
137 opp-hz = /bits/ 64 <1300000000>;
138 opp-microvolt = <1150000>;
139 clock-latency-ns = <140000>;
142 opp-hz = /bits/ 64 <1400000000>;
143 opp-microvolt = <1200000>;
144 clock-latency-ns = <140000>;
147 opp-hz = /bits/ 64 <1500000000>;
148 opp-microvolt = <1225000>;
149 clock-latency-ns = <140000>;
152 opp-hz = /bits/ 64 <1600000000>;
153 opp-microvolt = <1250000>;
154 clock-latency-ns = <140000>;
157 opp-hz = /bits/ 64 <1700000000>;
158 opp-microvolt = <1300000>;
159 clock-latency-ns = <140000>;
165 compatible = "mmio-sram";
166 reg = <0x02020000 0x30000>;
167 #address-cells = <1>;
169 ranges = <0 0x02020000 0x30000>;
172 compatible = "samsung,exynos4210-sysram";
177 compatible = "samsung,exynos4210-sysram-ns";
178 reg = <0x2f000 0x1000>;
182 pd_gsc: gsc-power-domain@10044000 {
183 compatible = "samsung,exynos4210-pd";
184 reg = <0x10044000 0x20>;
185 #power-domain-cells = <0>;
188 pd_mfc: mfc-power-domain@10044040 {
189 compatible = "samsung,exynos4210-pd";
190 reg = <0x10044040 0x20>;
191 #power-domain-cells = <0>;
194 pd_disp1: disp1-power-domain@100440A0 {
195 compatible = "samsung,exynos4210-pd";
196 reg = <0x100440A0 0x20>;
197 #power-domain-cells = <0>;
198 clocks = <&clock CLK_FIN_PLL>,
199 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
200 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
201 clock-names = "oscclk", "clk0", "clk1";
204 clock: clock-controller@10010000 {
205 compatible = "samsung,exynos5250-clock";
206 reg = <0x10010000 0x30000>;
210 clock_audss: audss-clock-controller@3810000 {
211 compatible = "samsung,exynos5250-audss-clock";
212 reg = <0x03810000 0x0C>;
214 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
215 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
216 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
220 compatible = "arm,armv7-timer";
221 interrupts = <1 13 0xf08>,
226 * Unfortunately we need this since some versions
227 * of U-Boot on Exynos don't set the CNTFRQ register,
228 * so we need the value from DT.
230 clock-frequency = <24000000>;
234 compatible = "samsung,exynos4210-mct";
235 reg = <0x101C0000 0x800>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 interrupt-parent = <&mct_map>;
239 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
242 clock-names = "fin_pll", "mct";
245 #interrupt-cells = <2>;
246 #address-cells = <0>;
248 interrupt-map = <0x0 0 &combiner 23 3>,
249 <0x1 0 &combiner 23 4>,
250 <0x2 0 &combiner 25 2>,
251 <0x3 0 &combiner 25 3>,
252 <0x4 0 &gic 0 120 0>,
253 <0x5 0 &gic 0 121 0>;
258 compatible = "arm,cortex-a15-pmu";
259 interrupt-parent = <&combiner>;
260 interrupts = <1 2>, <22 4>;
263 pinctrl_0: pinctrl@11400000 {
264 compatible = "samsung,exynos5250-pinctrl";
265 reg = <0x11400000 0x1000>;
266 interrupts = <0 46 0>;
268 wakup_eint: wakeup-interrupt-controller {
269 compatible = "samsung,exynos4210-wakeup-eint";
270 interrupt-parent = <&gic>;
271 interrupts = <0 32 0>;
275 pinctrl_1: pinctrl@13400000 {
276 compatible = "samsung,exynos5250-pinctrl";
277 reg = <0x13400000 0x1000>;
278 interrupts = <0 45 0>;
281 pinctrl_2: pinctrl@10d10000 {
282 compatible = "samsung,exynos5250-pinctrl";
283 reg = <0x10d10000 0x1000>;
284 interrupts = <0 50 0>;
287 pinctrl_3: pinctrl@03860000 {
288 compatible = "samsung,exynos5250-pinctrl";
289 reg = <0x03860000 0x1000>;
290 interrupts = <0 47 0>;
293 pmu_system_controller: system-controller@10040000 {
294 compatible = "samsung,exynos5250-pmu", "syscon";
295 reg = <0x10040000 0x5000>;
296 clock-names = "clkout16";
297 clocks = <&clock CLK_FIN_PLL>;
299 interrupt-controller;
300 #interrupt-cells = <3>;
301 interrupt-parent = <&gic>;
305 compatible = "samsung,exynos5250-wdt";
306 reg = <0x101D0000 0x100>;
307 interrupts = <0 42 0>;
308 clocks = <&clock CLK_WDT>;
309 clock-names = "watchdog";
310 samsung,syscon-phandle = <&pmu_system_controller>;
314 compatible = "samsung,exynos5250-g2d";
315 reg = <0x10850000 0x1000>;
316 interrupts = <0 91 0>;
317 clocks = <&clock CLK_G2D>;
318 clock-names = "fimg2d";
319 iommus = <&sysmmu_g2d>;
322 mfc: codec@11000000 {
323 compatible = "samsung,mfc-v6";
324 reg = <0x11000000 0x10000>;
325 interrupts = <0 96 0>;
326 power-domains = <&pd_mfc>;
327 clocks = <&clock CLK_MFC>;
329 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
330 iommu-names = "left", "right";
333 rotator: rotator@11C00000 {
334 compatible = "samsung,exynos5250-rotator";
335 reg = <0x11C00000 0x64>;
336 interrupts = <0 84 0>;
337 clocks = <&clock CLK_ROTATOR>;
338 clock-names = "rotator";
339 iommus = <&sysmmu_rotator>;
343 compatible = "samsung,exynos5250-tmu";
344 reg = <0x10060000 0x100>;
345 interrupts = <0 65 0>;
346 clocks = <&clock CLK_TMU>;
347 clock-names = "tmu_apbif";
348 #include "exynos4412-tmu-sensor-conf.dtsi"
351 sata: sata@122F0000 {
352 compatible = "snps,dwc-ahci";
353 samsung,sata-freq = <66>;
354 reg = <0x122F0000 0x1ff>;
355 interrupts = <0 115 0>;
356 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
357 clock-names = "sata", "sclk_sata";
359 phy-names = "sata-phy";
363 sata_phy: sata-phy@12170000 {
364 compatible = "samsung,exynos5250-sata-phy";
365 reg = <0x12170000 0x1ff>;
366 clocks = <&clock CLK_SATA_PHYCTRL>;
367 clock-names = "sata_phyctrl";
369 samsung,syscon-phandle = <&pmu_system_controller>;
373 /* i2c_0-3 are defined in exynos5.dtsi */
374 i2c_4: i2c@12CA0000 {
375 compatible = "samsung,s3c2440-i2c";
376 reg = <0x12CA0000 0x100>;
377 interrupts = <0 60 0>;
378 #address-cells = <1>;
380 clocks = <&clock CLK_I2C4>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c4_bus>;
387 i2c_5: i2c@12CB0000 {
388 compatible = "samsung,s3c2440-i2c";
389 reg = <0x12CB0000 0x100>;
390 interrupts = <0 61 0>;
391 #address-cells = <1>;
393 clocks = <&clock CLK_I2C5>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c5_bus>;
400 i2c_6: i2c@12CC0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CC0000 0x100>;
403 interrupts = <0 62 0>;
404 #address-cells = <1>;
406 clocks = <&clock CLK_I2C6>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c6_bus>;
413 i2c_7: i2c@12CD0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CD0000 0x100>;
416 interrupts = <0 63 0>;
417 #address-cells = <1>;
419 clocks = <&clock CLK_I2C7>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c7_bus>;
426 i2c_8: i2c@12CE0000 {
427 compatible = "samsung,s3c2440-hdmiphy-i2c";
428 reg = <0x12CE0000 0x1000>;
429 interrupts = <0 64 0>;
430 #address-cells = <1>;
432 clocks = <&clock CLK_I2C_HDMI>;
437 i2c_9: i2c@121D0000 {
438 compatible = "samsung,exynos5-sata-phy-i2c";
439 reg = <0x121D0000 0x100>;
440 #address-cells = <1>;
442 clocks = <&clock CLK_SATA_PHYI2C>;
447 spi_0: spi@12d20000 {
448 compatible = "samsung,exynos4210-spi";
450 reg = <0x12d20000 0x100>;
451 interrupts = <0 66 0>;
454 dma-names = "tx", "rx";
455 #address-cells = <1>;
457 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
458 clock-names = "spi", "spi_busclk0";
459 pinctrl-names = "default";
460 pinctrl-0 = <&spi0_bus>;
463 spi_1: spi@12d30000 {
464 compatible = "samsung,exynos4210-spi";
466 reg = <0x12d30000 0x100>;
467 interrupts = <0 67 0>;
470 dma-names = "tx", "rx";
471 #address-cells = <1>;
473 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
474 clock-names = "spi", "spi_busclk0";
475 pinctrl-names = "default";
476 pinctrl-0 = <&spi1_bus>;
479 spi_2: spi@12d40000 {
480 compatible = "samsung,exynos4210-spi";
482 reg = <0x12d40000 0x100>;
483 interrupts = <0 68 0>;
486 dma-names = "tx", "rx";
487 #address-cells = <1>;
489 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
490 clock-names = "spi", "spi_busclk0";
491 pinctrl-names = "default";
492 pinctrl-0 = <&spi2_bus>;
495 mmc_0: mmc@12200000 {
496 compatible = "samsung,exynos5250-dw-mshc";
497 interrupts = <0 75 0>;
498 #address-cells = <1>;
500 reg = <0x12200000 0x1000>;
501 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
502 clock-names = "biu", "ciu";
507 mmc_1: mmc@12210000 {
508 compatible = "samsung,exynos5250-dw-mshc";
509 interrupts = <0 76 0>;
510 #address-cells = <1>;
512 reg = <0x12210000 0x1000>;
513 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
514 clock-names = "biu", "ciu";
519 mmc_2: mmc@12220000 {
520 compatible = "samsung,exynos5250-dw-mshc";
521 interrupts = <0 77 0>;
522 #address-cells = <1>;
524 reg = <0x12220000 0x1000>;
525 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
526 clock-names = "biu", "ciu";
531 mmc_3: mmc@12230000 {
532 compatible = "samsung,exynos5250-dw-mshc";
533 reg = <0x12230000 0x1000>;
534 interrupts = <0 78 0>;
535 #address-cells = <1>;
537 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
538 clock-names = "biu", "ciu";
544 compatible = "samsung,s5pv210-i2s";
546 reg = <0x03830000 0x100>;
550 dma-names = "tx", "rx", "tx-sec";
551 clocks = <&clock_audss EXYNOS_I2S_BUS>,
552 <&clock_audss EXYNOS_I2S_BUS>,
553 <&clock_audss EXYNOS_SCLK_I2S>;
554 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
555 samsung,idma-addr = <0x03000000>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2s0_bus>;
561 compatible = "samsung,s3c6410-i2s";
563 reg = <0x12D60000 0x100>;
566 dma-names = "tx", "rx";
567 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
568 clock-names = "iis", "i2s_opclk0";
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2s1_bus>;
574 compatible = "samsung,s3c6410-i2s";
576 reg = <0x12D70000 0x100>;
579 dma-names = "tx", "rx";
580 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
581 clock-names = "iis", "i2s_opclk0";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2s2_bus>;
587 compatible = "samsung,exynos5250-dwusb3";
588 clocks = <&clock CLK_USB3>;
589 clock-names = "usbdrd30";
590 #address-cells = <1>;
594 usbdrd_dwc3: dwc3@12000000 {
595 compatible = "synopsys,dwc3";
596 reg = <0x12000000 0x10000>;
597 interrupts = <0 72 0>;
598 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
599 phy-names = "usb2-phy", "usb3-phy";
603 usbdrd_phy: phy@12100000 {
604 compatible = "samsung,exynos5250-usbdrd-phy";
605 reg = <0x12100000 0x100>;
606 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
607 clock-names = "phy", "ref";
608 samsung,pmu-syscon = <&pmu_system_controller>;
613 compatible = "samsung,exynos4210-ehci";
614 reg = <0x12110000 0x100>;
615 interrupts = <0 71 0>;
617 clocks = <&clock CLK_USB2>;
618 clock-names = "usbhost";
619 #address-cells = <1>;
623 phys = <&usb2_phy_gen 1>;
628 compatible = "samsung,exynos4210-ohci";
629 reg = <0x12120000 0x100>;
630 interrupts = <0 71 0>;
632 clocks = <&clock CLK_USB2>;
633 clock-names = "usbhost";
634 #address-cells = <1>;
638 phys = <&usb2_phy_gen 1>;
642 usb2_phy_gen: phy@12130000 {
643 compatible = "samsung,exynos5250-usb2-phy";
644 reg = <0x12130000 0x100>;
645 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
646 clock-names = "phy", "ref";
648 samsung,sysreg-phandle = <&sysreg_system_controller>;
649 samsung,pmureg-phandle = <&pmu_system_controller>;
653 #address-cells = <1>;
655 compatible = "simple-bus";
656 interrupt-parent = <&gic>;
659 pdma0: pdma@121A0000 {
660 compatible = "arm,pl330", "arm,primecell";
661 reg = <0x121A0000 0x1000>;
662 interrupts = <0 34 0>;
663 clocks = <&clock CLK_PDMA0>;
664 clock-names = "apb_pclk";
667 #dma-requests = <32>;
670 pdma1: pdma@121B0000 {
671 compatible = "arm,pl330", "arm,primecell";
672 reg = <0x121B0000 0x1000>;
673 interrupts = <0 35 0>;
674 clocks = <&clock CLK_PDMA1>;
675 clock-names = "apb_pclk";
678 #dma-requests = <32>;
681 mdma0: mdma@10800000 {
682 compatible = "arm,pl330", "arm,primecell";
683 reg = <0x10800000 0x1000>;
684 interrupts = <0 33 0>;
685 clocks = <&clock CLK_MDMA0>;
686 clock-names = "apb_pclk";
692 mdma1: mdma@11C10000 {
693 compatible = "arm,pl330", "arm,primecell";
694 reg = <0x11C10000 0x1000>;
695 interrupts = <0 124 0>;
696 clocks = <&clock CLK_MDMA1>;
697 clock-names = "apb_pclk";
704 gsc_0: gsc@13e00000 {
705 compatible = "samsung,exynos5-gsc";
706 reg = <0x13e00000 0x1000>;
707 interrupts = <0 85 0>;
708 power-domains = <&pd_gsc>;
709 clocks = <&clock CLK_GSCL0>;
710 clock-names = "gscl";
711 iommus = <&sysmmu_gsc0>;
714 gsc_1: gsc@13e10000 {
715 compatible = "samsung,exynos5-gsc";
716 reg = <0x13e10000 0x1000>;
717 interrupts = <0 86 0>;
718 power-domains = <&pd_gsc>;
719 clocks = <&clock CLK_GSCL1>;
720 clock-names = "gscl";
721 iommus = <&sysmmu_gsc1>;
724 gsc_2: gsc@13e20000 {
725 compatible = "samsung,exynos5-gsc";
726 reg = <0x13e20000 0x1000>;
727 interrupts = <0 87 0>;
728 power-domains = <&pd_gsc>;
729 clocks = <&clock CLK_GSCL2>;
730 clock-names = "gscl";
731 iommus = <&sysmmu_gsc2>;
734 gsc_3: gsc@13e30000 {
735 compatible = "samsung,exynos5-gsc";
736 reg = <0x13e30000 0x1000>;
737 interrupts = <0 88 0>;
738 power-domains = <&pd_gsc>;
739 clocks = <&clock CLK_GSCL3>;
740 clock-names = "gscl";
741 iommus = <&sysmmu_gsc3>;
744 hdmi: hdmi@14530000 {
745 compatible = "samsung,exynos4212-hdmi";
746 reg = <0x14530000 0x70000>;
747 power-domains = <&pd_disp1>;
748 interrupts = <0 95 0>;
749 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
750 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
751 <&clock CLK_MOUT_HDMI>;
752 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
753 "sclk_hdmiphy", "mout_hdmi";
754 samsung,syscon-phandle = <&pmu_system_controller>;
758 compatible = "samsung,exynos5250-mixer";
759 reg = <0x14450000 0x10000>;
760 power-domains = <&pd_disp1>;
761 interrupts = <0 94 0>;
762 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
763 <&clock CLK_SCLK_HDMI>;
764 clock-names = "mixer", "hdmi", "sclk_hdmi";
765 iommus = <&sysmmu_tv>;
769 compatible = "samsung,exynos5250-dp-video-phy";
770 samsung,pmu-syscon = <&pmu_system_controller>;
775 compatible = "samsung,exynos-adc-v1";
776 reg = <0x12D10000 0x100>;
777 interrupts = <0 106 0>;
778 clocks = <&clock CLK_ADC>;
780 #io-channel-cells = <1>;
782 samsung,syscon-phandle = <&pmu_system_controller>;
787 compatible = "samsung,exynos4210-secss";
788 reg = <0x10830000 0x300>;
789 interrupts = <0 112 0>;
790 clocks = <&clock CLK_SSS>;
791 clock-names = "secss";
794 sysmmu_g2d: sysmmu@10A60000 {
795 compatible = "samsung,exynos-sysmmu";
796 reg = <0x10A60000 0x1000>;
797 interrupt-parent = <&combiner>;
799 clock-names = "sysmmu", "master";
800 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
804 sysmmu_mfc_r: sysmmu@11200000 {
805 compatible = "samsung,exynos-sysmmu";
806 reg = <0x11200000 0x1000>;
807 interrupt-parent = <&combiner>;
809 power-domains = <&pd_mfc>;
810 clock-names = "sysmmu", "master";
811 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
815 sysmmu_mfc_l: sysmmu@11210000 {
816 compatible = "samsung,exynos-sysmmu";
817 reg = <0x11210000 0x1000>;
818 interrupt-parent = <&combiner>;
820 power-domains = <&pd_mfc>;
821 clock-names = "sysmmu", "master";
822 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
826 sysmmu_rotator: sysmmu@11D40000 {
827 compatible = "samsung,exynos-sysmmu";
828 reg = <0x11D40000 0x1000>;
829 interrupt-parent = <&combiner>;
831 clock-names = "sysmmu", "master";
832 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
836 sysmmu_jpeg: sysmmu@11F20000 {
837 compatible = "samsung,exynos-sysmmu";
838 reg = <0x11F20000 0x1000>;
839 interrupt-parent = <&combiner>;
841 power-domains = <&pd_gsc>;
842 clock-names = "sysmmu", "master";
843 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
847 sysmmu_fimc_isp: sysmmu@13260000 {
848 compatible = "samsung,exynos-sysmmu";
849 reg = <0x13260000 0x1000>;
850 interrupt-parent = <&combiner>;
852 clock-names = "sysmmu";
853 clocks = <&clock CLK_SMMU_FIMC_ISP>;
857 sysmmu_fimc_drc: sysmmu@13270000 {
858 compatible = "samsung,exynos-sysmmu";
859 reg = <0x13270000 0x1000>;
860 interrupt-parent = <&combiner>;
862 clock-names = "sysmmu";
863 clocks = <&clock CLK_SMMU_FIMC_DRC>;
867 sysmmu_fimc_fd: sysmmu@132A0000 {
868 compatible = "samsung,exynos-sysmmu";
869 reg = <0x132A0000 0x1000>;
870 interrupt-parent = <&combiner>;
872 clock-names = "sysmmu";
873 clocks = <&clock CLK_SMMU_FIMC_FD>;
877 sysmmu_fimc_scc: sysmmu@13280000 {
878 compatible = "samsung,exynos-sysmmu";
879 reg = <0x13280000 0x1000>;
880 interrupt-parent = <&combiner>;
882 clock-names = "sysmmu";
883 clocks = <&clock CLK_SMMU_FIMC_SCC>;
887 sysmmu_fimc_scp: sysmmu@13290000 {
888 compatible = "samsung,exynos-sysmmu";
889 reg = <0x13290000 0x1000>;
890 interrupt-parent = <&combiner>;
892 clock-names = "sysmmu";
893 clocks = <&clock CLK_SMMU_FIMC_SCP>;
897 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
898 compatible = "samsung,exynos-sysmmu";
899 reg = <0x132B0000 0x1000>;
900 interrupt-parent = <&combiner>;
902 clock-names = "sysmmu";
903 clocks = <&clock CLK_SMMU_FIMC_MCU>;
907 sysmmu_fimc_odc: sysmmu@132C0000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x132C0000 0x1000>;
910 interrupt-parent = <&combiner>;
912 clock-names = "sysmmu";
913 clocks = <&clock CLK_SMMU_FIMC_ODC>;
917 sysmmu_fimc_dis0: sysmmu@132D0000 {
918 compatible = "samsung,exynos-sysmmu";
919 reg = <0x132D0000 0x1000>;
920 interrupt-parent = <&combiner>;
922 clock-names = "sysmmu";
923 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
927 sysmmu_fimc_dis1: sysmmu@132E0000{
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x132E0000 0x1000>;
930 interrupt-parent = <&combiner>;
932 clock-names = "sysmmu";
933 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
937 sysmmu_fimc_3dnr: sysmmu@132F0000 {
938 compatible = "samsung,exynos-sysmmu";
939 reg = <0x132F0000 0x1000>;
940 interrupt-parent = <&combiner>;
942 clock-names = "sysmmu";
943 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
947 sysmmu_fimc_lite0: sysmmu@13C40000 {
948 compatible = "samsung,exynos-sysmmu";
949 reg = <0x13C40000 0x1000>;
950 interrupt-parent = <&combiner>;
952 power-domains = <&pd_gsc>;
953 clock-names = "sysmmu", "master";
954 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
958 sysmmu_fimc_lite1: sysmmu@13C50000 {
959 compatible = "samsung,exynos-sysmmu";
960 reg = <0x13C50000 0x1000>;
961 interrupt-parent = <&combiner>;
963 power-domains = <&pd_gsc>;
964 clock-names = "sysmmu", "master";
965 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
969 sysmmu_gsc0: sysmmu@13E80000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x13E80000 0x1000>;
972 interrupt-parent = <&combiner>;
974 power-domains = <&pd_gsc>;
975 clock-names = "sysmmu", "master";
976 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
980 sysmmu_gsc1: sysmmu@13E90000 {
981 compatible = "samsung,exynos-sysmmu";
982 reg = <0x13E90000 0x1000>;
983 interrupt-parent = <&combiner>;
985 power-domains = <&pd_gsc>;
986 clock-names = "sysmmu", "master";
987 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
991 sysmmu_gsc2: sysmmu@13EA0000 {
992 compatible = "samsung,exynos-sysmmu";
993 reg = <0x13EA0000 0x1000>;
994 interrupt-parent = <&combiner>;
996 power-domains = <&pd_gsc>;
997 clock-names = "sysmmu", "master";
998 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1002 sysmmu_gsc3: sysmmu@13EB0000 {
1003 compatible = "samsung,exynos-sysmmu";
1004 reg = <0x13EB0000 0x1000>;
1005 interrupt-parent = <&combiner>;
1007 power-domains = <&pd_gsc>;
1008 clock-names = "sysmmu", "master";
1009 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1013 sysmmu_fimd1: sysmmu@14640000 {
1014 compatible = "samsung,exynos-sysmmu";
1015 reg = <0x14640000 0x1000>;
1016 interrupt-parent = <&combiner>;
1018 power-domains = <&pd_disp1>;
1019 clock-names = "sysmmu", "master";
1020 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1024 sysmmu_tv: sysmmu@14650000 {
1025 compatible = "samsung,exynos-sysmmu";
1026 reg = <0x14650000 0x1000>;
1027 interrupt-parent = <&combiner>;
1029 power-domains = <&pd_disp1>;
1030 clock-names = "sysmmu", "master";
1031 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1037 cpu_thermal: cpu-thermal {
1038 polling-delay-passive = <0>;
1039 polling-delay = <0>;
1040 thermal-sensors = <&tmu 0>;
1044 /* Corresponds to 800MHz at freq_table */
1045 cooling-device = <&cpu0 9 9>;
1048 /* Corresponds to 200MHz at freq_table */
1049 cooling-device = <&cpu0 15 15>;
1057 power-domains = <&pd_disp1>;
1058 clocks = <&clock CLK_DP>;
1065 power-domains = <&pd_disp1>;
1066 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1067 clock-names = "sclk_fimd", "fimd";
1068 iommus = <&sysmmu_fimd1>;
1072 clocks = <&clock CLK_I2C0>;
1073 clock-names = "i2c";
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&i2c0_bus>;
1079 clocks = <&clock CLK_I2C1>;
1080 clock-names = "i2c";
1081 pinctrl-names = "default";
1082 pinctrl-0 = <&i2c1_bus>;
1086 clocks = <&clock CLK_I2C2>;
1087 clock-names = "i2c";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&i2c2_bus>;
1093 clocks = <&clock CLK_I2C3>;
1094 clock-names = "i2c";
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&i2c3_bus>;
1100 clocks = <&clock CLK_PWM>;
1101 clock-names = "timers";
1105 clocks = <&clock CLK_RTC>;
1106 clock-names = "rtc";
1107 interrupt-parent = <&pmu_system_controller>;
1108 status = "disabled";
1112 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1113 clock-names = "uart", "clk_uart_baud0";
1117 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1118 clock-names = "uart", "clk_uart_baud0";
1122 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1123 clock-names = "uart", "clk_uart_baud0";
1127 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1128 clock-names = "uart", "clk_uart_baud0";
1131 #include "exynos5250-pinctrl.dtsi"