GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / exynos5250.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * SAMSUNG EXYNOS5250 SoC device tree source
4  *
5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6  *              http://www.samsung.com
7  *
8  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9  * EXYNOS5250 based board files can include this file and provide
10  * values for board specfic bindings.
11  *
12  * Note: This file does not include device nodes for all the controllers in
13  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
14  * additional nodes can be added to this file.
15  */
16
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21
22 / {
23         compatible = "samsung,exynos5250", "samsung,exynos5";
24
25         aliases {
26                 spi0 = &spi_0;
27                 spi1 = &spi_1;
28                 spi2 = &spi_2;
29                 gsc0 = &gsc_0;
30                 gsc1 = &gsc_1;
31                 gsc2 = &gsc_2;
32                 gsc3 = &gsc_3;
33                 mshc0 = &mmc_0;
34                 mshc1 = &mmc_1;
35                 mshc2 = &mmc_2;
36                 mshc3 = &mmc_3;
37                 i2c4 = &i2c_4;
38                 i2c5 = &i2c_5;
39                 i2c6 = &i2c_6;
40                 i2c7 = &i2c_7;
41                 i2c8 = &i2c_8;
42                 i2c9 = &i2c_9;
43                 pinctrl0 = &pinctrl_0;
44                 pinctrl1 = &pinctrl_1;
45                 pinctrl2 = &pinctrl_2;
46                 pinctrl3 = &pinctrl_3;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52
53                 cpu0: cpu@0 {
54                         device_type = "cpu";
55                         compatible = "arm,cortex-a15";
56                         reg = <0>;
57                         clocks = <&clock CLK_ARM_CLK>;
58                         clock-names = "cpu";
59                         operating-points-v2 = <&cpu0_opp_table>;
60                         #cooling-cells = <2>; /* min followed by max */
61                 };
62                 cpu@1 {
63                         device_type = "cpu";
64                         compatible = "arm,cortex-a15";
65                         reg = <1>;
66                         clocks = <&clock CLK_ARM_CLK>;
67                         clock-names = "cpu";
68                         operating-points-v2 = <&cpu0_opp_table>;
69                         #cooling-cells = <2>; /* min followed by max */
70                 };
71         };
72
73         cpu0_opp_table: opp_table0 {
74                 compatible = "operating-points-v2";
75                 opp-shared;
76
77                 opp-200000000 {
78                         opp-hz = /bits/ 64 <200000000>;
79                         opp-microvolt = <925000>;
80                         clock-latency-ns = <140000>;
81                 };
82                 opp-300000000 {
83                         opp-hz = /bits/ 64 <300000000>;
84                         opp-microvolt = <937500>;
85                         clock-latency-ns = <140000>;
86                 };
87                 opp-400000000 {
88                         opp-hz = /bits/ 64 <400000000>;
89                         opp-microvolt = <950000>;
90                         clock-latency-ns = <140000>;
91                 };
92                 opp-500000000 {
93                         opp-hz = /bits/ 64 <500000000>;
94                         opp-microvolt = <975000>;
95                         clock-latency-ns = <140000>;
96                 };
97                 opp-600000000 {
98                         opp-hz = /bits/ 64 <600000000>;
99                         opp-microvolt = <1000000>;
100                         clock-latency-ns = <140000>;
101                 };
102                 opp-700000000 {
103                         opp-hz = /bits/ 64 <700000000>;
104                         opp-microvolt = <1012500>;
105                         clock-latency-ns = <140000>;
106                 };
107                 opp-800000000 {
108                         opp-hz = /bits/ 64 <800000000>;
109                         opp-microvolt = <1025000>;
110                         clock-latency-ns = <140000>;
111                 };
112                 opp-900000000 {
113                         opp-hz = /bits/ 64 <900000000>;
114                         opp-microvolt = <1050000>;
115                         clock-latency-ns = <140000>;
116                 };
117                 opp-1000000000 {
118                         opp-hz = /bits/ 64 <1000000000>;
119                         opp-microvolt = <1075000>;
120                         clock-latency-ns = <140000>;
121                         opp-suspend;
122                 };
123                 opp-1100000000 {
124                         opp-hz = /bits/ 64 <1100000000>;
125                         opp-microvolt = <1100000>;
126                         clock-latency-ns = <140000>;
127                 };
128                 opp-1200000000 {
129                         opp-hz = /bits/ 64 <1200000000>;
130                         opp-microvolt = <1125000>;
131                         clock-latency-ns = <140000>;
132                 };
133                 opp-1300000000 {
134                         opp-hz = /bits/ 64 <1300000000>;
135                         opp-microvolt = <1150000>;
136                         clock-latency-ns = <140000>;
137                 };
138                 opp-1400000000 {
139                         opp-hz = /bits/ 64 <1400000000>;
140                         opp-microvolt = <1200000>;
141                         clock-latency-ns = <140000>;
142                 };
143                 opp-1500000000 {
144                         opp-hz = /bits/ 64 <1500000000>;
145                         opp-microvolt = <1225000>;
146                         clock-latency-ns = <140000>;
147                 };
148                 opp-1600000000 {
149                         opp-hz = /bits/ 64 <1600000000>;
150                         opp-microvolt = <1250000>;
151                         clock-latency-ns = <140000>;
152                 };
153                 opp-1700000000 {
154                         opp-hz = /bits/ 64 <1700000000>;
155                         opp-microvolt = <1300000>;
156                         clock-latency-ns = <140000>;
157                 };
158         };
159
160         soc: soc {
161                 sysram@2020000 {
162                         compatible = "mmio-sram";
163                         reg = <0x02020000 0x30000>;
164                         #address-cells = <1>;
165                         #size-cells = <1>;
166                         ranges = <0 0x02020000 0x30000>;
167
168                         smp-sysram@0 {
169                                 compatible = "samsung,exynos4210-sysram";
170                                 reg = <0x0 0x1000>;
171                         };
172
173                         smp-sysram@2f000 {
174                                 compatible = "samsung,exynos4210-sysram-ns";
175                                 reg = <0x2f000 0x1000>;
176                         };
177                 };
178
179                 pd_gsc: power-domain@10044000 {
180                         compatible = "samsung,exynos4210-pd";
181                         reg = <0x10044000 0x20>;
182                         #power-domain-cells = <0>;
183                         label = "GSC";
184                 };
185
186                 pd_mfc: power-domain@10044040 {
187                         compatible = "samsung,exynos4210-pd";
188                         reg = <0x10044040 0x20>;
189                         #power-domain-cells = <0>;
190                         label = "MFC";
191                 };
192
193                 pd_g3d: power-domain@10044060 {
194                         compatible = "samsung,exynos4210-pd";
195                         reg = <0x10044060 0x20>;
196                         #power-domain-cells = <0>;
197                         label = "G3D";
198                 };
199
200                 pd_disp1: power-domain@100440a0 {
201                         compatible = "samsung,exynos4210-pd";
202                         reg = <0x100440A0 0x20>;
203                         #power-domain-cells = <0>;
204                         label = "DISP1";
205                 };
206
207                 pd_mau: power-domain@100440c0 {
208                         compatible = "samsung,exynos4210-pd";
209                         reg = <0x100440C0 0x20>;
210                         #power-domain-cells = <0>;
211                         label = "MAU";
212                 };
213
214                 clock: clock-controller@10010000 {
215                         compatible = "samsung,exynos5250-clock";
216                         reg = <0x10010000 0x30000>;
217                         #clock-cells = <1>;
218                 };
219
220                 clock_audss: audss-clock-controller@3810000 {
221                         compatible = "samsung,exynos5250-audss-clock";
222                         reg = <0x03810000 0x0C>;
223                         #clock-cells = <1>;
224                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
225                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
226                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
227                         power-domains = <&pd_mau>;
228                 };
229
230                 timer {
231                         compatible = "arm,armv7-timer";
232                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
233                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
234                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
235                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
236                         /*
237                          * Unfortunately we need this since some versions
238                          * of U-Boot on Exynos don't set the CNTFRQ register,
239                          * so we need the value from DT.
240                          */
241                         clock-frequency = <24000000>;
242                 };
243
244                 mct@101c0000 {
245                         compatible = "samsung,exynos4210-mct";
246                         reg = <0x101C0000 0x800>;
247                         interrupt-controller;
248                         #interrupt-cells = <2>;
249                         interrupt-parent = <&mct_map>;
250                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
251                                      <4 0>, <5 0>;
252                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
253                         clock-names = "fin_pll", "mct";
254
255                         mct_map: mct-map {
256                                 #interrupt-cells = <2>;
257                                 #address-cells = <0>;
258                                 #size-cells = <0>;
259                                 interrupt-map = <0x0 0 &combiner 23 3>,
260                                                 <0x1 0 &combiner 23 4>,
261                                                 <0x2 0 &combiner 25 2>,
262                                                 <0x3 0 &combiner 25 3>,
263                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
264                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
265                         };
266                 };
267
268                 pmu {
269                         compatible = "arm,cortex-a15-pmu";
270                         interrupt-parent = <&combiner>;
271                         interrupts = <1 2>, <22 4>;
272                 };
273
274                 pinctrl_0: pinctrl@11400000 {
275                         compatible = "samsung,exynos5250-pinctrl";
276                         reg = <0x11400000 0x1000>;
277                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
278
279                         wakup_eint: wakeup-interrupt-controller {
280                                 compatible = "samsung,exynos4210-wakeup-eint";
281                                 interrupt-parent = <&gic>;
282                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
283                         };
284                 };
285
286                 pinctrl_1: pinctrl@13400000 {
287                         compatible = "samsung,exynos5250-pinctrl";
288                         reg = <0x13400000 0x1000>;
289                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
290                 };
291
292                 pinctrl_2: pinctrl@10d10000 {
293                         compatible = "samsung,exynos5250-pinctrl";
294                         reg = <0x10d10000 0x1000>;
295                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
296                 };
297
298                 pinctrl_3: pinctrl@3860000 {
299                         compatible = "samsung,exynos5250-pinctrl";
300                         reg = <0x03860000 0x1000>;
301                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
302                         power-domains = <&pd_mau>;
303                 };
304
305                 pmu_system_controller: system-controller@10040000 {
306                         compatible = "samsung,exynos5250-pmu", "syscon";
307                         reg = <0x10040000 0x5000>;
308                         clock-names = "clkout16";
309                         clocks = <&clock CLK_FIN_PLL>;
310                         #clock-cells = <1>;
311                         interrupt-controller;
312                         #interrupt-cells = <3>;
313                         interrupt-parent = <&gic>;
314                 };
315
316                 watchdog@101d0000 {
317                         compatible = "samsung,exynos5250-wdt";
318                         reg = <0x101D0000 0x100>;
319                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
320                         clocks = <&clock CLK_WDT>;
321                         clock-names = "watchdog";
322                         samsung,syscon-phandle = <&pmu_system_controller>;
323                 };
324
325                 mfc: codec@11000000 {
326                         compatible = "samsung,mfc-v6";
327                         reg = <0x11000000 0x10000>;
328                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
329                         power-domains = <&pd_mfc>;
330                         clocks = <&clock CLK_MFC>;
331                         clock-names = "mfc";
332                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
333                         iommu-names = "left", "right";
334                 };
335
336                 rotator: rotator@11c00000 {
337                         compatible = "samsung,exynos5250-rotator";
338                         reg = <0x11C00000 0x64>;
339                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
340                         clocks = <&clock CLK_ROTATOR>;
341                         clock-names = "rotator";
342                         iommus = <&sysmmu_rotator>;
343                 };
344
345                 tmu: tmu@10060000 {
346                         compatible = "samsung,exynos5250-tmu";
347                         reg = <0x10060000 0x100>;
348                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
349                         clocks = <&clock CLK_TMU>;
350                         clock-names = "tmu_apbif";
351                         #thermal-sensor-cells = <0>;
352                 };
353
354                 sata: sata@122f0000 {
355                         compatible = "snps,dwc-ahci";
356                         samsung,sata-freq = <66>;
357                         reg = <0x122F0000 0x1ff>;
358                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
359                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
360                         clock-names = "sata", "sclk_sata";
361                         phys = <&sata_phy>;
362                         phy-names = "sata-phy";
363                         status = "disabled";
364                 };
365
366                 sata_phy: sata-phy@12170000 {
367                         compatible = "samsung,exynos5250-sata-phy";
368                         reg = <0x12170000 0x1ff>;
369                         clocks = <&clock CLK_SATA_PHYCTRL>;
370                         clock-names = "sata_phyctrl";
371                         #phy-cells = <0>;
372                         samsung,syscon-phandle = <&pmu_system_controller>;
373                         status = "disabled";
374                 };
375
376                 /* i2c_0-3 are defined in exynos5.dtsi */
377                 i2c_4: i2c@12ca0000 {
378                         compatible = "samsung,s3c2440-i2c";
379                         reg = <0x12CA0000 0x100>;
380                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
381                         #address-cells = <1>;
382                         #size-cells = <0>;
383                         clocks = <&clock CLK_I2C4>;
384                         clock-names = "i2c";
385                         pinctrl-names = "default";
386                         pinctrl-0 = <&i2c4_bus>;
387                         status = "disabled";
388                 };
389
390                 i2c_5: i2c@12cb0000 {
391                         compatible = "samsung,s3c2440-i2c";
392                         reg = <0x12CB0000 0x100>;
393                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
394                         #address-cells = <1>;
395                         #size-cells = <0>;
396                         clocks = <&clock CLK_I2C5>;
397                         clock-names = "i2c";
398                         pinctrl-names = "default";
399                         pinctrl-0 = <&i2c5_bus>;
400                         status = "disabled";
401                 };
402
403                 i2c_6: i2c@12cc0000 {
404                         compatible = "samsung,s3c2440-i2c";
405                         reg = <0x12CC0000 0x100>;
406                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
407                         #address-cells = <1>;
408                         #size-cells = <0>;
409                         clocks = <&clock CLK_I2C6>;
410                         clock-names = "i2c";
411                         pinctrl-names = "default";
412                         pinctrl-0 = <&i2c6_bus>;
413                         status = "disabled";
414                 };
415
416                 i2c_7: i2c@12cd0000 {
417                         compatible = "samsung,s3c2440-i2c";
418                         reg = <0x12CD0000 0x100>;
419                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
420                         #address-cells = <1>;
421                         #size-cells = <0>;
422                         clocks = <&clock CLK_I2C7>;
423                         clock-names = "i2c";
424                         pinctrl-names = "default";
425                         pinctrl-0 = <&i2c7_bus>;
426                         status = "disabled";
427                 };
428
429                 i2c_8: i2c@12ce0000 {
430                         compatible = "samsung,s3c2440-hdmiphy-i2c";
431                         reg = <0x12CE0000 0x1000>;
432                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
433                         #address-cells = <1>;
434                         #size-cells = <0>;
435                         clocks = <&clock CLK_I2C_HDMI>;
436                         clock-names = "i2c";
437                         status = "disabled";
438
439                         hdmiphy: hdmiphy@38 {
440                                 compatible = "samsung,exynos4212-hdmiphy";
441                                 reg = <0x38>;
442                         };
443                 };
444
445                 i2c_9: i2c@121d0000 {
446                         compatible = "samsung,exynos5-sata-phy-i2c";
447                         reg = <0x121D0000 0x100>;
448                         #address-cells = <1>;
449                         #size-cells = <0>;
450                         clocks = <&clock CLK_SATA_PHYI2C>;
451                         clock-names = "i2c";
452                         status = "disabled";
453                 };
454
455                 spi_0: spi@12d20000 {
456                         compatible = "samsung,exynos4210-spi";
457                         status = "disabled";
458                         reg = <0x12d20000 0x100>;
459                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
460                         dmas = <&pdma0 5
461                                 &pdma0 4>;
462                         dma-names = "tx", "rx";
463                         #address-cells = <1>;
464                         #size-cells = <0>;
465                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
466                         clock-names = "spi", "spi_busclk0";
467                         pinctrl-names = "default";
468                         pinctrl-0 = <&spi0_bus>;
469                 };
470
471                 spi_1: spi@12d30000 {
472                         compatible = "samsung,exynos4210-spi";
473                         status = "disabled";
474                         reg = <0x12d30000 0x100>;
475                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
476                         dmas = <&pdma1 5
477                                 &pdma1 4>;
478                         dma-names = "tx", "rx";
479                         #address-cells = <1>;
480                         #size-cells = <0>;
481                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
482                         clock-names = "spi", "spi_busclk0";
483                         pinctrl-names = "default";
484                         pinctrl-0 = <&spi1_bus>;
485                 };
486
487                 spi_2: spi@12d40000 {
488                         compatible = "samsung,exynos4210-spi";
489                         status = "disabled";
490                         reg = <0x12d40000 0x100>;
491                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
492                         dmas = <&pdma0 7
493                                 &pdma0 6>;
494                         dma-names = "tx", "rx";
495                         #address-cells = <1>;
496                         #size-cells = <0>;
497                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
498                         clock-names = "spi", "spi_busclk0";
499                         pinctrl-names = "default";
500                         pinctrl-0 = <&spi2_bus>;
501                 };
502
503                 mmc_0: mmc@12200000 {
504                         compatible = "samsung,exynos5250-dw-mshc";
505                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
506                         #address-cells = <1>;
507                         #size-cells = <0>;
508                         reg = <0x12200000 0x1000>;
509                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
510                         clock-names = "biu", "ciu";
511                         fifo-depth = <0x80>;
512                         status = "disabled";
513                 };
514
515                 mmc_1: mmc@12210000 {
516                         compatible = "samsung,exynos5250-dw-mshc";
517                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
518                         #address-cells = <1>;
519                         #size-cells = <0>;
520                         reg = <0x12210000 0x1000>;
521                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
522                         clock-names = "biu", "ciu";
523                         fifo-depth = <0x80>;
524                         status = "disabled";
525                 };
526
527                 mmc_2: mmc@12220000 {
528                         compatible = "samsung,exynos5250-dw-mshc";
529                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
530                         #address-cells = <1>;
531                         #size-cells = <0>;
532                         reg = <0x12220000 0x1000>;
533                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
534                         clock-names = "biu", "ciu";
535                         fifo-depth = <0x80>;
536                         status = "disabled";
537                 };
538
539                 mmc_3: mmc@12230000 {
540                         compatible = "samsung,exynos5250-dw-mshc";
541                         reg = <0x12230000 0x1000>;
542                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
543                         #address-cells = <1>;
544                         #size-cells = <0>;
545                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
546                         clock-names = "biu", "ciu";
547                         fifo-depth = <0x80>;
548                         status = "disabled";
549                 };
550
551                 i2s0: i2s@3830000 {
552                         compatible = "samsung,s5pv210-i2s";
553                         status = "disabled";
554                         reg = <0x03830000 0x100>;
555                         dmas = <&pdma0 10
556                                 &pdma0 9
557                                 &pdma0 8>;
558                         dma-names = "tx", "rx", "tx-sec";
559                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
560                                 <&clock_audss EXYNOS_I2S_BUS>,
561                                 <&clock_audss EXYNOS_SCLK_I2S>;
562                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
563                         samsung,idma-addr = <0x03000000>;
564                         pinctrl-names = "default";
565                         pinctrl-0 = <&i2s0_bus>;
566                         power-domains = <&pd_mau>;
567                         #clock-cells = <1>;
568                         #sound-dai-cells = <1>;
569                 };
570
571                 i2s1: i2s@12d60000 {
572                         compatible = "samsung,s3c6410-i2s";
573                         status = "disabled";
574                         reg = <0x12D60000 0x100>;
575                         dmas = <&pdma1 12
576                                 &pdma1 11>;
577                         dma-names = "tx", "rx";
578                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
579                         clock-names = "iis", "i2s_opclk0";
580                         pinctrl-names = "default";
581                         pinctrl-0 = <&i2s1_bus>;
582                         power-domains = <&pd_mau>;
583                         #sound-dai-cells = <1>;
584                 };
585
586                 i2s2: i2s@12d70000 {
587                         compatible = "samsung,s3c6410-i2s";
588                         status = "disabled";
589                         reg = <0x12D70000 0x100>;
590                         dmas = <&pdma0 12
591                                 &pdma0 11>;
592                         dma-names = "tx", "rx";
593                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
594                         clock-names = "iis", "i2s_opclk0";
595                         pinctrl-names = "default";
596                         pinctrl-0 = <&i2s2_bus>;
597                         power-domains = <&pd_mau>;
598                         #sound-dai-cells = <1>;
599                 };
600
601                 usb_dwc3 {
602                         compatible = "samsung,exynos5250-dwusb3";
603                         clocks = <&clock CLK_USB3>;
604                         clock-names = "usbdrd30";
605                         #address-cells = <1>;
606                         #size-cells = <1>;
607                         ranges;
608
609                         usbdrd_dwc3: dwc3@12000000 {
610                                 compatible = "synopsys,dwc3";
611                                 reg = <0x12000000 0x10000>;
612                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
613                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
614                                 phy-names = "usb2-phy", "usb3-phy";
615                         };
616                 };
617
618                 usbdrd_phy: phy@12100000 {
619                         compatible = "samsung,exynos5250-usbdrd-phy";
620                         reg = <0x12100000 0x100>;
621                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
622                         clock-names = "phy", "ref";
623                         samsung,pmu-syscon = <&pmu_system_controller>;
624                         #phy-cells = <1>;
625                 };
626
627                 ehci: usb@12110000 {
628                         compatible = "samsung,exynos4210-ehci";
629                         reg = <0x12110000 0x100>;
630                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
631
632                         clocks = <&clock CLK_USB2>;
633                         clock-names = "usbhost";
634                         #address-cells = <1>;
635                         #size-cells = <0>;
636                         port@0 {
637                                 reg = <0>;
638                                 phys = <&usb2_phy_gen 1>;
639                         };
640                 };
641
642                 ohci: usb@12120000 {
643                         compatible = "samsung,exynos4210-ohci";
644                         reg = <0x12120000 0x100>;
645                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
646
647                         clocks = <&clock CLK_USB2>;
648                         clock-names = "usbhost";
649                         #address-cells = <1>;
650                         #size-cells = <0>;
651                         port@0 {
652                                 reg = <0>;
653                                 phys = <&usb2_phy_gen 1>;
654                         };
655                 };
656
657                 usb2_phy_gen: phy@12130000 {
658                         compatible = "samsung,exynos5250-usb2-phy";
659                         reg = <0x12130000 0x100>;
660                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
661                         clock-names = "phy", "ref";
662                         #phy-cells = <1>;
663                         samsung,sysreg-phandle = <&sysreg_system_controller>;
664                         samsung,pmureg-phandle = <&pmu_system_controller>;
665                 };
666
667                 amba {
668                         #address-cells = <1>;
669                         #size-cells = <1>;
670                         compatible = "simple-bus";
671                         interrupt-parent = <&gic>;
672                         ranges;
673
674                         pdma0: pdma@121a0000 {
675                                 compatible = "arm,pl330", "arm,primecell";
676                                 reg = <0x121A0000 0x1000>;
677                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
678                                 clocks = <&clock CLK_PDMA0>;
679                                 clock-names = "apb_pclk";
680                                 #dma-cells = <1>;
681                                 #dma-channels = <8>;
682                                 #dma-requests = <32>;
683                         };
684
685                         pdma1: pdma@121b0000 {
686                                 compatible = "arm,pl330", "arm,primecell";
687                                 reg = <0x121B0000 0x1000>;
688                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
689                                 clocks = <&clock CLK_PDMA1>;
690                                 clock-names = "apb_pclk";
691                                 #dma-cells = <1>;
692                                 #dma-channels = <8>;
693                                 #dma-requests = <32>;
694                         };
695
696                         mdma0: mdma@10800000 {
697                                 compatible = "arm,pl330", "arm,primecell";
698                                 reg = <0x10800000 0x1000>;
699                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
700                                 clocks = <&clock CLK_MDMA0>;
701                                 clock-names = "apb_pclk";
702                                 #dma-cells = <1>;
703                                 #dma-channels = <8>;
704                                 #dma-requests = <1>;
705                         };
706
707                         mdma1: mdma@11c10000 {
708                                 compatible = "arm,pl330", "arm,primecell";
709                                 reg = <0x11C10000 0x1000>;
710                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
711                                 clocks = <&clock CLK_MDMA1>;
712                                 clock-names = "apb_pclk";
713                                 #dma-cells = <1>;
714                                 #dma-channels = <8>;
715                                 #dma-requests = <1>;
716                         };
717                 };
718
719                 gsc_0:  gsc@13e00000 {
720                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
721                         reg = <0x13e00000 0x1000>;
722                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
723                         power-domains = <&pd_gsc>;
724                         clocks = <&clock CLK_GSCL0>;
725                         clock-names = "gscl";
726                         iommus = <&sysmmu_gsc0>;
727                 };
728
729                 gsc_1:  gsc@13e10000 {
730                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
731                         reg = <0x13e10000 0x1000>;
732                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
733                         power-domains = <&pd_gsc>;
734                         clocks = <&clock CLK_GSCL1>;
735                         clock-names = "gscl";
736                         iommus = <&sysmmu_gsc1>;
737                 };
738
739                 gsc_2:  gsc@13e20000 {
740                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
741                         reg = <0x13e20000 0x1000>;
742                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
743                         power-domains = <&pd_gsc>;
744                         clocks = <&clock CLK_GSCL2>;
745                         clock-names = "gscl";
746                         iommus = <&sysmmu_gsc2>;
747                 };
748
749                 gsc_3:  gsc@13e30000 {
750                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
751                         reg = <0x13e30000 0x1000>;
752                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
753                         power-domains = <&pd_gsc>;
754                         clocks = <&clock CLK_GSCL3>;
755                         clock-names = "gscl";
756                         iommus = <&sysmmu_gsc3>;
757                 };
758
759                 hdmi: hdmi@14530000 {
760                         compatible = "samsung,exynos4212-hdmi";
761                         reg = <0x14530000 0x70000>;
762                         power-domains = <&pd_disp1>;
763                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
764                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
765                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
766                                  <&clock CLK_MOUT_HDMI>;
767                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
768                                         "sclk_hdmiphy", "mout_hdmi";
769                         samsung,syscon-phandle = <&pmu_system_controller>;
770                         phy = <&hdmiphy>;
771                         #sound-dai-cells = <0>;
772                         status = "disabled";
773                 };
774
775                 hdmicec: cec@101b0000 {
776                         compatible = "samsung,s5p-cec";
777                         reg = <0x101B0000 0x200>;
778                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
779                         clocks = <&clock CLK_HDMI_CEC>;
780                         clock-names = "hdmicec";
781                         samsung,syscon-phandle = <&pmu_system_controller>;
782                         hdmi-phandle = <&hdmi>;
783                         pinctrl-names = "default";
784                         pinctrl-0 = <&hdmi_cec>;
785                         status = "disabled";
786                 };
787
788                 mixer: mixer@14450000 {
789                         compatible = "samsung,exynos5250-mixer";
790                         reg = <0x14450000 0x10000>;
791                         power-domains = <&pd_disp1>;
792                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
793                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
794                                  <&clock CLK_SCLK_HDMI>;
795                         clock-names = "mixer", "hdmi", "sclk_hdmi";
796                         iommus = <&sysmmu_tv>;
797                         status = "disabled";
798                 };
799
800                 dp_phy: video-phy {
801                         compatible = "samsung,exynos5250-dp-video-phy";
802                         samsung,pmu-syscon = <&pmu_system_controller>;
803                         #phy-cells = <0>;
804                 };
805
806                 adc: adc@12d10000 {
807                         compatible = "samsung,exynos-adc-v1";
808                         reg = <0x12D10000 0x100>;
809                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
810                         clocks = <&clock CLK_ADC>;
811                         clock-names = "adc";
812                         #io-channel-cells = <1>;
813                         io-channel-ranges;
814                         samsung,syscon-phandle = <&pmu_system_controller>;
815                         status = "disabled";
816                 };
817
818                 sysmmu_g2d: sysmmu@10a60000 {
819                         compatible = "samsung,exynos-sysmmu";
820                         reg = <0x10A60000 0x1000>;
821                         interrupt-parent = <&combiner>;
822                         interrupts = <24 5>;
823                         clock-names = "sysmmu", "master";
824                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
825                         #iommu-cells = <0>;
826                 };
827
828                 sysmmu_mfc_r: sysmmu@11200000 {
829                         compatible = "samsung,exynos-sysmmu";
830                         reg = <0x11200000 0x1000>;
831                         interrupt-parent = <&combiner>;
832                         interrupts = <6 2>;
833                         power-domains = <&pd_mfc>;
834                         clock-names = "sysmmu", "master";
835                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
836                         #iommu-cells = <0>;
837                 };
838
839                 sysmmu_mfc_l: sysmmu@11210000 {
840                         compatible = "samsung,exynos-sysmmu";
841                         reg = <0x11210000 0x1000>;
842                         interrupt-parent = <&combiner>;
843                         interrupts = <8 5>;
844                         power-domains = <&pd_mfc>;
845                         clock-names = "sysmmu", "master";
846                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
847                         #iommu-cells = <0>;
848                 };
849
850                 sysmmu_rotator: sysmmu@11d40000 {
851                         compatible = "samsung,exynos-sysmmu";
852                         reg = <0x11D40000 0x1000>;
853                         interrupt-parent = <&combiner>;
854                         interrupts = <4 0>;
855                         clock-names = "sysmmu", "master";
856                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
857                         #iommu-cells = <0>;
858                 };
859
860                 sysmmu_jpeg: sysmmu@11f20000 {
861                         compatible = "samsung,exynos-sysmmu";
862                         reg = <0x11F20000 0x1000>;
863                         interrupt-parent = <&combiner>;
864                         interrupts = <4 2>;
865                         power-domains = <&pd_gsc>;
866                         clock-names = "sysmmu", "master";
867                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
868                         #iommu-cells = <0>;
869                 };
870
871                 sysmmu_fimc_isp: sysmmu@13260000 {
872                         compatible = "samsung,exynos-sysmmu";
873                         reg = <0x13260000 0x1000>;
874                         interrupt-parent = <&combiner>;
875                         interrupts = <10 6>;
876                         clock-names = "sysmmu";
877                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
878                         #iommu-cells = <0>;
879                 };
880
881                 sysmmu_fimc_drc: sysmmu@13270000 {
882                         compatible = "samsung,exynos-sysmmu";
883                         reg = <0x13270000 0x1000>;
884                         interrupt-parent = <&combiner>;
885                         interrupts = <11 6>;
886                         clock-names = "sysmmu";
887                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
888                         #iommu-cells = <0>;
889                 };
890
891                 sysmmu_fimc_fd: sysmmu@132a0000 {
892                         compatible = "samsung,exynos-sysmmu";
893                         reg = <0x132A0000 0x1000>;
894                         interrupt-parent = <&combiner>;
895                         interrupts = <5 0>;
896                         clock-names = "sysmmu";
897                         clocks = <&clock CLK_SMMU_FIMC_FD>;
898                         #iommu-cells = <0>;
899                 };
900
901                 sysmmu_fimc_scc: sysmmu@13280000 {
902                         compatible = "samsung,exynos-sysmmu";
903                         reg = <0x13280000 0x1000>;
904                         interrupt-parent = <&combiner>;
905                         interrupts = <5 2>;
906                         clock-names = "sysmmu";
907                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
908                         #iommu-cells = <0>;
909                 };
910
911                 sysmmu_fimc_scp: sysmmu@13290000 {
912                         compatible = "samsung,exynos-sysmmu";
913                         reg = <0x13290000 0x1000>;
914                         interrupt-parent = <&combiner>;
915                         interrupts = <3 6>;
916                         clock-names = "sysmmu";
917                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
918                         #iommu-cells = <0>;
919                 };
920
921                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
922                         compatible = "samsung,exynos-sysmmu";
923                         reg = <0x132B0000 0x1000>;
924                         interrupt-parent = <&combiner>;
925                         interrupts = <5 4>;
926                         clock-names = "sysmmu";
927                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
928                         #iommu-cells = <0>;
929                 };
930
931                 sysmmu_fimc_odc: sysmmu@132c0000 {
932                         compatible = "samsung,exynos-sysmmu";
933                         reg = <0x132C0000 0x1000>;
934                         interrupt-parent = <&combiner>;
935                         interrupts = <11 0>;
936                         clock-names = "sysmmu";
937                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
938                         #iommu-cells = <0>;
939                 };
940
941                 sysmmu_fimc_dis0: sysmmu@132d0000 {
942                         compatible = "samsung,exynos-sysmmu";
943                         reg = <0x132D0000 0x1000>;
944                         interrupt-parent = <&combiner>;
945                         interrupts = <10 4>;
946                         clock-names = "sysmmu";
947                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
948                         #iommu-cells = <0>;
949                 };
950
951                 sysmmu_fimc_dis1: sysmmu@132e0000 {
952                         compatible = "samsung,exynos-sysmmu";
953                         reg = <0x132E0000 0x1000>;
954                         interrupt-parent = <&combiner>;
955                         interrupts = <9 4>;
956                         clock-names = "sysmmu";
957                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
958                         #iommu-cells = <0>;
959                 };
960
961                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
962                         compatible = "samsung,exynos-sysmmu";
963                         reg = <0x132F0000 0x1000>;
964                         interrupt-parent = <&combiner>;
965                         interrupts = <5 6>;
966                         clock-names = "sysmmu";
967                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
968                         #iommu-cells = <0>;
969                 };
970
971                 sysmmu_fimc_lite0: sysmmu@13c40000 {
972                         compatible = "samsung,exynos-sysmmu";
973                         reg = <0x13C40000 0x1000>;
974                         interrupt-parent = <&combiner>;
975                         interrupts = <3 4>;
976                         power-domains = <&pd_gsc>;
977                         clock-names = "sysmmu", "master";
978                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
979                         #iommu-cells = <0>;
980                 };
981
982                 sysmmu_fimc_lite1: sysmmu@13c50000 {
983                         compatible = "samsung,exynos-sysmmu";
984                         reg = <0x13C50000 0x1000>;
985                         interrupt-parent = <&combiner>;
986                         interrupts = <24 1>;
987                         power-domains = <&pd_gsc>;
988                         clock-names = "sysmmu", "master";
989                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
990                         #iommu-cells = <0>;
991                 };
992
993                 sysmmu_gsc0: sysmmu@13e80000 {
994                         compatible = "samsung,exynos-sysmmu";
995                         reg = <0x13E80000 0x1000>;
996                         interrupt-parent = <&combiner>;
997                         interrupts = <2 0>;
998                         power-domains = <&pd_gsc>;
999                         clock-names = "sysmmu", "master";
1000                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1001                         #iommu-cells = <0>;
1002                 };
1003
1004                 sysmmu_gsc1: sysmmu@13e90000 {
1005                         compatible = "samsung,exynos-sysmmu";
1006                         reg = <0x13E90000 0x1000>;
1007                         interrupt-parent = <&combiner>;
1008                         interrupts = <2 2>;
1009                         power-domains = <&pd_gsc>;
1010                         clock-names = "sysmmu", "master";
1011                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1012                         #iommu-cells = <0>;
1013                 };
1014
1015                 sysmmu_gsc2: sysmmu@13ea0000 {
1016                         compatible = "samsung,exynos-sysmmu";
1017                         reg = <0x13EA0000 0x1000>;
1018                         interrupt-parent = <&combiner>;
1019                         interrupts = <2 4>;
1020                         power-domains = <&pd_gsc>;
1021                         clock-names = "sysmmu", "master";
1022                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1023                         #iommu-cells = <0>;
1024                 };
1025
1026                 sysmmu_gsc3: sysmmu@13eb0000 {
1027                         compatible = "samsung,exynos-sysmmu";
1028                         reg = <0x13EB0000 0x1000>;
1029                         interrupt-parent = <&combiner>;
1030                         interrupts = <2 6>;
1031                         power-domains = <&pd_gsc>;
1032                         clock-names = "sysmmu", "master";
1033                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1034                         #iommu-cells = <0>;
1035                 };
1036
1037                 sysmmu_fimd1: sysmmu@14640000 {
1038                         compatible = "samsung,exynos-sysmmu";
1039                         reg = <0x14640000 0x1000>;
1040                         interrupt-parent = <&combiner>;
1041                         interrupts = <3 2>;
1042                         power-domains = <&pd_disp1>;
1043                         clock-names = "sysmmu", "master";
1044                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1045                         #iommu-cells = <0>;
1046                 };
1047
1048                 sysmmu_tv: sysmmu@14650000 {
1049                         compatible = "samsung,exynos-sysmmu";
1050                         reg = <0x14650000 0x1000>;
1051                         interrupt-parent = <&combiner>;
1052                         interrupts = <7 4>;
1053                         power-domains = <&pd_disp1>;
1054                         clock-names = "sysmmu", "master";
1055                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1056                         #iommu-cells = <0>;
1057                 };
1058         };
1059
1060         thermal-zones {
1061                 cpu_thermal: cpu-thermal {
1062                         polling-delay-passive = <0>;
1063                         polling-delay = <0>;
1064                         thermal-sensors = <&tmu 0>;
1065
1066                         cooling-maps {
1067                                 map0 {
1068                                      /* Corresponds to 800MHz at freq_table */
1069                                      cooling-device = <&cpu0 9 9>;
1070                                 };
1071                                 map1 {
1072                                      /* Corresponds to 200MHz at freq_table */
1073                                      cooling-device = <&cpu0 15 15>;
1074                                };
1075                        };
1076                 };
1077         };
1078 };
1079
1080 &dp {
1081         power-domains = <&pd_disp1>;
1082         clocks = <&clock CLK_DP>;
1083         clock-names = "dp";
1084         phys = <&dp_phy>;
1085         phy-names = "dp";
1086 };
1087
1088 &fimd {
1089         power-domains = <&pd_disp1>;
1090         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1091         clock-names = "sclk_fimd", "fimd";
1092         iommus = <&sysmmu_fimd1>;
1093 };
1094
1095 &g2d {
1096         iommus = <&sysmmu_g2d>;
1097         clocks = <&clock CLK_G2D>;
1098         clock-names = "fimg2d";
1099         status = "okay";
1100 };
1101
1102 &i2c_0 {
1103         clocks = <&clock CLK_I2C0>;
1104         clock-names = "i2c";
1105         pinctrl-names = "default";
1106         pinctrl-0 = <&i2c0_bus>;
1107 };
1108
1109 &i2c_1 {
1110         clocks = <&clock CLK_I2C1>;
1111         clock-names = "i2c";
1112         pinctrl-names = "default";
1113         pinctrl-0 = <&i2c1_bus>;
1114 };
1115
1116 &i2c_2 {
1117         clocks = <&clock CLK_I2C2>;
1118         clock-names = "i2c";
1119         pinctrl-names = "default";
1120         pinctrl-0 = <&i2c2_bus>;
1121 };
1122
1123 &i2c_3 {
1124         clocks = <&clock CLK_I2C3>;
1125         clock-names = "i2c";
1126         pinctrl-names = "default";
1127         pinctrl-0 = <&i2c3_bus>;
1128 };
1129
1130 &prng {
1131         clocks = <&clock CLK_SSS>;
1132         clock-names = "secss";
1133 };
1134
1135 &pwm {
1136         clocks = <&clock CLK_PWM>;
1137         clock-names = "timers";
1138 };
1139
1140 &rtc {
1141         clocks = <&clock CLK_RTC>;
1142         clock-names = "rtc";
1143         interrupt-parent = <&pmu_system_controller>;
1144         status = "disabled";
1145 };
1146
1147 &serial_0 {
1148         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1149         clock-names = "uart", "clk_uart_baud0";
1150         dmas = <&pdma0 13>, <&pdma0 14>;
1151         dma-names = "rx", "tx";
1152 };
1153
1154 &serial_1 {
1155         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1156         clock-names = "uart", "clk_uart_baud0";
1157         dmas = <&pdma1 15>, <&pdma1 16>;
1158         dma-names = "rx", "tx";
1159 };
1160
1161 &serial_2 {
1162         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1163         clock-names = "uart", "clk_uart_baud0";
1164         dmas = <&pdma0 15>, <&pdma0 16>;
1165         dma-names = "rx", "tx";
1166 };
1167
1168 &serial_3 {
1169         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1170         clock-names = "uart", "clk_uart_baud0";
1171         dmas = <&pdma1 17>, <&pdma1 18>;
1172         dma-names = "rx", "tx";
1173 };
1174
1175 &sss {
1176         clocks = <&clock CLK_SSS>;
1177         clock-names = "secss";
1178 };
1179
1180 &trng {
1181         clocks = <&clock CLK_SSS>;
1182         clock-names = "secss";
1183 };
1184
1185 #include "exynos5250-pinctrl.dtsi"
1186 #include "exynos-syscon-restart.dtsi"