1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
10 * values for board specfic bindings.
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file.
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
66 compatible = "arm,cortex-a15";
68 clocks = <&clock CLK_ARM_CLK>;
70 operating-points-v2 = <&cpu0_opp_table>;
71 #cooling-cells = <2>; /* min followed by max */
75 compatible = "arm,cortex-a15";
77 clocks = <&clock CLK_ARM_CLK>;
79 operating-points-v2 = <&cpu0_opp_table>;
80 #cooling-cells = <2>; /* min followed by max */
84 cpu0_opp_table: opp-table0 {
85 compatible = "operating-points-v2";
89 opp-hz = /bits/ 64 <200000000>;
90 opp-microvolt = <925000>;
91 clock-latency-ns = <140000>;
94 opp-hz = /bits/ 64 <300000000>;
95 opp-microvolt = <937500>;
96 clock-latency-ns = <140000>;
99 opp-hz = /bits/ 64 <400000000>;
100 opp-microvolt = <950000>;
101 clock-latency-ns = <140000>;
104 opp-hz = /bits/ 64 <500000000>;
105 opp-microvolt = <975000>;
106 clock-latency-ns = <140000>;
109 opp-hz = /bits/ 64 <600000000>;
110 opp-microvolt = <1000000>;
111 clock-latency-ns = <140000>;
114 opp-hz = /bits/ 64 <700000000>;
115 opp-microvolt = <1012500>;
116 clock-latency-ns = <140000>;
119 opp-hz = /bits/ 64 <800000000>;
120 opp-microvolt = <1025000>;
121 clock-latency-ns = <140000>;
124 opp-hz = /bits/ 64 <900000000>;
125 opp-microvolt = <1050000>;
126 clock-latency-ns = <140000>;
129 opp-hz = /bits/ 64 <1000000000>;
130 opp-microvolt = <1075000>;
131 clock-latency-ns = <140000>;
135 opp-hz = /bits/ 64 <1100000000>;
136 opp-microvolt = <1100000>;
137 clock-latency-ns = <140000>;
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1125000>;
142 clock-latency-ns = <140000>;
145 opp-hz = /bits/ 64 <1300000000>;
146 opp-microvolt = <1150000>;
147 clock-latency-ns = <140000>;
150 opp-hz = /bits/ 64 <1400000000>;
151 opp-microvolt = <1200000>;
152 clock-latency-ns = <140000>;
155 opp-hz = /bits/ 64 <1500000000>;
156 opp-microvolt = <1225000>;
157 clock-latency-ns = <140000>;
160 opp-hz = /bits/ 64 <1600000000>;
161 opp-microvolt = <1250000>;
162 clock-latency-ns = <140000>;
165 opp-hz = /bits/ 64 <1700000000>;
166 opp-microvolt = <1300000>;
167 clock-latency-ns = <140000>;
172 compatible = "arm,cortex-a15-pmu";
173 interrupt-parent = <&combiner>;
174 interrupts = <1 2>, <22 4>;
179 compatible = "mmio-sram";
180 reg = <0x02020000 0x30000>;
181 #address-cells = <1>;
183 ranges = <0 0x02020000 0x30000>;
186 compatible = "samsung,exynos4210-sysram";
191 compatible = "samsung,exynos4210-sysram-ns";
192 reg = <0x2f000 0x1000>;
196 pd_gsc: power-domain@10044000 {
197 compatible = "samsung,exynos4210-pd";
198 reg = <0x10044000 0x20>;
199 #power-domain-cells = <0>;
203 pd_mfc: power-domain@10044040 {
204 compatible = "samsung,exynos4210-pd";
205 reg = <0x10044040 0x20>;
206 #power-domain-cells = <0>;
210 pd_g3d: power-domain@10044060 {
211 compatible = "samsung,exynos4210-pd";
212 reg = <0x10044060 0x20>;
213 #power-domain-cells = <0>;
217 pd_disp1: power-domain@100440a0 {
218 compatible = "samsung,exynos4210-pd";
219 reg = <0x100440A0 0x20>;
220 #power-domain-cells = <0>;
224 pd_mau: power-domain@100440c0 {
225 compatible = "samsung,exynos4210-pd";
226 reg = <0x100440C0 0x20>;
227 #power-domain-cells = <0>;
231 clock: clock-controller@10010000 {
232 compatible = "samsung,exynos5250-clock";
233 reg = <0x10010000 0x30000>;
237 clock_audss: audss-clock-controller@3810000 {
238 compatible = "samsung,exynos5250-audss-clock";
239 reg = <0x03810000 0x0C>;
241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
242 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
243 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
244 power-domains = <&pd_mau>;
248 compatible = "samsung,exynos4210-mct";
249 reg = <0x101C0000 0x800>;
250 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
251 clock-names = "fin_pll", "mct";
252 interrupts-extended = <&combiner 23 3>,
256 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
257 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
260 pinctrl_0: pinctrl@11400000 {
261 compatible = "samsung,exynos5250-pinctrl";
262 reg = <0x11400000 0x1000>;
263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
265 wakup_eint: wakeup-interrupt-controller {
266 compatible = "samsung,exynos4210-wakeup-eint";
267 interrupt-parent = <&gic>;
268 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
272 pinctrl_1: pinctrl@13400000 {
273 compatible = "samsung,exynos5250-pinctrl";
274 reg = <0x13400000 0x1000>;
275 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
278 pinctrl_2: pinctrl@10d10000 {
279 compatible = "samsung,exynos5250-pinctrl";
280 reg = <0x10d10000 0x1000>;
281 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
284 pinctrl_3: pinctrl@3860000 {
285 compatible = "samsung,exynos5250-pinctrl";
286 reg = <0x03860000 0x1000>;
287 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
288 power-domains = <&pd_mau>;
291 pmu_system_controller: system-controller@10040000 {
292 compatible = "samsung,exynos5250-pmu", "syscon";
293 reg = <0x10040000 0x5000>;
294 clock-names = "clkout16";
295 clocks = <&clock CLK_FIN_PLL>;
297 interrupt-controller;
298 #interrupt-cells = <3>;
299 interrupt-parent = <&gic>;
303 compatible = "samsung,exynos5250-wdt";
304 reg = <0x101D0000 0x100>;
305 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&clock CLK_WDT>;
307 clock-names = "watchdog";
308 samsung,syscon-phandle = <&pmu_system_controller>;
311 mfc: codec@11000000 {
312 compatible = "samsung,mfc-v6";
313 reg = <0x11000000 0x10000>;
314 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
315 power-domains = <&pd_mfc>;
316 clocks = <&clock CLK_MFC>;
318 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
319 iommu-names = "left", "right";
322 rotator: rotator@11c00000 {
323 compatible = "samsung,exynos5250-rotator";
324 reg = <0x11C00000 0x64>;
325 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clock CLK_ROTATOR>;
327 clock-names = "rotator";
328 iommus = <&sysmmu_rotator>;
332 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
333 reg = <0x11800000 0x5000>;
334 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
337 interrupt-names = "job", "mmu", "gpu";
338 clocks = <&clock CLK_G3D>;
339 clock-names = "core";
340 operating-points-v2 = <&gpu_opp_table>;
341 power-domains = <&pd_g3d>;
344 gpu_opp_table: opp-table {
345 compatible = "operating-points-v2";
348 opp-hz = /bits/ 64 <100000000>;
349 opp-microvolt = <925000>;
352 opp-hz = /bits/ 64 <160000000>;
353 opp-microvolt = <925000>;
356 opp-hz = /bits/ 64 <266000000>;
357 opp-microvolt = <1025000>;
360 opp-hz = /bits/ 64 <350000000>;
361 opp-microvolt = <1075000>;
364 opp-hz = /bits/ 64 <400000000>;
365 opp-microvolt = <1125000>;
368 opp-hz = /bits/ 64 <450000000>;
369 opp-microvolt = <1150000>;
372 opp-hz = /bits/ 64 <533000000>;
373 opp-microvolt = <1250000>;
379 compatible = "samsung,exynos5250-tmu";
380 reg = <0x10060000 0x100>;
381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clock CLK_TMU>;
383 clock-names = "tmu_apbif";
384 #thermal-sensor-cells = <0>;
387 sata: sata@122f0000 {
388 compatible = "snps,dwc-ahci";
389 samsung,sata-freq = <66>;
390 reg = <0x122F0000 0x1ff>;
391 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
393 clock-names = "sata", "sclk_sata";
395 phy-names = "sata-phy";
396 ports-implemented = <0x1>;
400 sata_phy: sata-phy@12170000 {
401 compatible = "samsung,exynos5250-sata-phy";
402 reg = <0x12170000 0x1ff>;
403 clocks = <&clock CLK_SATA_PHYCTRL>;
404 clock-names = "sata_phyctrl";
406 samsung,syscon-phandle = <&pmu_system_controller>;
410 /* i2c_0-3 are defined in exynos5.dtsi */
411 i2c_4: i2c@12ca0000 {
412 compatible = "samsung,s3c2440-i2c";
413 reg = <0x12CA0000 0x100>;
414 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
417 clocks = <&clock CLK_I2C4>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c4_bus>;
424 i2c_5: i2c@12cb0000 {
425 compatible = "samsung,s3c2440-i2c";
426 reg = <0x12CB0000 0x100>;
427 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
430 clocks = <&clock CLK_I2C5>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c5_bus>;
437 i2c_6: i2c@12cc0000 {
438 compatible = "samsung,s3c2440-i2c";
439 reg = <0x12CC0000 0x100>;
440 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
443 clocks = <&clock CLK_I2C6>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c6_bus>;
450 i2c_7: i2c@12cd0000 {
451 compatible = "samsung,s3c2440-i2c";
452 reg = <0x12CD0000 0x100>;
453 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
454 #address-cells = <1>;
456 clocks = <&clock CLK_I2C7>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&i2c7_bus>;
463 i2c_8: i2c@12ce0000 {
464 compatible = "samsung,s3c2440-hdmiphy-i2c";
465 reg = <0x12CE0000 0x1000>;
466 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
469 clocks = <&clock CLK_I2C_HDMI>;
473 hdmiphy: hdmiphy@38 {
474 compatible = "samsung,exynos4212-hdmiphy";
479 i2c_9: i2c@121d0000 {
480 compatible = "samsung,exynos5-sata-phy-i2c";
481 reg = <0x121D0000 0x100>;
482 #address-cells = <1>;
484 clocks = <&clock CLK_SATA_PHYI2C>;
488 sata_phy_i2c: sata-phy-i2c@38 {
489 compatible = "samsung,exynos-sataphy-i2c";
495 spi_0: spi@12d20000 {
496 compatible = "samsung,exynos4210-spi";
498 reg = <0x12d20000 0x100>;
499 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
502 dma-names = "tx", "rx";
503 #address-cells = <1>;
505 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
506 clock-names = "spi", "spi_busclk0";
507 pinctrl-names = "default";
508 pinctrl-0 = <&spi0_bus>;
511 spi_1: spi@12d30000 {
512 compatible = "samsung,exynos4210-spi";
514 reg = <0x12d30000 0x100>;
515 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
518 dma-names = "tx", "rx";
519 #address-cells = <1>;
521 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
522 clock-names = "spi", "spi_busclk0";
523 pinctrl-names = "default";
524 pinctrl-0 = <&spi1_bus>;
527 spi_2: spi@12d40000 {
528 compatible = "samsung,exynos4210-spi";
530 reg = <0x12d40000 0x100>;
531 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
534 dma-names = "tx", "rx";
535 #address-cells = <1>;
537 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
538 clock-names = "spi", "spi_busclk0";
539 pinctrl-names = "default";
540 pinctrl-0 = <&spi2_bus>;
543 mmc_0: mmc@12200000 {
544 compatible = "samsung,exynos5250-dw-mshc";
545 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
548 reg = <0x12200000 0x1000>;
549 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
550 clock-names = "biu", "ciu";
555 mmc_1: mmc@12210000 {
556 compatible = "samsung,exynos5250-dw-mshc";
557 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
560 reg = <0x12210000 0x1000>;
561 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
562 clock-names = "biu", "ciu";
567 mmc_2: mmc@12220000 {
568 compatible = "samsung,exynos5250-dw-mshc";
569 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
572 reg = <0x12220000 0x1000>;
573 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
574 clock-names = "biu", "ciu";
579 mmc_3: mmc@12230000 {
580 compatible = "samsung,exynos5250-dw-mshc";
581 reg = <0x12230000 0x1000>;
582 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
583 #address-cells = <1>;
585 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
586 clock-names = "biu", "ciu";
592 compatible = "samsung,s5pv210-i2s";
594 reg = <0x03830000 0x100>;
598 dma-names = "tx", "rx", "tx-sec";
599 clocks = <&clock_audss EXYNOS_I2S_BUS>,
600 <&clock_audss EXYNOS_I2S_BUS>,
601 <&clock_audss EXYNOS_SCLK_I2S>;
602 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
603 samsung,idma-addr = <0x03000000>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&i2s0_bus>;
606 power-domains = <&pd_mau>;
608 #sound-dai-cells = <1>;
612 compatible = "samsung,s3c6410-i2s";
614 reg = <0x12D60000 0x100>;
617 dma-names = "tx", "rx";
618 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
619 clock-names = "iis", "i2s_opclk0";
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2s1_bus>;
622 power-domains = <&pd_mau>;
623 #sound-dai-cells = <1>;
627 compatible = "samsung,s3c6410-i2s";
629 reg = <0x12D70000 0x100>;
632 dma-names = "tx", "rx";
633 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
634 clock-names = "iis", "i2s_opclk0";
635 pinctrl-names = "default";
636 pinctrl-0 = <&i2s2_bus>;
637 power-domains = <&pd_mau>;
638 #sound-dai-cells = <1>;
642 compatible = "samsung,exynos5250-dwusb3";
643 clocks = <&clock CLK_USB3>;
644 clock-names = "usbdrd30";
645 #address-cells = <1>;
649 usbdrd_dwc3: usb@12000000 {
650 compatible = "snps,dwc3";
651 reg = <0x12000000 0x10000>;
652 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
653 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
654 phy-names = "usb2-phy", "usb3-phy";
658 usbdrd_phy: phy@12100000 {
659 compatible = "samsung,exynos5250-usbdrd-phy";
660 reg = <0x12100000 0x100>;
661 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
662 clock-names = "phy", "ref";
663 samsung,pmu-syscon = <&pmu_system_controller>;
668 compatible = "samsung,exynos4210-ehci";
669 reg = <0x12110000 0x100>;
670 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clock CLK_USB2>;
673 clock-names = "usbhost";
674 phys = <&usb2_phy_gen 1>;
679 compatible = "samsung,exynos4210-ohci";
680 reg = <0x12120000 0x100>;
681 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clock CLK_USB2>;
684 clock-names = "usbhost";
685 phys = <&usb2_phy_gen 1>;
689 usb2_phy_gen: phy@12130000 {
690 compatible = "samsung,exynos5250-usb2-phy";
691 reg = <0x12130000 0x100>;
692 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
693 clock-names = "phy", "ref";
695 samsung,sysreg-phandle = <&sysreg_system_controller>;
696 samsung,pmureg-phandle = <&pmu_system_controller>;
699 pdma0: pdma@121a0000 {
700 compatible = "arm,pl330", "arm,primecell";
701 reg = <0x121A0000 0x1000>;
702 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clock CLK_PDMA0>;
704 clock-names = "apb_pclk";
707 #dma-requests = <32>;
710 pdma1: pdma@121b0000 {
711 compatible = "arm,pl330", "arm,primecell";
712 reg = <0x121B0000 0x1000>;
713 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clock CLK_PDMA1>;
715 clock-names = "apb_pclk";
718 #dma-requests = <32>;
721 mdma0: mdma@10800000 {
722 compatible = "arm,pl330", "arm,primecell";
723 reg = <0x10800000 0x1000>;
724 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clock CLK_MDMA0>;
726 clock-names = "apb_pclk";
732 mdma1: mdma@11c10000 {
733 compatible = "arm,pl330", "arm,primecell";
734 reg = <0x11C10000 0x1000>;
735 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clock CLK_MDMA1>;
737 clock-names = "apb_pclk";
743 gsc_0: gsc@13e00000 {
744 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
745 reg = <0x13e00000 0x1000>;
746 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
747 power-domains = <&pd_gsc>;
748 clocks = <&clock CLK_GSCL0>;
749 clock-names = "gscl";
750 iommus = <&sysmmu_gsc0>;
753 gsc_1: gsc@13e10000 {
754 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
755 reg = <0x13e10000 0x1000>;
756 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
757 power-domains = <&pd_gsc>;
758 clocks = <&clock CLK_GSCL1>;
759 clock-names = "gscl";
760 iommus = <&sysmmu_gsc1>;
763 gsc_2: gsc@13e20000 {
764 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
765 reg = <0x13e20000 0x1000>;
766 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
767 power-domains = <&pd_gsc>;
768 clocks = <&clock CLK_GSCL2>;
769 clock-names = "gscl";
770 iommus = <&sysmmu_gsc2>;
773 gsc_3: gsc@13e30000 {
774 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
775 reg = <0x13e30000 0x1000>;
776 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
777 power-domains = <&pd_gsc>;
778 clocks = <&clock CLK_GSCL3>;
779 clock-names = "gscl";
780 iommus = <&sysmmu_gsc3>;
783 hdmi: hdmi@14530000 {
784 compatible = "samsung,exynos4212-hdmi";
785 reg = <0x14530000 0x70000>;
786 power-domains = <&pd_disp1>;
787 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
789 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
790 <&clock CLK_MOUT_HDMI>;
791 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
792 "sclk_hdmiphy", "mout_hdmi";
793 samsung,syscon-phandle = <&pmu_system_controller>;
795 #sound-dai-cells = <0>;
799 hdmicec: cec@101b0000 {
800 compatible = "samsung,s5p-cec";
801 reg = <0x101B0000 0x200>;
802 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clock CLK_HDMI_CEC>;
804 clock-names = "hdmicec";
805 samsung,syscon-phandle = <&pmu_system_controller>;
806 hdmi-phandle = <&hdmi>;
807 pinctrl-names = "default";
808 pinctrl-0 = <&hdmi_cec>;
812 mixer: mixer@14450000 {
813 compatible = "samsung,exynos5250-mixer";
814 reg = <0x14450000 0x10000>;
815 power-domains = <&pd_disp1>;
816 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
818 <&clock CLK_SCLK_HDMI>;
819 clock-names = "mixer", "hdmi", "sclk_hdmi";
820 iommus = <&sysmmu_tv>;
825 compatible = "samsung,exynos5250-dp-video-phy";
826 samsung,pmu-syscon = <&pmu_system_controller>;
830 mipi_phy: video-phy@10040710 {
831 compatible = "samsung,s5pv210-mipi-video-phy";
832 reg = <0x10040710 0x100>;
834 syscon = <&pmu_system_controller>;
837 dsi_0: dsi@14500000 {
838 compatible = "samsung,exynos4210-mipi-dsi";
839 reg = <0x14500000 0x10000>;
840 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
841 samsung,power-domain = <&pd_disp1>;
842 phys = <&mipi_phy 3>;
844 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
845 clock-names = "bus_clk", "sclk_mipi";
847 #address-cells = <1>;
852 compatible = "samsung,exynos-adc-v1";
853 reg = <0x12D10000 0x100>;
854 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clock CLK_ADC>;
857 #io-channel-cells = <1>;
858 samsung,syscon-phandle = <&pmu_system_controller>;
862 sysmmu_g2d: sysmmu@10a60000 {
863 compatible = "samsung,exynos-sysmmu";
864 reg = <0x10A60000 0x1000>;
865 interrupt-parent = <&combiner>;
867 clock-names = "sysmmu", "master";
868 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
872 sysmmu_mfc_r: sysmmu@11200000 {
873 compatible = "samsung,exynos-sysmmu";
874 reg = <0x11200000 0x1000>;
875 interrupt-parent = <&combiner>;
877 power-domains = <&pd_mfc>;
878 clock-names = "sysmmu", "master";
879 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
883 sysmmu_mfc_l: sysmmu@11210000 {
884 compatible = "samsung,exynos-sysmmu";
885 reg = <0x11210000 0x1000>;
886 interrupt-parent = <&combiner>;
888 power-domains = <&pd_mfc>;
889 clock-names = "sysmmu", "master";
890 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
894 sysmmu_rotator: sysmmu@11d40000 {
895 compatible = "samsung,exynos-sysmmu";
896 reg = <0x11D40000 0x1000>;
897 interrupt-parent = <&combiner>;
899 clock-names = "sysmmu", "master";
900 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
904 sysmmu_jpeg: sysmmu@11f20000 {
905 compatible = "samsung,exynos-sysmmu";
906 reg = <0x11F20000 0x1000>;
907 interrupt-parent = <&combiner>;
909 power-domains = <&pd_gsc>;
910 clock-names = "sysmmu", "master";
911 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
915 sysmmu_fimc_isp: sysmmu@13260000 {
916 compatible = "samsung,exynos-sysmmu";
917 reg = <0x13260000 0x1000>;
918 interrupt-parent = <&combiner>;
920 clock-names = "sysmmu";
921 clocks = <&clock CLK_SMMU_FIMC_ISP>;
925 sysmmu_fimc_drc: sysmmu@13270000 {
926 compatible = "samsung,exynos-sysmmu";
927 reg = <0x13270000 0x1000>;
928 interrupt-parent = <&combiner>;
930 clock-names = "sysmmu";
931 clocks = <&clock CLK_SMMU_FIMC_DRC>;
935 sysmmu_fimc_fd: sysmmu@132a0000 {
936 compatible = "samsung,exynos-sysmmu";
937 reg = <0x132A0000 0x1000>;
938 interrupt-parent = <&combiner>;
940 clock-names = "sysmmu";
941 clocks = <&clock CLK_SMMU_FIMC_FD>;
945 sysmmu_fimc_scc: sysmmu@13280000 {
946 compatible = "samsung,exynos-sysmmu";
947 reg = <0x13280000 0x1000>;
948 interrupt-parent = <&combiner>;
950 clock-names = "sysmmu";
951 clocks = <&clock CLK_SMMU_FIMC_SCC>;
955 sysmmu_fimc_scp: sysmmu@13290000 {
956 compatible = "samsung,exynos-sysmmu";
957 reg = <0x13290000 0x1000>;
958 interrupt-parent = <&combiner>;
960 clock-names = "sysmmu";
961 clocks = <&clock CLK_SMMU_FIMC_SCP>;
965 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
966 compatible = "samsung,exynos-sysmmu";
967 reg = <0x132B0000 0x1000>;
968 interrupt-parent = <&combiner>;
970 clock-names = "sysmmu";
971 clocks = <&clock CLK_SMMU_FIMC_MCU>;
975 sysmmu_fimc_odc: sysmmu@132c0000 {
976 compatible = "samsung,exynos-sysmmu";
977 reg = <0x132C0000 0x1000>;
978 interrupt-parent = <&combiner>;
980 clock-names = "sysmmu";
981 clocks = <&clock CLK_SMMU_FIMC_ODC>;
985 sysmmu_fimc_dis0: sysmmu@132d0000 {
986 compatible = "samsung,exynos-sysmmu";
987 reg = <0x132D0000 0x1000>;
988 interrupt-parent = <&combiner>;
990 clock-names = "sysmmu";
991 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
995 sysmmu_fimc_dis1: sysmmu@132e0000 {
996 compatible = "samsung,exynos-sysmmu";
997 reg = <0x132E0000 0x1000>;
998 interrupt-parent = <&combiner>;
1000 clock-names = "sysmmu";
1001 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
1005 sysmmu_fimc_3dnr: sysmmu@132f0000 {
1006 compatible = "samsung,exynos-sysmmu";
1007 reg = <0x132F0000 0x1000>;
1008 interrupt-parent = <&combiner>;
1010 clock-names = "sysmmu";
1011 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1015 sysmmu_fimc_lite0: sysmmu@13c40000 {
1016 compatible = "samsung,exynos-sysmmu";
1017 reg = <0x13C40000 0x1000>;
1018 interrupt-parent = <&combiner>;
1020 power-domains = <&pd_gsc>;
1021 clock-names = "sysmmu", "master";
1022 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1026 sysmmu_fimc_lite1: sysmmu@13c50000 {
1027 compatible = "samsung,exynos-sysmmu";
1028 reg = <0x13C50000 0x1000>;
1029 interrupt-parent = <&combiner>;
1030 interrupts = <24 1>;
1031 power-domains = <&pd_gsc>;
1032 clock-names = "sysmmu", "master";
1033 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1037 sysmmu_gsc0: sysmmu@13e80000 {
1038 compatible = "samsung,exynos-sysmmu";
1039 reg = <0x13E80000 0x1000>;
1040 interrupt-parent = <&combiner>;
1042 power-domains = <&pd_gsc>;
1043 clock-names = "sysmmu", "master";
1044 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1048 sysmmu_gsc1: sysmmu@13e90000 {
1049 compatible = "samsung,exynos-sysmmu";
1050 reg = <0x13E90000 0x1000>;
1051 interrupt-parent = <&combiner>;
1053 power-domains = <&pd_gsc>;
1054 clock-names = "sysmmu", "master";
1055 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1059 sysmmu_gsc2: sysmmu@13ea0000 {
1060 compatible = "samsung,exynos-sysmmu";
1061 reg = <0x13EA0000 0x1000>;
1062 interrupt-parent = <&combiner>;
1064 power-domains = <&pd_gsc>;
1065 clock-names = "sysmmu", "master";
1066 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1070 sysmmu_gsc3: sysmmu@13eb0000 {
1071 compatible = "samsung,exynos-sysmmu";
1072 reg = <0x13EB0000 0x1000>;
1073 interrupt-parent = <&combiner>;
1075 power-domains = <&pd_gsc>;
1076 clock-names = "sysmmu", "master";
1077 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1081 sysmmu_fimd1: sysmmu@14640000 {
1082 compatible = "samsung,exynos-sysmmu";
1083 reg = <0x14640000 0x1000>;
1084 interrupt-parent = <&combiner>;
1086 power-domains = <&pd_disp1>;
1087 clock-names = "sysmmu", "master";
1088 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1092 sysmmu_tv: sysmmu@14650000 {
1093 compatible = "samsung,exynos-sysmmu";
1094 reg = <0x14650000 0x1000>;
1095 interrupt-parent = <&combiner>;
1097 power-domains = <&pd_disp1>;
1098 clock-names = "sysmmu", "master";
1099 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1105 compatible = "arm,armv7-timer";
1106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1111 * Unfortunately we need this since some versions
1112 * of U-Boot on Exynos don't set the CNTFRQ register,
1113 * so we need the value from DT.
1115 clock-frequency = <24000000>;
1120 polling-delay-passive = <0>;
1121 polling-delay = <0>;
1122 thermal-sensors = <&tmu 0>;
1126 /* Corresponds to 800MHz at freq_table */
1127 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1130 /* Corresponds to 200MHz at freq_table */
1131 cooling-device = <&cpu0 15 15>,
1138 power-domains = <&pd_disp1>;
1139 clocks = <&clock CLK_DP>;
1146 power-domains = <&pd_disp1>;
1147 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1148 clock-names = "sclk_fimd", "fimd";
1149 iommus = <&sysmmu_fimd1>;
1153 iommus = <&sysmmu_g2d>;
1154 clocks = <&clock CLK_G2D>;
1155 clock-names = "fimg2d";
1160 clocks = <&clock CLK_I2C0>;
1161 clock-names = "i2c";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&i2c0_bus>;
1167 clocks = <&clock CLK_I2C1>;
1168 clock-names = "i2c";
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&i2c1_bus>;
1174 clocks = <&clock CLK_I2C2>;
1175 clock-names = "i2c";
1176 pinctrl-names = "default";
1177 pinctrl-0 = <&i2c2_bus>;
1181 clocks = <&clock CLK_I2C3>;
1182 clock-names = "i2c";
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&i2c3_bus>;
1188 clocks = <&clock CLK_SSS>;
1189 clock-names = "secss";
1193 clocks = <&clock CLK_PWM>;
1194 clock-names = "timers";
1198 clocks = <&clock CLK_RTC>;
1199 clock-names = "rtc";
1200 interrupt-parent = <&pmu_system_controller>;
1201 status = "disabled";
1205 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1206 clock-names = "uart", "clk_uart_baud0";
1207 dmas = <&pdma0 13>, <&pdma0 14>;
1208 dma-names = "rx", "tx";
1212 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1213 clock-names = "uart", "clk_uart_baud0";
1214 dmas = <&pdma1 15>, <&pdma1 16>;
1215 dma-names = "rx", "tx";
1219 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1220 clock-names = "uart", "clk_uart_baud0";
1221 dmas = <&pdma0 15>, <&pdma0 16>;
1222 dma-names = "rx", "tx";
1226 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1227 clock-names = "uart", "clk_uart_baud0";
1228 dmas = <&pdma1 17>, <&pdma1 18>;
1229 dma-names = "rx", "tx";
1233 clocks = <&clock CLK_SSS>;
1234 clock-names = "secss";
1238 clocks = <&clock CLK_SSS>;
1239 clock-names = "secss";
1242 #include "exynos5250-pinctrl.dtsi"
1243 #include "exynos-syscon-restart.dtsi"