arch/arm/boot/dts/exynos4412.dtsi

   1 /*
   2  * Samsung's Exynos4412 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4x12.dtsi"
  21
  22 / {
  23         compatible = "samsung,exynos4412", "samsung,exynos4";
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@A00 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         reg = <0xA00>;
  33                         clocks = <&clock CLK_ARM_CLK>;
  34                         clock-names = "cpu";
  35                         operating-points-v2 = <&cpu0_opp_table>;
  36                         #cooling-cells = <2>; /* min followed by max */
  37                 };
  38
  39                 cpu@A01 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <0xA01>;
  43                         operating-points-v2 = <&cpu0_opp_table>;
  44                 };
  45
  46                 cpu@A02 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <0xA02>;
  50                         operating-points-v2 = <&cpu0_opp_table>;
  51                 };
  52
  53                 cpu@A03 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a9";
  56                         reg = <0xA03>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                 };
  59         };
  60
  61         cpu0_opp_table: opp_table0 {
  62                 compatible = "operating-points-v2";
  63                 opp-shared;
  64
  65                 opp@200000000 {
  66                         opp-hz = /bits/ 64 <200000000>;
  67                         opp-microvolt = <900000>;
  68                         clock-latency-ns = <200000>;
  69                 };
  70                 opp@300000000 {
  71                         opp-hz = /bits/ 64 <300000000>;
  72                         opp-microvolt = <900000>;
  73                         clock-latency-ns = <200000>;
  74                 };
  75                 opp@400000000 {
  76                         opp-hz = /bits/ 64 <400000000>;
  77                         opp-microvolt = <925000>;
  78                         clock-latency-ns = <200000>;
  79                 };
  80                 opp@500000000 {
  81                         opp-hz = /bits/ 64 <500000000>;
  82                         opp-microvolt = <950000>;
  83                         clock-latency-ns = <200000>;
  84                 };
  85                 opp@600000000 {
  86                         opp-hz = /bits/ 64 <600000000>;
  87                         opp-microvolt = <975000>;
  88                         clock-latency-ns = <200000>;
  89                 };
  90                 opp@700000000 {
  91                         opp-hz = /bits/ 64 <700000000>;
  92                         opp-microvolt = <987500>;
  93                         clock-latency-ns = <200000>;
  94                 };
  95                 opp@800000000 {
  96                         opp-hz = /bits/ 64 <800000000>;
  97                         opp-microvolt = <1000000>;
  98                         clock-latency-ns = <200000>;
  99                         opp-suspend;
 100                 };
 101                 opp@900000000 {
 102                         opp-hz = /bits/ 64 <900000000>;
 103                         opp-microvolt = <1037500>;
 104                         clock-latency-ns = <200000>;
 105                 };
 106                 opp@1000000000 {
 107                         opp-hz = /bits/ 64 <1000000000>;
 108                         opp-microvolt = <1087500>;
 109                         clock-latency-ns = <200000>;
 110                 };
 111                 opp@1100000000 {
 112                         opp-hz = /bits/ 64 <1100000000>;
 113                         opp-microvolt = <1137500>;
 114                         clock-latency-ns = <200000>;
 115                 };
 116                 opp@1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1187500>;
 119                         clock-latency-ns = <200000>;
 120                 };
 121                 opp@1300000000 {
 122                         opp-hz = /bits/ 64 <1300000000>;
 123                         opp-microvolt = <1250000>;
 124                         clock-latency-ns = <200000>;
 125                 };
 126                 opp@1400000000 {
 127                         opp-hz = /bits/ 64 <1400000000>;
 128                         opp-microvolt = <1287500>;
 129                         clock-latency-ns = <200000>;
 130                 };
 131                 cpu0_opp_1500: opp@1500000000 {
 132                         opp-hz = /bits/ 64 <1500000000>;
 133                         opp-microvolt = <1350000>;
 134                         clock-latency-ns = <200000>;
 135                         turbo-mode;
 136                 };
 137         };
 138
 139         pmu {
 140                 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
 141         };
 142 };
 143
 144 &pmu_system_controller {
 145         compatible = "samsung,exynos4412-pmu", "syscon";
 146 };
 147
 148 &combiner {
 149         samsung,combiner-nr = <20>;
 150 };
 151
 152 &gic {
 153         cpu-offset = <0x4000>;
 154 };