2 * Samsung's Exynos4412 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4.dtsi"
21 #include "exynos4412-pinctrl.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
25 compatible = "samsung,exynos4412", "samsung,exynos4";
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 fimc-lite0 = &fimc_lite_0;
33 fimc-lite1 = &fimc_lite_1;
43 compatible = "arm,cortex-a9";
45 clocks = <&clock CLK_ARM_CLK>;
47 operating-points-v2 = <&cpu0_opp_table>;
48 #cooling-cells = <2>; /* min followed by max */
53 compatible = "arm,cortex-a9";
55 operating-points-v2 = <&cpu0_opp_table>;
60 compatible = "arm,cortex-a9";
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a9";
69 operating-points-v2 = <&cpu0_opp_table>;
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <900000>;
80 clock-latency-ns = <200000>;
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <900000>;
85 clock-latency-ns = <200000>;
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <925000>;
90 clock-latency-ns = <200000>;
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <950000>;
95 clock-latency-ns = <200000>;
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <975000>;
100 clock-latency-ns = <200000>;
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <987500>;
105 clock-latency-ns = <200000>;
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1000000>;
110 clock-latency-ns = <200000>;
114 opp-hz = /bits/ 64 <900000000>;
115 opp-microvolt = <1037500>;
116 clock-latency-ns = <200000>;
119 opp-hz = /bits/ 64 <1000000000>;
120 opp-microvolt = <1087500>;
121 clock-latency-ns = <200000>;
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1137500>;
126 clock-latency-ns = <200000>;
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1187500>;
131 clock-latency-ns = <200000>;
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1250000>;
136 clock-latency-ns = <200000>;
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1287500>;
141 clock-latency-ns = <200000>;
143 cpu0_opp_1500: opp-1500000000 {
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1350000>;
146 clock-latency-ns = <200000>;
152 compatible = "mmio-sram";
153 reg = <0x02020000 0x40000>;
154 #address-cells = <1>;
156 ranges = <0 0x02020000 0x40000>;
159 compatible = "samsung,exynos4210-sysram";
164 compatible = "samsung,exynos4210-sysram-ns";
165 reg = <0x2f000 0x1000>;
169 pd_isp: isp-power-domain@10023CA0 {
170 compatible = "samsung,exynos4210-pd";
171 reg = <0x10023CA0 0x20>;
172 #power-domain-cells = <0>;
176 l2c: l2-cache-controller@10502000 {
177 compatible = "arm,pl310-cache";
178 reg = <0x10502000 0x1000>;
181 arm,tag-latency = <2 2 1>;
182 arm,data-latency = <3 2 1>;
183 arm,double-linefill = <1>;
184 arm,double-linefill-incr = <0>;
185 arm,double-linefill-wrap = <1>;
186 arm,prefetch-drop = <1>;
187 arm,prefetch-offset = <7>;
190 clock: clock-controller@10030000 {
191 compatible = "samsung,exynos4412-clock";
192 reg = <0x10030000 0x20000>;
197 compatible = "samsung,exynos4412-mct";
198 reg = <0x10050000 0x800>;
199 interrupt-parent = <&mct_map>;
200 interrupts = <0>, <1>, <2>, <3>, <4>;
201 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
202 clock-names = "fin_pll", "mct";
205 #interrupt-cells = <1>;
206 #address-cells = <0>;
208 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
212 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
216 watchdog: watchdog@10060000 {
217 compatible = "samsung,exynos5250-wdt";
218 reg = <0x10060000 0x100>;
219 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clock CLK_WDT>;
221 clock-names = "watchdog";
222 samsung,syscon-phandle = <&pmu_system_controller>;
226 compatible = "samsung,exynos-adc-v1";
227 reg = <0x126C0000 0x100>;
228 interrupt-parent = <&combiner>;
230 clocks = <&clock CLK_TSADC>;
232 #io-channel-cells = <1>;
234 samsung,syscon-phandle = <&pmu_system_controller>;
239 compatible = "samsung,exynos4212-g2d";
240 reg = <0x10800000 0x1000>;
241 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
243 clock-names = "sclk_fimg2d", "fimg2d";
244 iommus = <&sysmmu_g2d>;
248 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
249 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
250 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
252 /* fimc_[0-3] are configured outside, under phandles */
253 fimc_lite_0: fimc-lite@12390000 {
254 compatible = "samsung,exynos4212-fimc-lite";
255 reg = <0x12390000 0x1000>;
256 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
257 power-domains = <&pd_isp>;
258 clocks = <&clock CLK_FIMC_LITE0>;
259 clock-names = "flite";
260 iommus = <&sysmmu_fimc_lite0>;
264 fimc_lite_1: fimc-lite@123A0000 {
265 compatible = "samsung,exynos4212-fimc-lite";
266 reg = <0x123A0000 0x1000>;
267 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
268 power-domains = <&pd_isp>;
269 clocks = <&clock CLK_FIMC_LITE1>;
270 clock-names = "flite";
271 iommus = <&sysmmu_fimc_lite1>;
275 fimc_is: fimc-is@12000000 {
276 compatible = "samsung,exynos4212-fimc-is";
277 reg = <0x12000000 0x260000>;
278 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
280 power-domains = <&pd_isp>;
281 clocks = <&clock CLK_FIMC_LITE0>,
282 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
283 <&clock CLK_PPMUISPMX>,
284 <&clock CLK_MOUT_MPLL_USER_T>,
285 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
286 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
287 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
288 <&clock CLK_PWM_ISP>,
289 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
290 <&clock CLK_DIV_MCUISP0>,
291 <&clock CLK_DIV_MCUISP1>,
292 <&clock CLK_UART_ISP_SCLK>,
293 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
294 <&clock CLK_ACLK400_MCUISP>,
295 <&clock CLK_DIV_ACLK400_MCUISP>;
296 clock-names = "lite0", "lite1", "ppmuispx",
297 "ppmuispmx", "mpll", "isp",
298 "drc", "fd", "mcuisp",
299 "gicisp", "mcuctl_isp", "pwm_isp",
300 "ispdiv0", "ispdiv1", "mcuispdiv0",
301 "mcuispdiv1", "uart", "aclk200",
302 "div_aclk200", "aclk400mcuisp",
304 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
305 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
306 iommu-names = "isp", "drc", "fd", "mcuctl";
307 #address-cells = <1>;
313 reg = <0x10020000 0x3000>;
316 i2c1_isp: i2c-isp@12140000 {
317 compatible = "samsung,exynos4212-i2c-isp";
318 reg = <0x12140000 0x100>;
319 clocks = <&clock CLK_I2C1_ISP>;
320 clock-names = "i2c_isp";
321 #address-cells = <1>;
327 mshc_0: mmc@12550000 {
328 compatible = "samsung,exynos4412-dw-mshc";
329 reg = <0x12550000 0x1000>;
330 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
334 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
335 clock-names = "biu", "ciu";
339 sysmmu_g2d: sysmmu@10A40000{
340 compatible = "samsung,exynos-sysmmu";
341 reg = <0x10A40000 0x1000>;
342 interrupt-parent = <&combiner>;
344 clock-names = "sysmmu", "master";
345 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
349 sysmmu_fimc_isp: sysmmu@12260000 {
350 compatible = "samsung,exynos-sysmmu";
351 reg = <0x12260000 0x1000>;
352 interrupt-parent = <&combiner>;
354 power-domains = <&pd_isp>;
355 clock-names = "sysmmu";
356 clocks = <&clock CLK_SMMU_ISP>;
360 sysmmu_fimc_drc: sysmmu@12270000 {
361 compatible = "samsung,exynos-sysmmu";
362 reg = <0x12270000 0x1000>;
363 interrupt-parent = <&combiner>;
365 power-domains = <&pd_isp>;
366 clock-names = "sysmmu";
367 clocks = <&clock CLK_SMMU_DRC>;
371 sysmmu_fimc_fd: sysmmu@122A0000 {
372 compatible = "samsung,exynos-sysmmu";
373 reg = <0x122A0000 0x1000>;
374 interrupt-parent = <&combiner>;
376 power-domains = <&pd_isp>;
377 clock-names = "sysmmu";
378 clocks = <&clock CLK_SMMU_FD>;
382 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
383 compatible = "samsung,exynos-sysmmu";
384 reg = <0x122B0000 0x1000>;
385 interrupt-parent = <&combiner>;
387 power-domains = <&pd_isp>;
388 clock-names = "sysmmu";
389 clocks = <&clock CLK_SMMU_ISPCX>;
393 sysmmu_fimc_lite0: sysmmu@123B0000 {
394 compatible = "samsung,exynos-sysmmu";
395 reg = <0x123B0000 0x1000>;
396 interrupt-parent = <&combiner>;
398 power-domains = <&pd_isp>;
399 clock-names = "sysmmu", "master";
400 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
404 sysmmu_fimc_lite1: sysmmu@123C0000 {
405 compatible = "samsung,exynos-sysmmu";
406 reg = <0x123C0000 0x1000>;
407 interrupt-parent = <&combiner>;
409 power-domains = <&pd_isp>;
410 clock-names = "sysmmu", "master";
411 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
416 compatible = "samsung,exynos-bus";
417 clocks = <&clock CLK_DIV_DMC>;
419 operating-points-v2 = <&bus_dmc_opp_table>;
424 compatible = "samsung,exynos-bus";
425 clocks = <&clock CLK_DIV_ACP>;
427 operating-points-v2 = <&bus_acp_opp_table>;
432 compatible = "samsung,exynos-bus";
433 clocks = <&clock CLK_DIV_C2C>;
435 operating-points-v2 = <&bus_dmc_opp_table>;
439 bus_dmc_opp_table: opp_table1 {
440 compatible = "operating-points-v2";
444 opp-hz = /bits/ 64 <100000000>;
445 opp-microvolt = <900000>;
448 opp-hz = /bits/ 64 <134000000>;
449 opp-microvolt = <900000>;
452 opp-hz = /bits/ 64 <160000000>;
453 opp-microvolt = <900000>;
456 opp-hz = /bits/ 64 <267000000>;
457 opp-microvolt = <950000>;
460 opp-hz = /bits/ 64 <400000000>;
461 opp-microvolt = <1050000>;
465 bus_acp_opp_table: opp_table2 {
466 compatible = "operating-points-v2";
470 opp-hz = /bits/ 64 <100000000>;
473 opp-hz = /bits/ 64 <134000000>;
476 opp-hz = /bits/ 64 <160000000>;
479 opp-hz = /bits/ 64 <267000000>;
483 bus_leftbus: bus_leftbus {
484 compatible = "samsung,exynos-bus";
485 clocks = <&clock CLK_DIV_GDL>;
487 operating-points-v2 = <&bus_leftbus_opp_table>;
491 bus_rightbus: bus_rightbus {
492 compatible = "samsung,exynos-bus";
493 clocks = <&clock CLK_DIV_GDR>;
495 operating-points-v2 = <&bus_leftbus_opp_table>;
499 bus_display: bus_display {
500 compatible = "samsung,exynos-bus";
501 clocks = <&clock CLK_ACLK160>;
503 operating-points-v2 = <&bus_display_opp_table>;
508 compatible = "samsung,exynos-bus";
509 clocks = <&clock CLK_ACLK133>;
511 operating-points-v2 = <&bus_fsys_opp_table>;
516 compatible = "samsung,exynos-bus";
517 clocks = <&clock CLK_ACLK100>;
519 operating-points-v2 = <&bus_peri_opp_table>;
524 compatible = "samsung,exynos-bus";
525 clocks = <&clock CLK_SCLK_MFC>;
527 operating-points-v2 = <&bus_leftbus_opp_table>;
531 bus_leftbus_opp_table: opp_table3 {
532 compatible = "operating-points-v2";
536 opp-hz = /bits/ 64 <100000000>;
537 opp-microvolt = <900000>;
540 opp-hz = /bits/ 64 <134000000>;
541 opp-microvolt = <925000>;
544 opp-hz = /bits/ 64 <160000000>;
545 opp-microvolt = <950000>;
548 opp-hz = /bits/ 64 <200000000>;
549 opp-microvolt = <1000000>;
553 bus_display_opp_table: opp_table4 {
554 compatible = "operating-points-v2";
558 opp-hz = /bits/ 64 <160000000>;
561 opp-hz = /bits/ 64 <200000000>;
565 bus_fsys_opp_table: opp_table5 {
566 compatible = "operating-points-v2";
570 opp-hz = /bits/ 64 <100000000>;
573 opp-hz = /bits/ 64 <134000000>;
577 bus_peri_opp_table: opp_table6 {
578 compatible = "operating-points-v2";
582 opp-hz = /bits/ 64 <50000000>;
585 opp-hz = /bits/ 64 <100000000>;
590 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
595 samsung,combiner-nr = <20>;
596 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
619 compatible = "samsung,exynos4x12-usb2-phy";
620 samsung,sysreg-phandle = <&sys_reg>;
624 compatible = "samsung,exynos4212-fimc";
625 samsung,pix-limits = <4224 8192 1920 4224>;
626 samsung,mainscaler-ext;
632 compatible = "samsung,exynos4212-fimc";
633 samsung,pix-limits = <4224 8192 1920 4224>;
634 samsung,mainscaler-ext;
640 compatible = "samsung,exynos4212-fimc";
641 samsung,pix-limits = <4224 8192 1920 4224>;
642 samsung,mainscaler-ext;
649 compatible = "samsung,exynos4212-fimc";
650 samsung,pix-limits = <1920 8192 1366 1920>;
651 samsung,rotators = <0>;
652 samsung,mainscaler-ext;
658 cpu-offset = <0x4000>;
662 compatible = "samsung,exynos4212-hdmi";
666 compatible = "samsung,exynos4212-jpeg";
670 compatible = "samsung,exynos4212-rotator";
674 compatible = "samsung,exynos4212-mixer";
675 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
676 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
677 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
681 compatible = "samsung,exynos4x12-pinctrl";
682 reg = <0x11400000 0x1000>;
683 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
687 compatible = "samsung,exynos4x12-pinctrl";
688 reg = <0x11000000 0x1000>;
689 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
691 wakup_eint: wakeup-interrupt-controller {
692 compatible = "samsung,exynos4210-wakeup-eint";
693 interrupt-parent = <&gic>;
694 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
699 compatible = "samsung,exynos4x12-pinctrl";
700 reg = <0x03860000 0x1000>;
701 interrupt-parent = <&combiner>;
706 compatible = "samsung,exynos4x12-pinctrl";
707 reg = <0x106E0000 0x1000>;
708 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
711 &pmu_system_controller {
712 compatible = "samsung,exynos4412-pmu", "syscon";
713 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
714 "clkout4", "clkout8", "clkout9";
715 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
716 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
717 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
722 compatible = "samsung,exynos4412-tmu";
723 interrupt-parent = <&combiner>;
725 reg = <0x100C0000 0x100>;
726 clocks = <&clock 383>;
727 clock-names = "tmu_apbif";