1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC device tree source
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
19 #include "exynos4.dtsi"
20 #include "exynos4-cpu-thermal.dtsi"
23 compatible = "samsung,exynos4210", "samsung,exynos4";
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
37 compatible = "arm,cortex-a9";
39 clocks = <&clock CLK_ARM_CLK>;
41 clock-latency = <160000>;
51 #cooling-cells = <2>; /* min followed by max */
56 compatible = "arm,cortex-a9";
58 clocks = <&clock CLK_ARM_CLK>;
60 clock-latency = <160000>;
70 #cooling-cells = <2>; /* min followed by max */
75 sysram: sysram@2020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x20000>;
80 ranges = <0 0x02020000 0x20000>;
83 compatible = "samsung,exynos4210-sysram";
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x1f000 0x1000>;
93 pd_lcd1: lcd1-power-domain@10023ca0 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10023CA0 0x20>;
96 #power-domain-cells = <0>;
100 l2c: l2-cache-controller@10502000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x10502000 0x1000>;
105 arm,tag-latency = <2 2 1>;
106 arm,data-latency = <2 2 1>;
110 compatible = "samsung,exynos4210-mct";
111 reg = <0x10050000 0x800>;
112 interrupt-parent = <&mct_map>;
113 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
114 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
115 clock-names = "fin_pll", "mct";
118 #interrupt-cells = <1>;
119 #address-cells = <0>;
122 <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
123 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
126 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
127 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
131 watchdog: watchdog@10060000 {
132 compatible = "samsung,s3c6410-wdt";
133 reg = <0x10060000 0x100>;
134 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&clock CLK_WDT>;
136 clock-names = "watchdog";
139 clock: clock-controller@10030000 {
140 compatible = "samsung,exynos4210-clock";
141 reg = <0x10030000 0x20000>;
145 pinctrl_0: pinctrl@11400000 {
146 compatible = "samsung,exynos4210-pinctrl";
147 reg = <0x11400000 0x1000>;
148 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
151 pinctrl_1: pinctrl@11000000 {
152 compatible = "samsung,exynos4210-pinctrl";
153 reg = <0x11000000 0x1000>;
154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
156 wakup_eint: wakeup-interrupt-controller {
157 compatible = "samsung,exynos4210-wakeup-eint";
158 interrupt-parent = <&gic>;
159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
163 pinctrl_2: pinctrl@3860000 {
164 compatible = "samsung,exynos4210-pinctrl";
165 reg = <0x03860000 0x1000>;
169 compatible = "samsung,s5pv210-g2d";
170 reg = <0x12800000 0x1000>;
171 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
173 clock-names = "sclk_fimg2d", "fimg2d";
174 power-domains = <&pd_lcd0>;
175 iommus = <&sysmmu_g2d>;
178 ppmu_acp: ppmu_acp@10ae0000 {
179 compatible = "samsung,exynos-ppmu";
180 reg = <0x10ae0000 0x2000>;
184 ppmu_lcd1: ppmu_lcd1@12240000 {
185 compatible = "samsung,exynos-ppmu";
186 reg = <0x12240000 0x2000>;
187 clocks = <&clock CLK_PPMULCD1>;
188 clock-names = "ppmu";
192 sysmmu_g2d: sysmmu@12a20000 {
193 compatible = "samsung,exynos-sysmmu";
194 reg = <0x12A20000 0x1000>;
195 interrupt-parent = <&combiner>;
197 clock-names = "sysmmu", "master";
198 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
199 power-domains = <&pd_lcd0>;
203 sysmmu_fimd1: sysmmu@12220000 {
204 compatible = "samsung,exynos-sysmmu";
205 interrupt-parent = <&combiner>;
206 reg = <0x12220000 0x1000>;
208 clock-names = "sysmmu", "master";
209 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
210 power-domains = <&pd_lcd1>;
215 compatible = "samsung,exynos-bus";
216 clocks = <&clock CLK_DIV_DMC>;
218 operating-points-v2 = <&bus_dmc_opp_table>;
223 compatible = "samsung,exynos-bus";
224 clocks = <&clock CLK_DIV_ACP>;
226 operating-points-v2 = <&bus_acp_opp_table>;
231 compatible = "samsung,exynos-bus";
232 clocks = <&clock CLK_ACLK100>;
234 operating-points-v2 = <&bus_peri_opp_table>;
239 compatible = "samsung,exynos-bus";
240 clocks = <&clock CLK_ACLK133>;
242 operating-points-v2 = <&bus_fsys_opp_table>;
246 bus_display: bus_display {
247 compatible = "samsung,exynos-bus";
248 clocks = <&clock CLK_ACLK160>;
250 operating-points-v2 = <&bus_display_opp_table>;
255 compatible = "samsung,exynos-bus";
256 clocks = <&clock CLK_ACLK200>;
258 operating-points-v2 = <&bus_leftbus_opp_table>;
262 bus_leftbus: bus_leftbus {
263 compatible = "samsung,exynos-bus";
264 clocks = <&clock CLK_DIV_GDL>;
266 operating-points-v2 = <&bus_leftbus_opp_table>;
270 bus_rightbus: bus_rightbus {
271 compatible = "samsung,exynos-bus";
272 clocks = <&clock CLK_DIV_GDR>;
274 operating-points-v2 = <&bus_leftbus_opp_table>;
279 compatible = "samsung,exynos-bus";
280 clocks = <&clock CLK_SCLK_MFC>;
282 operating-points-v2 = <&bus_leftbus_opp_table>;
286 bus_dmc_opp_table: opp_table1 {
287 compatible = "operating-points-v2";
291 opp-hz = /bits/ 64 <134000000>;
292 opp-microvolt = <1025000>;
295 opp-hz = /bits/ 64 <267000000>;
296 opp-microvolt = <1050000>;
299 opp-hz = /bits/ 64 <400000000>;
300 opp-microvolt = <1150000>;
305 bus_acp_opp_table: opp_table2 {
306 compatible = "operating-points-v2";
310 opp-hz = /bits/ 64 <134000000>;
313 opp-hz = /bits/ 64 <160000000>;
316 opp-hz = /bits/ 64 <200000000>;
320 bus_peri_opp_table: opp_table3 {
321 compatible = "operating-points-v2";
325 opp-hz = /bits/ 64 <5000000>;
328 opp-hz = /bits/ 64 <100000000>;
332 bus_fsys_opp_table: opp_table4 {
333 compatible = "operating-points-v2";
337 opp-hz = /bits/ 64 <10000000>;
340 opp-hz = /bits/ 64 <134000000>;
344 bus_display_opp_table: opp_table5 {
345 compatible = "operating-points-v2";
349 opp-hz = /bits/ 64 <100000000>;
352 opp-hz = /bits/ 64 <134000000>;
355 opp-hz = /bits/ 64 <160000000>;
359 bus_leftbus_opp_table: opp_table6 {
360 compatible = "operating-points-v2";
364 opp-hz = /bits/ 64 <100000000>;
367 opp-hz = /bits/ 64 <160000000>;
370 opp-hz = /bits/ 64 <200000000>;
377 cpu_thermal: cpu-thermal {
378 polling-delay-passive = <0>;
380 thermal-sensors = <&tmu 0>;
383 cpu_alert0: cpu-alert-0 {
384 temperature = <85000>; /* millicelsius */
386 cpu_alert1: cpu-alert-1 {
387 temperature = <100000>; /* millicelsius */
389 cpu_alert2: cpu-alert-2 {
390 temperature = <110000>; /* millicelsius */
398 cpu-offset = <0x8000>;
402 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
403 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
404 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
408 samsung,combiner-nr = <16>;
409 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
428 samsung,pix-limits = <4224 8192 1920 4224>;
429 samsung,mainscaler-ext;
434 samsung,pix-limits = <4224 8192 1920 4224>;
435 samsung,mainscaler-ext;
440 samsung,pix-limits = <4224 8192 1920 4224>;
441 samsung,mainscaler-ext;
446 samsung,pix-limits = <1920 8192 1366 1920>;
447 samsung,rotators = <0>;
448 samsung,mainscaler-ext;
453 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "gp",
473 operating-points-v2 = <&gpu_opp_table>;
475 gpu_opp_table: opp_table {
476 compatible = "operating-points-v2";
479 opp-hz = /bits/ 64 <160000000>;
480 opp-microvolt = <950000>;
483 opp-hz = /bits/ 64 <267000000>;
484 opp-microvolt = <1050000>;
490 power-domains = <&pd_lcd0>;
494 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
496 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
497 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
498 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
502 interrupts = <2 2>, <3 2>;
503 interrupt-affinity = <&cpu0>, <&cpu1>;
507 &pmu_system_controller {
508 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
509 "clkout4", "clkout8", "clkout9";
510 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
511 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
512 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
517 power-domains = <&pd_lcd0>;
521 power-domains = <&pd_lcd0>;
525 compatible = "samsung,exynos4210-tmu";
526 clocks = <&clock CLK_TMU_APBIF>;
527 clock-names = "tmu_apbif";
528 samsung,tmu_gain = <15>;
529 samsung,tmu_reference_voltage = <7>;
532 #include "exynos4210-pinctrl.dtsi"