2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #include "exynos4.dtsi"
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4-cpu-thermal.dtsi"
27 compatible = "samsung,exynos4210", "samsung,exynos4";
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
41 compatible = "arm,cortex-a9";
43 clocks = <&clock CLK_ARM_CLK>;
45 clock-latency = <160000>;
55 #cooling-cells = <2>; /* min followed by max */
60 compatible = "arm,cortex-a9";
62 clocks = <&clock CLK_ARM_CLK>;
64 clock-latency = <160000>;
74 #cooling-cells = <2>; /* min followed by max */
78 sysram: sysram@02020000 {
79 compatible = "mmio-sram";
80 reg = <0x02020000 0x20000>;
83 ranges = <0 0x02020000 0x20000>;
86 compatible = "samsung,exynos4210-sysram";
91 compatible = "samsung,exynos4210-sysram-ns";
92 reg = <0x1f000 0x1000>;
96 pd_lcd1: lcd1-power-domain@10023CA0 {
97 compatible = "samsung,exynos4210-pd";
98 reg = <0x10023CA0 0x20>;
99 #power-domain-cells = <0>;
102 l2c: l2-cache-controller@10502000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x10502000 0x1000>;
107 arm,tag-latency = <2 2 1>;
108 arm,data-latency = <2 2 1>;
112 compatible = "samsung,exynos4210-mct";
113 reg = <0x10050000 0x800>;
114 interrupt-parent = <&mct_map>;
115 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
116 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
117 clock-names = "fin_pll", "mct";
120 #interrupt-cells = <1>;
121 #address-cells = <0>;
123 interrupt-map = <0 &gic 0 57 0>,
132 clock: clock-controller@10030000 {
133 compatible = "samsung,exynos4210-clock";
134 reg = <0x10030000 0x20000>;
138 pinctrl_0: pinctrl@11400000 {
139 compatible = "samsung,exynos4210-pinctrl";
140 reg = <0x11400000 0x1000>;
141 interrupts = <0 47 0>;
144 pinctrl_1: pinctrl@11000000 {
145 compatible = "samsung,exynos4210-pinctrl";
146 reg = <0x11000000 0x1000>;
147 interrupts = <0 46 0>;
149 wakup_eint: wakeup-interrupt-controller {
150 compatible = "samsung,exynos4210-wakeup-eint";
151 interrupt-parent = <&gic>;
152 interrupts = <0 32 0>;
156 pinctrl_2: pinctrl@03860000 {
157 compatible = "samsung,exynos4210-pinctrl";
158 reg = <0x03860000 0x1000>;
162 compatible = "samsung,exynos4210-tmu";
163 interrupt-parent = <&combiner>;
164 reg = <0x100C0000 0x100>;
166 clocks = <&clock CLK_TMU_APBIF>;
167 clock-names = "tmu_apbif";
168 samsung,tmu_gain = <15>;
169 samsung,tmu_reference_voltage = <7>;
174 cpu_thermal: cpu-thermal {
175 polling-delay-passive = <0>;
177 thermal-sensors = <&tmu 0>;
180 cpu_alert0: cpu-alert-0 {
181 temperature = <85000>; /* millicelsius */
183 cpu_alert1: cpu-alert-1 {
184 temperature = <100000>; /* millicelsius */
186 cpu_alert2: cpu-alert-2 {
187 temperature = <110000>; /* millicelsius */
194 compatible = "samsung,s5pv210-g2d";
195 reg = <0x12800000 0x1000>;
196 interrupts = <0 89 0>;
197 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
198 clock-names = "sclk_fimg2d", "fimg2d";
199 power-domains = <&pd_lcd0>;
200 iommus = <&sysmmu_g2d>;
204 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
205 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
206 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
208 fimc_0: fimc@11800000 {
209 samsung,pix-limits = <4224 8192 1920 4224>;
210 samsung,mainscaler-ext;
214 fimc_1: fimc@11810000 {
215 samsung,pix-limits = <4224 8192 1920 4224>;
216 samsung,mainscaler-ext;
220 fimc_2: fimc@11820000 {
221 samsung,pix-limits = <4224 8192 1920 4224>;
222 samsung,mainscaler-ext;
226 fimc_3: fimc@11830000 {
227 samsung,pix-limits = <1920 8192 1366 1920>;
228 samsung,rotators = <0>;
229 samsung,mainscaler-ext;
234 mixer: mixer@12C10000 {
235 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
237 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
238 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
239 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
242 ppmu_lcd1: ppmu_lcd1@12240000 {
243 compatible = "samsung,exynos-ppmu";
244 reg = <0x12240000 0x2000>;
245 clocks = <&clock CLK_PPMULCD1>;
246 clock-names = "ppmu";
250 sysmmu_g2d: sysmmu@12A20000 {
251 compatible = "samsung,exynos-sysmmu";
252 reg = <0x12A20000 0x1000>;
253 interrupt-parent = <&combiner>;
255 clock-names = "sysmmu", "master";
256 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
257 power-domains = <&pd_lcd0>;
261 sysmmu_fimd1: sysmmu@12220000 {
262 compatible = "samsung,exynos-sysmmu";
263 interrupt-parent = <&combiner>;
264 reg = <0x12220000 0x1000>;
266 clock-names = "sysmmu", "master";
267 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
268 power-domains = <&pd_lcd1>;
273 compatible = "samsung,exynos-bus";
274 clocks = <&clock CLK_DIV_DMC>;
276 operating-points-v2 = <&bus_dmc_opp_table>;
281 compatible = "samsung,exynos-bus";
282 clocks = <&clock CLK_DIV_ACP>;
284 operating-points-v2 = <&bus_acp_opp_table>;
289 compatible = "samsung,exynos-bus";
290 clocks = <&clock CLK_ACLK100>;
292 operating-points-v2 = <&bus_peri_opp_table>;
297 compatible = "samsung,exynos-bus";
298 clocks = <&clock CLK_ACLK133>;
300 operating-points-v2 = <&bus_fsys_opp_table>;
304 bus_display: bus_display {
305 compatible = "samsung,exynos-bus";
306 clocks = <&clock CLK_ACLK160>;
308 operating-points-v2 = <&bus_display_opp_table>;
313 compatible = "samsung,exynos-bus";
314 clocks = <&clock CLK_ACLK200>;
316 operating-points-v2 = <&bus_leftbus_opp_table>;
320 bus_leftbus: bus_leftbus {
321 compatible = "samsung,exynos-bus";
322 clocks = <&clock CLK_DIV_GDL>;
324 operating-points-v2 = <&bus_leftbus_opp_table>;
328 bus_rightbus: bus_rightbus {
329 compatible = "samsung,exynos-bus";
330 clocks = <&clock CLK_DIV_GDR>;
332 operating-points-v2 = <&bus_leftbus_opp_table>;
337 compatible = "samsung,exynos-bus";
338 clocks = <&clock CLK_SCLK_MFC>;
340 operating-points-v2 = <&bus_leftbus_opp_table>;
344 bus_dmc_opp_table: opp_table1 {
345 compatible = "operating-points-v2";
349 opp-hz = /bits/ 64 <134000000>;
350 opp-microvolt = <1025000>;
353 opp-hz = /bits/ 64 <267000000>;
354 opp-microvolt = <1050000>;
357 opp-hz = /bits/ 64 <400000000>;
358 opp-microvolt = <1150000>;
362 bus_acp_opp_table: opp_table2 {
363 compatible = "operating-points-v2";
367 opp-hz = /bits/ 64 <134000000>;
370 opp-hz = /bits/ 64 <160000000>;
373 opp-hz = /bits/ 64 <200000000>;
377 bus_peri_opp_table: opp_table3 {
378 compatible = "operating-points-v2";
382 opp-hz = /bits/ 64 <5000000>;
385 opp-hz = /bits/ 64 <100000000>;
389 bus_fsys_opp_table: opp_table4 {
390 compatible = "operating-points-v2";
394 opp-hz = /bits/ 64 <10000000>;
397 opp-hz = /bits/ 64 <134000000>;
401 bus_display_opp_table: opp_table5 {
402 compatible = "operating-points-v2";
406 opp-hz = /bits/ 64 <100000000>;
409 opp-hz = /bits/ 64 <134000000>;
412 opp-hz = /bits/ 64 <160000000>;
416 bus_leftbus_opp_table: opp_table6 {
417 compatible = "operating-points-v2";
421 opp-hz = /bits/ 64 <100000000>;
424 opp-hz = /bits/ 64 <160000000>;
427 opp-hz = /bits/ 64 <200000000>;
433 cpu-offset = <0x8000>;
437 samsung,combiner-nr = <16>;
438 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
439 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
440 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
441 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
445 power-domains = <&pd_lcd0>;
448 &pmu_system_controller {
449 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
450 "clkout4", "clkout8", "clkout9";
451 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
452 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
453 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
458 power-domains = <&pd_lcd0>;
462 power-domains = <&pd_lcd0>;