arch/arm/boot/dts/exynos4210.dtsi

   1 /*
   2  * Samsung's Exynos4210 SoC device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  10  * based board files can include this file and provide values for board specfic
  11  * bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20 */
  21
  22 #include "exynos4.dtsi"
  23 #include "exynos4210-pinctrl.dtsi"
  24 #include "exynos4-cpu-thermal.dtsi"
  25
  26 / {
  27         compatible = "samsung,exynos4210", "samsung,exynos4";
  28
  29         aliases {
  30                 pinctrl0 = &pinctrl_0;
  31                 pinctrl1 = &pinctrl_1;
  32                 pinctrl2 = &pinctrl_2;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu0: cpu@900 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a9";
  42                         reg = <0x900>;
  43                         clocks = <&clock CLK_ARM_CLK>;
  44                         clock-names = "cpu";
  45                         clock-latency = <160000>;
  46
  47                         operating-points = <
  48                                 1200000 1250000
  49                                 1000000 1150000
  50                                 800000  1075000
  51                                 500000  975000
  52                                 400000  975000
  53                                 200000  950000
  54                         >;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57
  58                 cpu@901 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a9";
  61                         reg = <0x901>;
  62                         clocks = <&clock CLK_ARM_CLK>;
  63                         clock-names = "cpu";
  64                         clock-latency = <160000>;
  65
  66                         operating-points = <
  67                                 1200000 1250000
  68                                 1000000 1150000
  69                                 800000  1075000
  70                                 500000  975000
  71                                 400000  975000
  72                                 200000  950000
  73                         >;
  74                         #cooling-cells = <2>; /* min followed by max */
  75                 };
  76         };
  77
  78         sysram: sysram@02020000 {
  79                 compatible = "mmio-sram";
  80                 reg = <0x02020000 0x20000>;
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges = <0 0x02020000 0x20000>;
  84
  85                 smp-sysram@0 {
  86                         compatible = "samsung,exynos4210-sysram";
  87                         reg = <0x0 0x1000>;
  88                 };
  89
  90                 smp-sysram@1f000 {
  91                         compatible = "samsung,exynos4210-sysram-ns";
  92                         reg = <0x1f000 0x1000>;
  93                 };
  94         };
  95
  96         pd_lcd1: lcd1-power-domain@10023CA0 {
  97                 compatible = "samsung,exynos4210-pd";
  98                 reg = <0x10023CA0 0x20>;
  99                 #power-domain-cells = <0>;
 100         };
 101
 102         l2c: l2-cache-controller@10502000 {
 103                 compatible = "arm,pl310-cache";
 104                 reg = <0x10502000 0x1000>;
 105                 cache-unified;
 106                 cache-level = <2>;
 107                 arm,tag-latency = <2 2 1>;
 108                 arm,data-latency = <2 2 1>;
 109         };
 110
 111         mct: mct@10050000 {
 112                 compatible = "samsung,exynos4210-mct";
 113                 reg = <0x10050000 0x800>;
 114                 interrupt-parent = <&mct_map>;
 115                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
 116                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 117                 clock-names = "fin_pll", "mct";
 118
 119                 mct_map: mct-map {
 120                         #interrupt-cells = <1>;
 121                         #address-cells = <0>;
 122                         #size-cells = <0>;
 123                         interrupt-map = <0 &gic 0 57 0>,
 124                                         <1 &gic 0 69 0>,
 125                                         <2 &combiner 12 6>,
 126                                         <3 &combiner 12 7>,
 127                                         <4 &gic 0 42 0>,
 128                                         <5 &gic 0 48 0>;
 129                 };
 130         };
 131
 132         clock: clock-controller@10030000 {
 133                 compatible = "samsung,exynos4210-clock";
 134                 reg = <0x10030000 0x20000>;
 135                 #clock-cells = <1>;
 136         };
 137
 138         pinctrl_0: pinctrl@11400000 {
 139                 compatible = "samsung,exynos4210-pinctrl";
 140                 reg = <0x11400000 0x1000>;
 141                 interrupts = <0 47 0>;
 142         };
 143
 144         pinctrl_1: pinctrl@11000000 {
 145                 compatible = "samsung,exynos4210-pinctrl";
 146                 reg = <0x11000000 0x1000>;
 147                 interrupts = <0 46 0>;
 148
 149                 wakup_eint: wakeup-interrupt-controller {
 150                         compatible = "samsung,exynos4210-wakeup-eint";
 151                         interrupt-parent = <&gic>;
 152                         interrupts = <0 32 0>;
 153                 };
 154         };
 155
 156         pinctrl_2: pinctrl@03860000 {
 157                 compatible = "samsung,exynos4210-pinctrl";
 158                 reg = <0x03860000 0x1000>;
 159         };
 160
 161         tmu: tmu@100C0000 {
 162                 compatible = "samsung,exynos4210-tmu";
 163                 interrupt-parent = <&combiner>;
 164                 reg = <0x100C0000 0x100>;
 165                 interrupts = <2 4>;
 166                 clocks = <&clock CLK_TMU_APBIF>;
 167                 clock-names = "tmu_apbif";
 168                 samsung,tmu_gain = <15>;
 169                 samsung,tmu_reference_voltage = <7>;
 170                 status = "disabled";
 171         };
 172
 173         thermal-zones {
 174                 cpu_thermal: cpu-thermal {
 175                         polling-delay-passive = <0>;
 176                         polling-delay = <0>;
 177                         thermal-sensors = <&tmu 0>;
 178
 179                         trips {
 180                               cpu_alert0: cpu-alert-0 {
 181                                       temperature = <85000>; /* millicelsius */
 182                               };
 183                               cpu_alert1: cpu-alert-1 {
 184                                       temperature = <100000>; /* millicelsius */
 185                               };
 186                               cpu_alert2: cpu-alert-2 {
 187                                       temperature = <110000>; /* millicelsius */
 188                               };
 189                         };
 190                 };
 191         };
 192
 193         g2d: g2d@12800000 {
 194                 compatible = "samsung,s5pv210-g2d";
 195                 reg = <0x12800000 0x1000>;
 196                 interrupts = <0 89 0>;
 197                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 198                 clock-names = "sclk_fimg2d", "fimg2d";
 199                 power-domains = <&pd_lcd0>;
 200                 iommus = <&sysmmu_g2d>;
 201         };
 202
 203         camera {
 204                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 205                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 206                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 207
 208                 fimc_0: fimc@11800000 {
 209                         samsung,pix-limits = <4224 8192 1920 4224>;
 210                         samsung,mainscaler-ext;
 211                         samsung,cam-if;
 212                 };
 213
 214                 fimc_1: fimc@11810000 {
 215                         samsung,pix-limits = <4224 8192 1920 4224>;
 216                         samsung,mainscaler-ext;
 217                         samsung,cam-if;
 218                 };
 219
 220                 fimc_2: fimc@11820000 {
 221                         samsung,pix-limits = <4224 8192 1920 4224>;
 222                         samsung,mainscaler-ext;
 223                         samsung,lcd-wb;
 224                 };
 225
 226                 fimc_3: fimc@11830000 {
 227                         samsung,pix-limits = <1920 8192 1366 1920>;
 228                         samsung,rotators = <0>;
 229                         samsung,mainscaler-ext;
 230                         samsung,lcd-wb;
 231                 };
 232         };
 233
 234         mixer: mixer@12C10000 {
 235                 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
 236                         "sclk_mixer";
 237                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 238                         <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
 239                         <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
 240         };
 241
 242         ppmu_lcd1: ppmu_lcd1@12240000 {
 243                 compatible = "samsung,exynos-ppmu";
 244                 reg = <0x12240000 0x2000>;
 245                 clocks = <&clock CLK_PPMULCD1>;
 246                 clock-names = "ppmu";
 247                 status = "disabled";
 248         };
 249
 250         sysmmu_g2d: sysmmu@12A20000 {
 251                 compatible = "samsung,exynos-sysmmu";
 252                 reg = <0x12A20000 0x1000>;
 253                 interrupt-parent = <&combiner>;
 254                 interrupts = <4 7>;
 255                 clock-names = "sysmmu", "master";
 256                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 257                 power-domains = <&pd_lcd0>;
 258                 #iommu-cells = <0>;
 259         };
 260
 261         sysmmu_fimd1: sysmmu@12220000 {
 262                 compatible = "samsung,exynos-sysmmu";
 263                 interrupt-parent = <&combiner>;
 264                 reg = <0x12220000 0x1000>;
 265                 interrupts = <5 3>;
 266                 clock-names = "sysmmu", "master";
 267                 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 268                 power-domains = <&pd_lcd1>;
 269                 #iommu-cells = <0>;
 270         };
 271
 272         bus_dmc: bus_dmc {
 273                 compatible = "samsung,exynos-bus";
 274                 clocks = <&clock CLK_DIV_DMC>;
 275                 clock-names = "bus";
 276                 operating-points-v2 = <&bus_dmc_opp_table>;
 277                 status = "disabled";
 278         };
 279
 280         bus_acp: bus_acp {
 281                 compatible = "samsung,exynos-bus";
 282                 clocks = <&clock CLK_DIV_ACP>;
 283                 clock-names = "bus";
 284                 operating-points-v2 = <&bus_acp_opp_table>;
 285                 status = "disabled";
 286         };
 287
 288         bus_peri: bus_peri {
 289                 compatible = "samsung,exynos-bus";
 290                 clocks = <&clock CLK_ACLK100>;
 291                 clock-names = "bus";
 292                 operating-points-v2 = <&bus_peri_opp_table>;
 293                 status = "disabled";
 294         };
 295
 296         bus_fsys: bus_fsys {
 297                 compatible = "samsung,exynos-bus";
 298                 clocks = <&clock CLK_ACLK133>;
 299                 clock-names = "bus";
 300                 operating-points-v2 = <&bus_fsys_opp_table>;
 301                 status = "disabled";
 302         };
 303
 304         bus_display: bus_display {
 305                 compatible = "samsung,exynos-bus";
 306                 clocks = <&clock CLK_ACLK160>;
 307                 clock-names = "bus";
 308                 operating-points-v2 = <&bus_display_opp_table>;
 309                 status = "disabled";
 310         };
 311
 312         bus_lcd0: bus_lcd0 {
 313                 compatible = "samsung,exynos-bus";
 314                 clocks = <&clock CLK_ACLK200>;
 315                 clock-names = "bus";
 316                 operating-points-v2 = <&bus_leftbus_opp_table>;
 317                 status = "disabled";
 318         };
 319
 320         bus_leftbus: bus_leftbus {
 321                 compatible = "samsung,exynos-bus";
 322                 clocks = <&clock CLK_DIV_GDL>;
 323                 clock-names = "bus";
 324                 operating-points-v2 = <&bus_leftbus_opp_table>;
 325                 status = "disabled";
 326         };
 327
 328         bus_rightbus: bus_rightbus {
 329                 compatible = "samsung,exynos-bus";
 330                 clocks = <&clock CLK_DIV_GDR>;
 331                 clock-names = "bus";
 332                 operating-points-v2 = <&bus_leftbus_opp_table>;
 333                 status = "disabled";
 334         };
 335
 336         bus_mfc: bus_mfc {
 337                 compatible = "samsung,exynos-bus";
 338                 clocks = <&clock CLK_SCLK_MFC>;
 339                 clock-names = "bus";
 340                 operating-points-v2 = <&bus_leftbus_opp_table>;
 341                 status = "disabled";
 342         };
 343
 344         bus_dmc_opp_table: opp_table1 {
 345                 compatible = "operating-points-v2";
 346                 opp-shared;
 347
 348                 opp@134000000 {
 349                         opp-hz = /bits/ 64 <134000000>;
 350                         opp-microvolt = <1025000>;
 351                 };
 352                 opp@267000000 {
 353                         opp-hz = /bits/ 64 <267000000>;
 354                         opp-microvolt = <1050000>;
 355                 };
 356                 opp@400000000 {
 357                         opp-hz = /bits/ 64 <400000000>;
 358                         opp-microvolt = <1150000>;
 359                 };
 360         };
 361
 362         bus_acp_opp_table: opp_table2 {
 363                 compatible = "operating-points-v2";
 364                 opp-shared;
 365
 366                 opp@134000000 {
 367                         opp-hz = /bits/ 64 <134000000>;
 368                 };
 369                 opp@160000000 {
 370                         opp-hz = /bits/ 64 <160000000>;
 371                 };
 372                 opp@200000000 {
 373                         opp-hz = /bits/ 64 <200000000>;
 374                 };
 375         };
 376
 377         bus_peri_opp_table: opp_table3 {
 378                 compatible = "operating-points-v2";
 379                 opp-shared;
 380
 381                 opp@5000000 {
 382                         opp-hz = /bits/ 64 <5000000>;
 383                 };
 384                 opp@100000000 {
 385                         opp-hz = /bits/ 64 <100000000>;
 386                 };
 387         };
 388
 389         bus_fsys_opp_table: opp_table4 {
 390                 compatible = "operating-points-v2";
 391                 opp-shared;
 392
 393                 opp@10000000 {
 394                         opp-hz = /bits/ 64 <10000000>;
 395                 };
 396                 opp@134000000 {
 397                         opp-hz = /bits/ 64 <134000000>;
 398                 };
 399         };
 400
 401         bus_display_opp_table: opp_table5 {
 402                 compatible = "operating-points-v2";
 403                 opp-shared;
 404
 405                 opp@100000000 {
 406                         opp-hz = /bits/ 64 <100000000>;
 407                 };
 408                 opp@134000000 {
 409                         opp-hz = /bits/ 64 <134000000>;
 410                 };
 411                 opp@160000000 {
 412                         opp-hz = /bits/ 64 <160000000>;
 413                 };
 414         };
 415
 416         bus_leftbus_opp_table: opp_table6 {
 417                 compatible = "operating-points-v2";
 418                 opp-shared;
 419
 420                 opp@100000000 {
 421                         opp-hz = /bits/ 64 <100000000>;
 422                 };
 423                 opp@160000000 {
 424                         opp-hz = /bits/ 64 <160000000>;
 425                 };
 426                 opp@200000000 {
 427                         opp-hz = /bits/ 64 <200000000>;
 428                 };
 429         };
 430 };
 431
 432 &gic {
 433         cpu-offset = <0x8000>;
 434 };
 435
 436 &combiner {
 437         samsung,combiner-nr = <16>;
 438         interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
 439                      <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 440                      <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 441                      <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 442 };
 443
 444 &mdma1 {
 445         power-domains = <&pd_lcd0>;
 446 };
 447
 448 &pmu_system_controller {
 449         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 450                         "clkout4", "clkout8", "clkout9";
 451         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 452                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 453                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 454         #clock-cells = <1>;
 455 };
 456
 457 &rotator {
 458         power-domains = <&pd_lcd0>;
 459 };
 460
 461 &sysmmu_rotator {
 462         power-domains = <&pd_lcd0>;
 463 };