2 * Samsung's Exynos3250 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4-cpu-thermal.dtsi"
21 #include "exynos-syscon-restart.dtsi"
22 #include <dt-bindings/clock/exynos3250.h>
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
31 pinctrl0 = &pinctrl_0;
32 pinctrl1 = &pinctrl_1;
57 compatible = "arm,cortex-a7";
59 clock-frequency = <1000000000>;
60 clocks = <&cmu CLK_ARM_CLK>;
80 compatible = "arm,cortex-a7";
82 clock-frequency = <1000000000>;
83 clocks = <&cmu CLK_ARM_CLK>;
103 compatible = "simple-bus";
104 #address-cells = <1>;
109 #address-cells = <1>;
113 compatible = "fixed-clock";
114 #address-cells = <1>;
117 clock-frequency = <0>;
119 clock-output-names = "xusbxti";
123 compatible = "fixed-clock";
125 clock-frequency = <0>;
127 clock-output-names = "xxti";
131 compatible = "fixed-clock";
133 clock-frequency = <0>;
135 clock-output-names = "xtcxo";
140 compatible = "mmio-sram";
141 reg = <0x02020000 0x40000>;
142 #address-cells = <1>;
144 ranges = <0 0x02020000 0x40000>;
147 compatible = "samsung,exynos4210-sysram";
152 compatible = "samsung,exynos4210-sysram-ns";
153 reg = <0x3f000 0x1000>;
158 compatible = "samsung,exynos4210-chipid";
159 reg = <0x10000000 0x100>;
162 sys_reg: syscon@10010000 {
163 compatible = "samsung,exynos3-sysreg", "syscon";
164 reg = <0x10010000 0x400>;
167 pmu_system_controller: system-controller@10020000 {
168 compatible = "samsung,exynos3250-pmu", "syscon";
169 reg = <0x10020000 0x4000>;
170 interrupt-controller;
171 #interrupt-cells = <3>;
172 interrupt-parent = <&gic>;
173 clock-names = "clkout8";
174 clocks = <&cmu CLK_FIN_PLL>;
178 mipi_phy: video-phy {
179 compatible = "samsung,s5pv210-mipi-video-phy";
181 syscon = <&pmu_system_controller>;
184 pd_cam: cam-power-domain@10023C00 {
185 compatible = "samsung,exynos4210-pd";
186 reg = <0x10023C00 0x20>;
187 #power-domain-cells = <0>;
190 pd_mfc: mfc-power-domain@10023C40 {
191 compatible = "samsung,exynos4210-pd";
192 reg = <0x10023C40 0x20>;
193 #power-domain-cells = <0>;
196 pd_g3d: g3d-power-domain@10023C60 {
197 compatible = "samsung,exynos4210-pd";
198 reg = <0x10023C60 0x20>;
199 #power-domain-cells = <0>;
202 pd_lcd0: lcd0-power-domain@10023C80 {
203 compatible = "samsung,exynos4210-pd";
204 reg = <0x10023C80 0x20>;
205 #power-domain-cells = <0>;
208 pd_isp: isp-power-domain@10023CA0 {
209 compatible = "samsung,exynos4210-pd";
210 reg = <0x10023CA0 0x20>;
211 #power-domain-cells = <0>;
214 cmu: clock-controller@10030000 {
215 compatible = "samsung,exynos3250-cmu";
216 reg = <0x10030000 0x20000>;
218 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
219 <&cmu CLK_MOUT_ACLK_266_SUB>;
220 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
224 cmu_dmc: clock-controller@105C0000 {
225 compatible = "samsung,exynos3250-cmu-dmc";
226 reg = <0x105C0000 0x2000>;
231 compatible = "samsung,s3c6410-rtc";
232 reg = <0x10070000 0x100>;
233 interrupts = <0 73 0>, <0 74 0>;
234 interrupt-parent = <&pmu_system_controller>;
239 compatible = "samsung,exynos3250-tmu";
240 reg = <0x100C0000 0x100>;
241 interrupts = <0 216 0>;
242 clocks = <&cmu CLK_TMU_APBIF>;
243 clock-names = "tmu_apbif";
244 #include "exynos4412-tmu-sensor-conf.dtsi"
248 gic: interrupt-controller@10481000 {
249 compatible = "arm,cortex-a15-gic";
250 #interrupt-cells = <3>;
251 interrupt-controller;
252 reg = <0x10481000 0x1000>,
256 interrupts = <1 9 0xf04>;
260 compatible = "samsung,exynos4210-mct";
261 reg = <0x10050000 0x800>;
262 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
263 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
264 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
265 clock-names = "fin_pll", "mct";
268 pinctrl_1: pinctrl@11000000 {
269 compatible = "samsung,exynos3250-pinctrl";
270 reg = <0x11000000 0x1000>;
271 interrupts = <0 225 0>;
273 wakeup-interrupt-controller {
274 compatible = "samsung,exynos4210-wakeup-eint";
275 interrupts = <0 48 0>;
279 pinctrl_0: pinctrl@11400000 {
280 compatible = "samsung,exynos3250-pinctrl";
281 reg = <0x11400000 0x1000>;
282 interrupts = <0 240 0>;
285 jpeg: codec@11830000 {
286 compatible = "samsung,exynos3250-jpeg";
287 reg = <0x11830000 0x1000>;
288 interrupts = <0 171 0>;
289 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
290 clock-names = "jpeg", "sclk";
291 power-domains = <&pd_cam>;
292 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
293 assigned-clock-rates = <0>, <150000000>;
294 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
295 iommus = <&sysmmu_jpeg>;
299 sysmmu_jpeg: sysmmu@11A60000 {
300 compatible = "samsung,exynos-sysmmu";
301 reg = <0x11a60000 0x1000>;
302 interrupts = <0 156 0>, <0 161 0>;
303 clock-names = "sysmmu", "master";
304 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
305 power-domains = <&pd_cam>;
309 fimd: fimd@11c00000 {
310 compatible = "samsung,exynos3250-fimd";
311 reg = <0x11c00000 0x30000>;
312 interrupt-names = "fifo", "vsync", "lcd_sys";
313 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
314 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
315 clock-names = "sclk_fimd", "fimd";
316 power-domains = <&pd_lcd0>;
317 iommus = <&sysmmu_fimd0>;
318 samsung,sysreg = <&sys_reg>;
322 dsi_0: dsi@11C80000 {
323 compatible = "samsung,exynos3250-mipi-dsi";
324 reg = <0x11C80000 0x10000>;
325 interrupts = <0 83 0>;
326 samsung,phy-type = <0>;
327 power-domains = <&pd_lcd0>;
328 phys = <&mipi_phy 1>;
330 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
331 clock-names = "bus_clk", "pll_clk";
332 #address-cells = <1>;
337 sysmmu_fimd0: sysmmu@11E20000 {
338 compatible = "samsung,exynos-sysmmu";
339 reg = <0x11e20000 0x1000>;
340 interrupts = <0 80 0>, <0 81 0>;
341 clock-names = "sysmmu", "master";
342 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
343 power-domains = <&pd_lcd0>;
347 hsotg: hsotg@12480000 {
348 compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
349 reg = <0x12480000 0x20000>;
350 interrupts = <0 141 0>;
351 clocks = <&cmu CLK_USBOTG>;
353 phys = <&exynos_usbphy 0>;
354 phy-names = "usb2-phy";
358 mshc_0: mshc@12510000 {
359 compatible = "samsung,exynos5420-dw-mshc";
360 reg = <0x12510000 0x1000>;
361 interrupts = <0 142 0>;
362 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
363 clock-names = "biu", "ciu";
365 #address-cells = <1>;
370 mshc_1: mshc@12520000 {
371 compatible = "samsung,exynos5420-dw-mshc";
372 reg = <0x12520000 0x1000>;
373 interrupts = <0 143 0>;
374 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
375 clock-names = "biu", "ciu";
377 #address-cells = <1>;
382 mshc_2: mshc@12530000 {
383 compatible = "samsung,exynos5250-dw-mshc";
384 reg = <0x12530000 0x1000>;
385 interrupts = <0 144 0>;
386 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
387 clock-names = "biu", "ciu";
389 #address-cells = <1>;
394 exynos_usbphy: exynos-usbphy@125B0000 {
395 compatible = "samsung,exynos3250-usb2-phy";
396 reg = <0x125B0000 0x100>;
397 samsung,pmureg-phandle = <&pmu_system_controller>;
398 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
399 clock-names = "phy", "ref";
405 compatible = "simple-bus";
406 #address-cells = <1>;
410 pdma0: pdma@12680000 {
411 compatible = "arm,pl330", "arm,primecell";
412 reg = <0x12680000 0x1000>;
413 interrupts = <0 138 0>;
414 clocks = <&cmu CLK_PDMA0>;
415 clock-names = "apb_pclk";
418 #dma-requests = <32>;
421 pdma1: pdma@12690000 {
422 compatible = "arm,pl330", "arm,primecell";
423 reg = <0x12690000 0x1000>;
424 interrupts = <0 139 0>;
425 clocks = <&cmu CLK_PDMA1>;
426 clock-names = "apb_pclk";
429 #dma-requests = <32>;
434 compatible = "samsung,exynos3250-adc",
435 "samsung,exynos-adc-v2";
436 reg = <0x126C0000 0x100>;
437 interrupts = <0 137 0>;
438 clock-names = "adc", "sclk";
439 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
440 #io-channel-cells = <1>;
442 samsung,syscon-phandle = <&pmu_system_controller>;
446 mfc: codec@13400000 {
447 compatible = "samsung,mfc-v7";
448 reg = <0x13400000 0x10000>;
449 interrupts = <0 102 0>;
450 clock-names = "mfc", "sclk_mfc";
451 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
452 power-domains = <&pd_mfc>;
453 iommus = <&sysmmu_mfc>;
456 sysmmu_mfc: sysmmu@13620000 {
457 compatible = "samsung,exynos-sysmmu";
458 reg = <0x13620000 0x1000>;
459 interrupts = <0 96 0>, <0 98 0>;
460 clock-names = "sysmmu", "master";
461 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
462 power-domains = <&pd_mfc>;
466 serial_0: serial@13800000 {
467 compatible = "samsung,exynos4210-uart";
468 reg = <0x13800000 0x100>;
469 interrupts = <0 109 0>;
470 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
471 clock-names = "uart", "clk_uart_baud0";
472 pinctrl-names = "default";
473 pinctrl-0 = <&uart0_data &uart0_fctl>;
477 serial_1: serial@13810000 {
478 compatible = "samsung,exynos4210-uart";
479 reg = <0x13810000 0x100>;
480 interrupts = <0 110 0>;
481 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
482 clock-names = "uart", "clk_uart_baud0";
483 pinctrl-names = "default";
484 pinctrl-0 = <&uart1_data>;
488 serial_2: serial@13820000 {
489 compatible = "samsung,exynos4210-uart";
490 reg = <0x13820000 0x100>;
491 interrupts = <0 111 0>;
492 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
493 clock-names = "uart", "clk_uart_baud0";
494 pinctrl-names = "default";
495 pinctrl-0 = <&uart2_data>;
499 i2c_0: i2c@13860000 {
500 #address-cells = <1>;
502 compatible = "samsung,s3c2440-i2c";
503 reg = <0x13860000 0x100>;
504 interrupts = <0 113 0>;
505 clocks = <&cmu CLK_I2C0>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c0_bus>;
512 i2c_1: i2c@13870000 {
513 #address-cells = <1>;
515 compatible = "samsung,s3c2440-i2c";
516 reg = <0x13870000 0x100>;
517 interrupts = <0 114 0>;
518 clocks = <&cmu CLK_I2C1>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c1_bus>;
525 i2c_2: i2c@13880000 {
526 #address-cells = <1>;
528 compatible = "samsung,s3c2440-i2c";
529 reg = <0x13880000 0x100>;
530 interrupts = <0 115 0>;
531 clocks = <&cmu CLK_I2C2>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c2_bus>;
538 i2c_3: i2c@13890000 {
539 #address-cells = <1>;
541 compatible = "samsung,s3c2440-i2c";
542 reg = <0x13890000 0x100>;
543 interrupts = <0 116 0>;
544 clocks = <&cmu CLK_I2C3>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c3_bus>;
551 i2c_4: i2c@138A0000 {
552 #address-cells = <1>;
554 compatible = "samsung,s3c2440-i2c";
555 reg = <0x138A0000 0x100>;
556 interrupts = <0 117 0>;
557 clocks = <&cmu CLK_I2C4>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c4_bus>;
564 i2c_5: i2c@138B0000 {
565 #address-cells = <1>;
567 compatible = "samsung,s3c2440-i2c";
568 reg = <0x138B0000 0x100>;
569 interrupts = <0 118 0>;
570 clocks = <&cmu CLK_I2C5>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c5_bus>;
577 i2c_6: i2c@138C0000 {
578 #address-cells = <1>;
580 compatible = "samsung,s3c2440-i2c";
581 reg = <0x138C0000 0x100>;
582 interrupts = <0 119 0>;
583 clocks = <&cmu CLK_I2C6>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c6_bus>;
590 i2c_7: i2c@138D0000 {
591 #address-cells = <1>;
593 compatible = "samsung,s3c2440-i2c";
594 reg = <0x138D0000 0x100>;
595 interrupts = <0 120 0>;
596 clocks = <&cmu CLK_I2C7>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&i2c7_bus>;
603 spi_0: spi@13920000 {
604 compatible = "samsung,exynos4210-spi";
605 reg = <0x13920000 0x100>;
606 interrupts = <0 121 0>;
607 dmas = <&pdma0 7>, <&pdma0 6>;
608 dma-names = "tx", "rx";
609 #address-cells = <1>;
611 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
612 clock-names = "spi", "spi_busclk0";
613 samsung,spi-src-clk = <0>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&spi0_bus>;
619 spi_1: spi@13930000 {
620 compatible = "samsung,exynos4210-spi";
621 reg = <0x13930000 0x100>;
622 interrupts = <0 122 0>;
623 dmas = <&pdma1 7>, <&pdma1 6>;
624 dma-names = "tx", "rx";
625 #address-cells = <1>;
627 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
628 clock-names = "spi", "spi_busclk0";
629 samsung,spi-src-clk = <0>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&spi1_bus>;
636 compatible = "samsung,s3c6410-i2s";
637 reg = <0x13970000 0x100>;
638 interrupts = <0 126 0>;
639 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
640 clock-names = "iis", "i2s_opclk0";
641 dmas = <&pdma0 14>, <&pdma0 13>;
642 dma-names = "tx", "rx";
643 pinctrl-0 = <&i2s2_bus>;
644 pinctrl-names = "default";
649 compatible = "samsung,exynos4210-pwm";
650 reg = <0x139D0000 0x1000>;
651 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
652 <0 107 0>, <0 108 0>;
658 compatible = "arm,cortex-a7-pmu";
659 interrupts = <0 18 0>, <0 19 0>;
662 ppmu_dmc0: ppmu_dmc0@106a0000 {
663 compatible = "samsung,exynos-ppmu";
664 reg = <0x106a0000 0x2000>;
668 ppmu_dmc1: ppmu_dmc1@106b0000 {
669 compatible = "samsung,exynos-ppmu";
670 reg = <0x106b0000 0x2000>;
674 ppmu_cpu: ppmu_cpu@106c0000 {
675 compatible = "samsung,exynos-ppmu";
676 reg = <0x106c0000 0x2000>;
680 ppmu_rightbus: ppmu_rightbus@112a0000 {
681 compatible = "samsung,exynos-ppmu";
682 reg = <0x112a0000 0x2000>;
683 clocks = <&cmu CLK_PPMURIGHT>;
684 clock-names = "ppmu";
688 ppmu_leftbus: ppmu_leftbus0@116a0000 {
689 compatible = "samsung,exynos-ppmu";
690 reg = <0x116a0000 0x2000>;
691 clocks = <&cmu CLK_PPMULEFT>;
692 clock-names = "ppmu";
696 ppmu_camif: ppmu_camif@11ac0000 {
697 compatible = "samsung,exynos-ppmu";
698 reg = <0x11ac0000 0x2000>;
699 clocks = <&cmu CLK_PPMUCAMIF>;
700 clock-names = "ppmu";
704 ppmu_lcd0: ppmu_lcd0@11e40000 {
705 compatible = "samsung,exynos-ppmu";
706 reg = <0x11e40000 0x2000>;
707 clocks = <&cmu CLK_PPMULCD0>;
708 clock-names = "ppmu";
712 ppmu_fsys: ppmu_fsys@12630000 {
713 compatible = "samsung,exynos-ppmu";
714 reg = <0x12630000 0x2000>;
715 clocks = <&cmu CLK_PPMUFILE>;
716 clock-names = "ppmu";
720 ppmu_g3d: ppmu_g3d@13220000 {
721 compatible = "samsung,exynos-ppmu";
722 reg = <0x13220000 0x2000>;
723 clocks = <&cmu CLK_PPMUG3D>;
724 clock-names = "ppmu";
728 ppmu_mfc: ppmu_mfc@13660000 {
729 compatible = "samsung,exynos-ppmu";
730 reg = <0x13660000 0x2000>;
731 clocks = <&cmu CLK_PPMUMFC_L>;
732 clock-names = "ppmu";
737 compatible = "samsung,exynos-bus";
738 clocks = <&cmu_dmc CLK_DIV_DMC>;
740 operating-points-v2 = <&bus_dmc_opp_table>;
744 bus_dmc_opp_table: opp_table1 {
745 compatible = "operating-points-v2";
749 opp-hz = /bits/ 64 <50000000>;
750 opp-microvolt = <800000>;
753 opp-hz = /bits/ 64 <100000000>;
754 opp-microvolt = <800000>;
757 opp-hz = /bits/ 64 <134000000>;
758 opp-microvolt = <800000>;
761 opp-hz = /bits/ 64 <200000000>;
762 opp-microvolt = <825000>;
765 opp-hz = /bits/ 64 <400000000>;
766 opp-microvolt = <875000>;
770 bus_leftbus: bus_leftbus {
771 compatible = "samsung,exynos-bus";
772 clocks = <&cmu CLK_DIV_GDL>;
774 operating-points-v2 = <&bus_leftbus_opp_table>;
778 bus_rightbus: bus_rightbus {
779 compatible = "samsung,exynos-bus";
780 clocks = <&cmu CLK_DIV_GDR>;
782 operating-points-v2 = <&bus_leftbus_opp_table>;
787 compatible = "samsung,exynos-bus";
788 clocks = <&cmu CLK_DIV_ACLK_160>;
790 operating-points-v2 = <&bus_leftbus_opp_table>;
795 compatible = "samsung,exynos-bus";
796 clocks = <&cmu CLK_DIV_ACLK_200>;
798 operating-points-v2 = <&bus_leftbus_opp_table>;
802 bus_mcuisp: bus_mcuisp {
803 compatible = "samsung,exynos-bus";
804 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
806 operating-points-v2 = <&bus_mcuisp_opp_table>;
811 compatible = "samsung,exynos-bus";
812 clocks = <&cmu CLK_DIV_ACLK_266>;
814 operating-points-v2 = <&bus_isp_opp_table>;
818 bus_peril: bus_peril {
819 compatible = "samsung,exynos-bus";
820 clocks = <&cmu CLK_DIV_ACLK_100>;
822 operating-points-v2 = <&bus_peril_opp_table>;
827 compatible = "samsung,exynos-bus";
828 clocks = <&cmu CLK_SCLK_MFC>;
830 operating-points-v2 = <&bus_leftbus_opp_table>;
834 bus_leftbus_opp_table: opp_table2 {
835 compatible = "operating-points-v2";
839 opp-hz = /bits/ 64 <50000000>;
840 opp-microvolt = <900000>;
843 opp-hz = /bits/ 64 <80000000>;
844 opp-microvolt = <900000>;
847 opp-hz = /bits/ 64 <100000000>;
848 opp-microvolt = <1000000>;
851 opp-hz = /bits/ 64 <134000000>;
852 opp-microvolt = <1000000>;
855 opp-hz = /bits/ 64 <200000000>;
856 opp-microvolt = <1000000>;
860 bus_mcuisp_opp_table: opp_table3 {
861 compatible = "operating-points-v2";
865 opp-hz = /bits/ 64 <50000000>;
868 opp-hz = /bits/ 64 <80000000>;
871 opp-hz = /bits/ 64 <100000000>;
874 opp-hz = /bits/ 64 <200000000>;
877 opp-hz = /bits/ 64 <400000000>;
881 bus_isp_opp_table: opp_table4 {
882 compatible = "operating-points-v2";
886 opp-hz = /bits/ 64 <50000000>;
889 opp-hz = /bits/ 64 <80000000>;
892 opp-hz = /bits/ 64 <100000000>;
895 opp-hz = /bits/ 64 <200000000>;
898 opp-hz = /bits/ 64 <300000000>;
902 bus_peril_opp_table: opp_table5 {
903 compatible = "operating-points-v2";
907 opp-hz = /bits/ 64 <50000000>;
910 opp-hz = /bits/ 64 <80000000>;
913 opp-hz = /bits/ 64 <100000000>;
919 #include "exynos3250-pinctrl.dtsi"