arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "exynos4-cpu-thermal.dtsi"
  21 #include "exynos-syscon-restart.dtsi"
  22 #include <dt-bindings/clock/exynos3250.h>
  23 #include <dt-bindings/interrupt-controller/arm-gic.h>
  24 #include <dt-bindings/interrupt-controller/irq.h>
  25
  26 / {
  27         compatible = "samsung,exynos3250";
  28         interrupt-parent = <&gic>;
  29         #address-cells = <1>;
  30         #size-cells = <1>;
  31
  32         aliases {
  33                 pinctrl0 = &pinctrl_0;
  34                 pinctrl1 = &pinctrl_1;
  35                 mshc0 = &mshc_0;
  36                 mshc1 = &mshc_1;
  37                 mshc2 = &mshc_2;
  38                 spi0 = &spi_0;
  39                 spi1 = &spi_1;
  40                 i2c0 = &i2c_0;
  41                 i2c1 = &i2c_1;
  42                 i2c2 = &i2c_2;
  43                 i2c3 = &i2c_3;
  44                 i2c4 = &i2c_4;
  45                 i2c5 = &i2c_5;
  46                 i2c6 = &i2c_6;
  47                 i2c7 = &i2c_7;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <0>;
  61                         clock-frequency = <1000000000>;
  62                         clocks = <&cmu CLK_ARM_CLK>;
  63                         clock-names = "cpu";
  64                         #cooling-cells = <2>;
  65
  66                         operating-points = <
  67                                 1000000 1150000
  68                                 900000  1112500
  69                                 800000  1075000
  70                                 700000  1037500
  71                                 600000  1000000
  72                                 500000  962500
  73                                 400000  925000
  74                                 300000  887500
  75                                 200000  850000
  76                                 100000  850000
  77                         >;
  78                 };
  79
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <1>;
  84                         clock-frequency = <1000000000>;
  85                         clocks = <&cmu CLK_ARM_CLK>;
  86                         clock-names = "cpu";
  87                         #cooling-cells = <2>;
  88
  89                         operating-points = <
  90                                 1000000 1150000
  91                                 900000  1112500
  92                                 800000  1075000
  93                                 700000  1037500
  94                                 600000  1000000
  95                                 500000  962500
  96                                 400000  925000
  97                                 300000  887500
  98                                 200000  850000
  99                                 100000  850000
 100                         >;
 101                 };
 102         };
 103
 104         soc: soc {
 105                 compatible = "simple-bus";
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 fixed-rate-clocks {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113
 114                         xusbxti: clock@0 {
 115                                 compatible = "fixed-clock";
 116                                 #address-cells = <1>;
 117                                 #size-cells = <0>;
 118                                 reg = <0>;
 119                                 clock-frequency = <0>;
 120                                 #clock-cells = <0>;
 121                                 clock-output-names = "xusbxti";
 122                         };
 123
 124                         xxti: clock@1 {
 125                                 compatible = "fixed-clock";
 126                                 reg = <1>;
 127                                 clock-frequency = <0>;
 128                                 #clock-cells = <0>;
 129                                 clock-output-names = "xxti";
 130                         };
 131
 132                         xtcxo: clock@2 {
 133                                 compatible = "fixed-clock";
 134                                 reg = <2>;
 135                                 clock-frequency = <0>;
 136                                 #clock-cells = <0>;
 137                                 clock-output-names = "xtcxo";
 138                         };
 139                 };
 140
 141                 sysram@02020000 {
 142                         compatible = "mmio-sram";
 143                         reg = <0x02020000 0x40000>;
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0 0x02020000 0x40000>;
 147
 148                         smp-sysram@0 {
 149                                 compatible = "samsung,exynos4210-sysram";
 150                                 reg = <0x0 0x1000>;
 151                         };
 152
 153                         smp-sysram@3f000 {
 154                                 compatible = "samsung,exynos4210-sysram-ns";
 155                                 reg = <0x3f000 0x1000>;
 156                         };
 157                 };
 158
 159                 chipid@10000000 {
 160                         compatible = "samsung,exynos4210-chipid";
 161                         reg = <0x10000000 0x100>;
 162                 };
 163
 164                 sys_reg: syscon@10010000 {
 165                         compatible = "samsung,exynos3-sysreg", "syscon";
 166                         reg = <0x10010000 0x400>;
 167                 };
 168
 169                 pmu_system_controller: system-controller@10020000 {
 170                         compatible = "samsung,exynos3250-pmu", "syscon";
 171                         reg = <0x10020000 0x4000>;
 172                         interrupt-controller;
 173                         #interrupt-cells = <3>;
 174                         interrupt-parent = <&gic>;
 175                         clock-names = "clkout8";
 176                         clocks = <&cmu CLK_FIN_PLL>;
 177                         #clock-cells = <1>;
 178                 };
 179
 180                 mipi_phy: video-phy {
 181                         compatible = "samsung,s5pv210-mipi-video-phy";
 182                         #phy-cells = <1>;
 183                         syscon = <&pmu_system_controller>;
 184                 };
 185
 186                 pd_cam: cam-power-domain@10023C00 {
 187                         compatible = "samsung,exynos4210-pd";
 188                         reg = <0x10023C00 0x20>;
 189                         #power-domain-cells = <0>;
 190                 };
 191
 192                 pd_mfc: mfc-power-domain@10023C40 {
 193                         compatible = "samsung,exynos4210-pd";
 194                         reg = <0x10023C40 0x20>;
 195                         #power-domain-cells = <0>;
 196                 };
 197
 198                 pd_g3d: g3d-power-domain@10023C60 {
 199                         compatible = "samsung,exynos4210-pd";
 200                         reg = <0x10023C60 0x20>;
 201                         #power-domain-cells = <0>;
 202                 };
 203
 204                 pd_lcd0: lcd0-power-domain@10023C80 {
 205                         compatible = "samsung,exynos4210-pd";
 206                         reg = <0x10023C80 0x20>;
 207                         #power-domain-cells = <0>;
 208                 };
 209
 210                 pd_isp: isp-power-domain@10023CA0 {
 211                         compatible = "samsung,exynos4210-pd";
 212                         reg = <0x10023CA0 0x20>;
 213                         #power-domain-cells = <0>;
 214                 };
 215
 216                 cmu: clock-controller@10030000 {
 217                         compatible = "samsung,exynos3250-cmu";
 218                         reg = <0x10030000 0x20000>;
 219                         #clock-cells = <1>;
 220                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 221                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 222                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 223                                                  <&cmu CLK_FIN_PLL>;
 224                 };
 225
 226                 cmu_dmc: clock-controller@105C0000 {
 227                         compatible = "samsung,exynos3250-cmu-dmc";
 228                         reg = <0x105C0000 0x2000>;
 229                         #clock-cells = <1>;
 230                 };
 231
 232                 rtc: rtc@10070000 {
 233                         compatible = "samsung,s3c6410-rtc";
 234                         reg = <0x10070000 0x100>;
 235                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 237                         interrupt-parent = <&pmu_system_controller>;
 238                         status = "disabled";
 239                 };
 240
 241                 tmu: tmu@100C0000 {
 242                         compatible = "samsung,exynos3250-tmu";
 243                         reg = <0x100C0000 0x100>;
 244                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&cmu CLK_TMU_APBIF>;
 246                         clock-names = "tmu_apbif";
 247                         #include "exynos4412-tmu-sensor-conf.dtsi"
 248                         status = "disabled";
 249                 };
 250
 251                 gic: interrupt-controller@10481000 {
 252                         compatible = "arm,cortex-a15-gic";
 253                         #interrupt-cells = <3>;
 254                         interrupt-controller;
 255                         reg = <0x10481000 0x1000>,
 256                               <0x10482000 0x2000>,
 257                               <0x10484000 0x2000>,
 258                               <0x10486000 0x2000>;
 259                         interrupts = <GIC_PPI 9
 260                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 261                 };
 262
 263                 mct@10050000 {
 264                         compatible = "samsung,exynos4210-mct";
 265                         reg = <0x10050000 0x800>;
 266                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 267                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 268                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 269                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 271                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 275                         clock-names = "fin_pll", "mct";
 276                 };
 277
 278                 pinctrl_1: pinctrl@11000000 {
 279                         compatible = "samsung,exynos3250-pinctrl";
 280                         reg = <0x11000000 0x1000>;
 281                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 282
 283                         wakeup-interrupt-controller {
 284                                 compatible = "samsung,exynos4210-wakeup-eint";
 285                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 286                         };
 287                 };
 288
 289                 pinctrl_0: pinctrl@11400000 {
 290                         compatible = "samsung,exynos3250-pinctrl";
 291                         reg = <0x11400000 0x1000>;
 292                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 293                 };
 294
 295                 jpeg: codec@11830000 {
 296                         compatible = "samsung,exynos3250-jpeg";
 297                         reg = <0x11830000 0x1000>;
 298                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 300                         clock-names = "jpeg", "sclk";
 301                         power-domains = <&pd_cam>;
 302                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 303                         assigned-clock-rates = <0>, <150000000>;
 304                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 305                         iommus = <&sysmmu_jpeg>;
 306                         status = "disabled";
 307                 };
 308
 309                 sysmmu_jpeg: sysmmu@11A60000 {
 310                         compatible = "samsung,exynos-sysmmu";
 311                         reg = <0x11a60000 0x1000>;
 312                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 314                         clock-names = "sysmmu", "master";
 315                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 316                         power-domains = <&pd_cam>;
 317                         #iommu-cells = <0>;
 318                 };
 319
 320                 fimd: fimd@11c00000 {
 321                         compatible = "samsung,exynos3250-fimd";
 322                         reg = <0x11c00000 0x30000>;
 323                         interrupt-names = "fifo", "vsync", "lcd_sys";
 324                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 326                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 328                         clock-names = "sclk_fimd", "fimd";
 329                         power-domains = <&pd_lcd0>;
 330                         iommus = <&sysmmu_fimd0>;
 331                         samsung,sysreg = <&sys_reg>;
 332                         status = "disabled";
 333                 };
 334
 335                 dsi_0: dsi@11C80000 {
 336                         compatible = "samsung,exynos3250-mipi-dsi";
 337                         reg = <0x11C80000 0x10000>;
 338                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 339                         samsung,phy-type = <0>;
 340                         power-domains = <&pd_lcd0>;
 341                         phys = <&mipi_phy 1>;
 342                         phy-names = "dsim";
 343                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 344                         clock-names = "bus_clk", "pll_clk";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         status = "disabled";
 348                 };
 349
 350                 sysmmu_fimd0: sysmmu@11E20000 {
 351                         compatible = "samsung,exynos-sysmmu";
 352                         reg = <0x11e20000 0x1000>;
 353                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 355                         clock-names = "sysmmu", "master";
 356                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 357                         power-domains = <&pd_lcd0>;
 358                         #iommu-cells = <0>;
 359                 };
 360
 361                 hsotg: hsotg@12480000 {
 362                         compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
 363                         reg = <0x12480000 0x20000>;
 364                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&cmu CLK_USBOTG>;
 366                         clock-names = "otg";
 367                         phys = <&exynos_usbphy 0>;
 368                         phy-names = "usb2-phy";
 369                         status = "disabled";
 370                 };
 371
 372                 mshc_0: mshc@12510000 {
 373                         compatible = "samsung,exynos5420-dw-mshc";
 374                         reg = <0x12510000 0x1000>;
 375                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 377                         clock-names = "biu", "ciu";
 378                         fifo-depth = <0x80>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         status = "disabled";
 382                 };
 383
 384                 mshc_1: mshc@12520000 {
 385                         compatible = "samsung,exynos5420-dw-mshc";
 386                         reg = <0x12520000 0x1000>;
 387                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 389                         clock-names = "biu", "ciu";
 390                         fifo-depth = <0x80>;
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         status = "disabled";
 394                 };
 395
 396                 mshc_2: mshc@12530000 {
 397                         compatible = "samsung,exynos5250-dw-mshc";
 398                         reg = <0x12530000 0x1000>;
 399                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 401                         clock-names = "biu", "ciu";
 402                         fifo-depth = <0x80>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         status = "disabled";
 406                 };
 407
 408                 exynos_usbphy: exynos-usbphy@125B0000 {
 409                         compatible = "samsung,exynos3250-usb2-phy";
 410                         reg = <0x125B0000 0x100>;
 411                         samsung,pmureg-phandle = <&pmu_system_controller>;
 412                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 413                         clock-names = "phy", "ref";
 414                         #phy-cells = <1>;
 415                         status = "disabled";
 416                 };
 417
 418                 amba {
 419                         compatible = "simple-bus";
 420                         #address-cells = <1>;
 421                         #size-cells = <1>;
 422                         ranges;
 423
 424                         pdma0: pdma@12680000 {
 425                                 compatible = "arm,pl330", "arm,primecell";
 426                                 reg = <0x12680000 0x1000>;
 427                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 428                                 clocks = <&cmu CLK_PDMA0>;
 429                                 clock-names = "apb_pclk";
 430                                 #dma-cells = <1>;
 431                                 #dma-channels = <8>;
 432                                 #dma-requests = <32>;
 433                         };
 434
 435                         pdma1: pdma@12690000 {
 436                                 compatible = "arm,pl330", "arm,primecell";
 437                                 reg = <0x12690000 0x1000>;
 438                                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&cmu CLK_PDMA1>;
 440                                 clock-names = "apb_pclk";
 441                                 #dma-cells = <1>;
 442                                 #dma-channels = <8>;
 443                                 #dma-requests = <32>;
 444                         };
 445                 };
 446
 447                 adc: adc@126C0000 {
 448                         compatible = "samsung,exynos3250-adc",
 449                                      "samsung,exynos-adc-v2";
 450                         reg = <0x126C0000 0x100>;
 451                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 452                         clock-names = "adc", "sclk";
 453                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 454                         #io-channel-cells = <1>;
 455                         io-channel-ranges;
 456                         samsung,syscon-phandle = <&pmu_system_controller>;
 457                         status = "disabled";
 458                 };
 459
 460                 mfc: codec@13400000 {
 461                         compatible = "samsung,mfc-v7";
 462                         reg = <0x13400000 0x10000>;
 463                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 464                         clock-names = "mfc", "sclk_mfc";
 465                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 466                         power-domains = <&pd_mfc>;
 467                         iommus = <&sysmmu_mfc>;
 468                 };
 469
 470                 sysmmu_mfc: sysmmu@13620000 {
 471                         compatible = "samsung,exynos-sysmmu";
 472                         reg = <0x13620000 0x1000>;
 473                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 474                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 475                         clock-names = "sysmmu", "master";
 476                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 477                         power-domains = <&pd_mfc>;
 478                         #iommu-cells = <0>;
 479                 };
 480
 481                 serial_0: serial@13800000 {
 482                         compatible = "samsung,exynos4210-uart";
 483                         reg = <0x13800000 0x100>;
 484                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 485                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 486                         clock-names = "uart", "clk_uart_baud0";
 487                         pinctrl-names = "default";
 488                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 489                         status = "disabled";
 490                 };
 491
 492                 serial_1: serial@13810000 {
 493                         compatible = "samsung,exynos4210-uart";
 494                         reg = <0x13810000 0x100>;
 495                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 496                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 497                         clock-names = "uart", "clk_uart_baud0";
 498                         pinctrl-names = "default";
 499                         pinctrl-0 = <&uart1_data>;
 500                         status = "disabled";
 501                 };
 502
 503                 serial_2: serial@13820000 {
 504                         compatible = "samsung,exynos4210-uart";
 505                         reg = <0x13820000 0x100>;
 506                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 508                         clock-names = "uart", "clk_uart_baud0";
 509                         pinctrl-names = "default";
 510                         pinctrl-0 = <&uart2_data>;
 511                         status = "disabled";
 512                 };
 513
 514                 i2c_0: i2c@13860000 {
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         compatible = "samsung,s3c2440-i2c";
 518                         reg = <0x13860000 0x100>;
 519                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 520                         clocks = <&cmu CLK_I2C0>;
 521                         clock-names = "i2c";
 522                         pinctrl-names = "default";
 523                         pinctrl-0 = <&i2c0_bus>;
 524                         status = "disabled";
 525                 };
 526
 527                 i2c_1: i2c@13870000 {
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         compatible = "samsung,s3c2440-i2c";
 531                         reg = <0x13870000 0x100>;
 532                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&cmu CLK_I2C1>;
 534                         clock-names = "i2c";
 535                         pinctrl-names = "default";
 536                         pinctrl-0 = <&i2c1_bus>;
 537                         status = "disabled";
 538                 };
 539
 540                 i2c_2: i2c@13880000 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         compatible = "samsung,s3c2440-i2c";
 544                         reg = <0x13880000 0x100>;
 545                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&cmu CLK_I2C2>;
 547                         clock-names = "i2c";
 548                         pinctrl-names = "default";
 549                         pinctrl-0 = <&i2c2_bus>;
 550                         status = "disabled";
 551                 };
 552
 553                 i2c_3: i2c@13890000 {
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         compatible = "samsung,s3c2440-i2c";
 557                         reg = <0x13890000 0x100>;
 558                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&cmu CLK_I2C3>;
 560                         clock-names = "i2c";
 561                         pinctrl-names = "default";
 562                         pinctrl-0 = <&i2c3_bus>;
 563                         status = "disabled";
 564                 };
 565
 566                 i2c_4: i2c@138A0000 {
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         compatible = "samsung,s3c2440-i2c";
 570                         reg = <0x138A0000 0x100>;
 571                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&cmu CLK_I2C4>;
 573                         clock-names = "i2c";
 574                         pinctrl-names = "default";
 575                         pinctrl-0 = <&i2c4_bus>;
 576                         status = "disabled";
 577                 };
 578
 579                 i2c_5: i2c@138B0000 {
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         compatible = "samsung,s3c2440-i2c";
 583                         reg = <0x138B0000 0x100>;
 584                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&cmu CLK_I2C5>;
 586                         clock-names = "i2c";
 587                         pinctrl-names = "default";
 588                         pinctrl-0 = <&i2c5_bus>;
 589                         status = "disabled";
 590                 };
 591
 592                 i2c_6: i2c@138C0000 {
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         compatible = "samsung,s3c2440-i2c";
 596                         reg = <0x138C0000 0x100>;
 597                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&cmu CLK_I2C6>;
 599                         clock-names = "i2c";
 600                         pinctrl-names = "default";
 601                         pinctrl-0 = <&i2c6_bus>;
 602                         status = "disabled";
 603                 };
 604
 605                 i2c_7: i2c@138D0000 {
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         compatible = "samsung,s3c2440-i2c";
 609                         reg = <0x138D0000 0x100>;
 610                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&cmu CLK_I2C7>;
 612                         clock-names = "i2c";
 613                         pinctrl-names = "default";
 614                         pinctrl-0 = <&i2c7_bus>;
 615                         status = "disabled";
 616                 };
 617
 618                 spi_0: spi@13920000 {
 619                         compatible = "samsung,exynos4210-spi";
 620                         reg = <0x13920000 0x100>;
 621                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 622                         dmas = <&pdma0 7>, <&pdma0 6>;
 623                         dma-names = "tx", "rx";
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 627                         clock-names = "spi", "spi_busclk0";
 628                         samsung,spi-src-clk = <0>;
 629                         pinctrl-names = "default";
 630                         pinctrl-0 = <&spi0_bus>;
 631                         status = "disabled";
 632                 };
 633
 634                 spi_1: spi@13930000 {
 635                         compatible = "samsung,exynos4210-spi";
 636                         reg = <0x13930000 0x100>;
 637                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 638                         dmas = <&pdma1 7>, <&pdma1 6>;
 639                         dma-names = "tx", "rx";
 640                         #address-cells = <1>;
 641                         #size-cells = <0>;
 642                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 643                         clock-names = "spi", "spi_busclk0";
 644                         samsung,spi-src-clk = <0>;
 645                         pinctrl-names = "default";
 646                         pinctrl-0 = <&spi1_bus>;
 647                         status = "disabled";
 648                 };
 649
 650                 i2s2: i2s@13970000 {
 651                         compatible = "samsung,s3c6410-i2s";
 652                         reg = <0x13970000 0x100>;
 653                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 655                         clock-names = "iis", "i2s_opclk0";
 656                         dmas = <&pdma0 14>, <&pdma0 13>;
 657                         dma-names = "tx", "rx";
 658                         pinctrl-0 = <&i2s2_bus>;
 659                         pinctrl-names = "default";
 660                         status = "disabled";
 661                 };
 662
 663                 pwm: pwm@139D0000 {
 664                         compatible = "samsung,exynos4210-pwm";
 665                         reg = <0x139D0000 0x1000>;
 666                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 668                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 669                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 670                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 671                         #pwm-cells = <3>;
 672                         status = "disabled";
 673                 };
 674
 675                 pmu {
 676                         compatible = "arm,cortex-a7-pmu";
 677                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 679                 };
 680
 681                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 682                         compatible = "samsung,exynos-ppmu";
 683                         reg = <0x106a0000 0x2000>;
 684                         status = "disabled";
 685                 };
 686
 687                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 688                         compatible = "samsung,exynos-ppmu";
 689                         reg = <0x106b0000 0x2000>;
 690                         status = "disabled";
 691                 };
 692
 693                 ppmu_cpu: ppmu_cpu@106c0000 {
 694                         compatible = "samsung,exynos-ppmu";
 695                         reg = <0x106c0000 0x2000>;
 696                         status = "disabled";
 697                 };
 698
 699                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 700                         compatible = "samsung,exynos-ppmu";
 701                         reg = <0x112a0000 0x2000>;
 702                         clocks = <&cmu CLK_PPMURIGHT>;
 703                         clock-names = "ppmu";
 704                         status = "disabled";
 705                 };
 706
 707                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 708                         compatible = "samsung,exynos-ppmu";
 709                         reg = <0x116a0000 0x2000>;
 710                         clocks = <&cmu CLK_PPMULEFT>;
 711                         clock-names = "ppmu";
 712                         status = "disabled";
 713                 };
 714
 715                 ppmu_camif: ppmu_camif@11ac0000 {
 716                         compatible = "samsung,exynos-ppmu";
 717                         reg = <0x11ac0000 0x2000>;
 718                         clocks = <&cmu CLK_PPMUCAMIF>;
 719                         clock-names = "ppmu";
 720                         status = "disabled";
 721                 };
 722
 723                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 724                         compatible = "samsung,exynos-ppmu";
 725                         reg = <0x11e40000 0x2000>;
 726                         clocks = <&cmu CLK_PPMULCD0>;
 727                         clock-names = "ppmu";
 728                         status = "disabled";
 729                 };
 730
 731                 ppmu_fsys: ppmu_fsys@12630000 {
 732                         compatible = "samsung,exynos-ppmu";
 733                         reg = <0x12630000 0x2000>;
 734                         clocks = <&cmu CLK_PPMUFILE>;
 735                         clock-names = "ppmu";
 736                         status = "disabled";
 737                 };
 738
 739                 ppmu_g3d: ppmu_g3d@13220000 {
 740                         compatible = "samsung,exynos-ppmu";
 741                         reg = <0x13220000 0x2000>;
 742                         clocks = <&cmu CLK_PPMUG3D>;
 743                         clock-names = "ppmu";
 744                         status = "disabled";
 745                 };
 746
 747                 ppmu_mfc: ppmu_mfc@13660000 {
 748                         compatible = "samsung,exynos-ppmu";
 749                         reg = <0x13660000 0x2000>;
 750                         clocks = <&cmu CLK_PPMUMFC_L>;
 751                         clock-names = "ppmu";
 752                         status = "disabled";
 753                 };
 754
 755                 bus_dmc: bus_dmc {
 756                         compatible = "samsung,exynos-bus";
 757                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 758                         clock-names = "bus";
 759                         operating-points-v2 = <&bus_dmc_opp_table>;
 760                         status = "disabled";
 761                 };
 762
 763                 bus_dmc_opp_table: opp_table1 {
 764                         compatible = "operating-points-v2";
 765                         opp-shared;
 766
 767                         opp-50000000 {
 768                                 opp-hz = /bits/ 64 <50000000>;
 769                                 opp-microvolt = <800000>;
 770                         };
 771                         opp-100000000 {
 772                                 opp-hz = /bits/ 64 <100000000>;
 773                                 opp-microvolt = <800000>;
 774                         };
 775                         opp-134000000 {
 776                                 opp-hz = /bits/ 64 <134000000>;
 777                                 opp-microvolt = <800000>;
 778                         };
 779                         opp-200000000 {
 780                                 opp-hz = /bits/ 64 <200000000>;
 781                                 opp-microvolt = <825000>;
 782                         };
 783                         opp-400000000 {
 784                                 opp-hz = /bits/ 64 <400000000>;
 785                                 opp-microvolt = <875000>;
 786                         };
 787                 };
 788
 789                 bus_leftbus: bus_leftbus {
 790                         compatible = "samsung,exynos-bus";
 791                         clocks = <&cmu CLK_DIV_GDL>;
 792                         clock-names = "bus";
 793                         operating-points-v2 = <&bus_leftbus_opp_table>;
 794                         status = "disabled";
 795                 };
 796
 797                 bus_rightbus: bus_rightbus {
 798                         compatible = "samsung,exynos-bus";
 799                         clocks = <&cmu CLK_DIV_GDR>;
 800                         clock-names = "bus";
 801                         operating-points-v2 = <&bus_leftbus_opp_table>;
 802                         status = "disabled";
 803                 };
 804
 805                 bus_lcd0: bus_lcd0 {
 806                         compatible = "samsung,exynos-bus";
 807                         clocks = <&cmu CLK_DIV_ACLK_160>;
 808                         clock-names = "bus";
 809                         operating-points-v2 = <&bus_leftbus_opp_table>;
 810                         status = "disabled";
 811                 };
 812
 813                 bus_fsys: bus_fsys {
 814                         compatible = "samsung,exynos-bus";
 815                         clocks = <&cmu CLK_DIV_ACLK_200>;
 816                         clock-names = "bus";
 817                         operating-points-v2 = <&bus_leftbus_opp_table>;
 818                         status = "disabled";
 819                 };
 820
 821                 bus_mcuisp: bus_mcuisp {
 822                         compatible = "samsung,exynos-bus";
 823                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 824                         clock-names = "bus";
 825                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 826                         status = "disabled";
 827                 };
 828
 829                 bus_isp: bus_isp {
 830                         compatible = "samsung,exynos-bus";
 831                         clocks = <&cmu CLK_DIV_ACLK_266>;
 832                         clock-names = "bus";
 833                         operating-points-v2 = <&bus_isp_opp_table>;
 834                         status = "disabled";
 835                 };
 836
 837                 bus_peril: bus_peril {
 838                         compatible = "samsung,exynos-bus";
 839                         clocks = <&cmu CLK_DIV_ACLK_100>;
 840                         clock-names = "bus";
 841                         operating-points-v2 = <&bus_peril_opp_table>;
 842                         status = "disabled";
 843                 };
 844
 845                 bus_mfc: bus_mfc {
 846                         compatible = "samsung,exynos-bus";
 847                         clocks = <&cmu CLK_SCLK_MFC>;
 848                         clock-names = "bus";
 849                         operating-points-v2 = <&bus_leftbus_opp_table>;
 850                         status = "disabled";
 851                 };
 852
 853                 bus_leftbus_opp_table: opp_table2 {
 854                         compatible = "operating-points-v2";
 855                         opp-shared;
 856
 857                         opp-50000000 {
 858                                 opp-hz = /bits/ 64 <50000000>;
 859                                 opp-microvolt = <900000>;
 860                         };
 861                         opp-80000000 {
 862                                 opp-hz = /bits/ 64 <80000000>;
 863                                 opp-microvolt = <900000>;
 864                         };
 865                         opp-100000000 {
 866                                 opp-hz = /bits/ 64 <100000000>;
 867                                 opp-microvolt = <1000000>;
 868                         };
 869                         opp-134000000 {
 870                                 opp-hz = /bits/ 64 <134000000>;
 871                                 opp-microvolt = <1000000>;
 872                         };
 873                         opp-200000000 {
 874                                 opp-hz = /bits/ 64 <200000000>;
 875                                 opp-microvolt = <1000000>;
 876                         };
 877                 };
 878
 879                 bus_mcuisp_opp_table: opp_table3 {
 880                         compatible = "operating-points-v2";
 881                         opp-shared;
 882
 883                         opp-50000000 {
 884                                 opp-hz = /bits/ 64 <50000000>;
 885                         };
 886                         opp-80000000 {
 887                                 opp-hz = /bits/ 64 <80000000>;
 888                         };
 889                         opp-100000000 {
 890                                 opp-hz = /bits/ 64 <100000000>;
 891                         };
 892                         opp-200000000 {
 893                                 opp-hz = /bits/ 64 <200000000>;
 894                         };
 895                         opp-400000000 {
 896                                 opp-hz = /bits/ 64 <400000000>;
 897                         };
 898                 };
 899
 900                 bus_isp_opp_table: opp_table4 {
 901                         compatible = "operating-points-v2";
 902                         opp-shared;
 903
 904                         opp-50000000 {
 905                                 opp-hz = /bits/ 64 <50000000>;
 906                         };
 907                         opp-80000000 {
 908                                 opp-hz = /bits/ 64 <80000000>;
 909                         };
 910                         opp-100000000 {
 911                                 opp-hz = /bits/ 64 <100000000>;
 912                         };
 913                         opp-200000000 {
 914                                 opp-hz = /bits/ 64 <200000000>;
 915                         };
 916                         opp-300000000 {
 917                                 opp-hz = /bits/ 64 <300000000>;
 918                         };
 919                 };
 920
 921                 bus_peril_opp_table: opp_table5 {
 922                         compatible = "operating-points-v2";
 923                         opp-shared;
 924
 925                         opp-50000000 {
 926                                 opp-hz = /bits/ 64 <50000000>;
 927                         };
 928                         opp-80000000 {
 929                                 opp-hz = /bits/ 64 <80000000>;
 930                         };
 931                         opp-100000000 {
 932                                 opp-hz = /bits/ 64 <100000000>;
 933                         };
 934                 };
 935         };
 936 };
 937
 938 #include "exynos3250-pinctrl.dtsi"