arch/arm/boot/dts/exynos3250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos3250 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4-cpu-thermal.dtsi"
  18 #include <dt-bindings/clock/exynos3250.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "samsung,exynos3250";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 mshc2 = &mshc_2;
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 i2c0 = &i2c_0;
  37                 i2c1 = &i2c_1;
  38                 i2c2 = &i2c_2;
  39                 i2c3 = &i2c_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 serial0 = &serial_0;
  45                 serial1 = &serial_1;
  46                 serial2 = &serial_2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu-map {
  54                         cluster0 {
  55                                 core0 {
  56                                         cpu = <&cpu0>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu1>;
  60                                 };
  61                         };
  62                 };
  63
  64                 cpu0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0>;
  68                         clock-frequency = <1000000000>;
  69                         clocks = <&cmu CLK_ARM_CLK>;
  70                         clock-names = "cpu";
  71                         #cooling-cells = <2>;
  72
  73                         operating-points = <
  74                                 1000000 1150000
  75                                 900000  1112500
  76                                 800000  1075000
  77                                 700000  1037500
  78                                 600000  1000000
  79                                 500000  962500
  80                                 400000  925000
  81                                 300000  887500
  82                                 200000  850000
  83                                 100000  850000
  84                         >;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a7";
  90                         reg = <1>;
  91                         clock-frequency = <1000000000>;
  92                         clocks = <&cmu CLK_ARM_CLK>;
  93                         clock-names = "cpu";
  94                         #cooling-cells = <2>;
  95
  96                         operating-points = <
  97                                 1000000 1150000
  98                                 900000  1112500
  99                                 800000  1075000
 100                                 700000  1037500
 101                                 600000  1000000
 102                                 500000  962500
 103                                 400000  925000
 104                                 300000  887500
 105                                 200000  850000
 106                                 100000  850000
 107                         >;
 108                 };
 109         };
 110
 111         xusbxti: clock-0 {
 112                 compatible = "fixed-clock";
 113                 clock-frequency = <0>;
 114                 #clock-cells = <0>;
 115                 clock-output-names = "xusbxti";
 116         };
 117
 118         xxti: clock-1 {
 119                 compatible = "fixed-clock";
 120                 clock-frequency = <0>;
 121                 #clock-cells = <0>;
 122                 clock-output-names = "xxti";
 123         };
 124
 125         xtcxo: clock-2 {
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <0>;
 128                 #clock-cells = <0>;
 129                 clock-output-names = "xtcxo";
 130         };
 131
 132         pmu {
 133                 compatible = "arm,cortex-a7-pmu";
 134                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 135                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 136         };
 137
 138         soc: soc {
 139                 compatible = "simple-bus";
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 ranges;
 143
 144                 sram@2020000 {
 145                         compatible = "mmio-sram";
 146                         reg = <0x02020000 0x40000>;
 147                         #address-cells = <1>;
 148                         #size-cells = <1>;
 149                         ranges = <0 0x02020000 0x40000>;
 150
 151                         smp-sram@0 {
 152                                 compatible = "samsung,exynos4210-sysram";
 153                                 reg = <0x0 0x1000>;
 154                         };
 155
 156                         smp-sram@3f000 {
 157                                 compatible = "samsung,exynos4210-sysram-ns";
 158                                 reg = <0x3f000 0x1000>;
 159                         };
 160                 };
 161
 162                 chipid@10000000 {
 163                         compatible = "samsung,exynos4210-chipid";
 164                         reg = <0x10000000 0x100>;
 165                 };
 166
 167                 sys_reg: syscon@10010000 {
 168                         compatible = "samsung,exynos3-sysreg", "syscon";
 169                         reg = <0x10010000 0x400>;
 170                 };
 171
 172                 pmu_system_controller: system-controller@10020000 {
 173                         compatible = "samsung,exynos3250-pmu", "syscon";
 174                         reg = <0x10020000 0x4000>;
 175                         interrupt-controller;
 176                         #interrupt-cells = <3>;
 177                         interrupt-parent = <&gic>;
 178                         clock-names = "clkout8";
 179                         clocks = <&cmu CLK_FIN_PLL>;
 180                         #clock-cells = <1>;
 181                 };
 182
 183                 mipi_phy: video-phy {
 184                         compatible = "samsung,s5pv210-mipi-video-phy";
 185                         #phy-cells = <1>;
 186                         syscon = <&pmu_system_controller>;
 187                 };
 188
 189                 pd_cam: power-domain@10023c00 {
 190                         compatible = "samsung,exynos4210-pd";
 191                         reg = <0x10023C00 0x20>;
 192                         #power-domain-cells = <0>;
 193                         label = "CAM";
 194                 };
 195
 196                 pd_mfc: power-domain@10023c40 {
 197                         compatible = "samsung,exynos4210-pd";
 198                         reg = <0x10023C40 0x20>;
 199                         #power-domain-cells = <0>;
 200                         label = "MFC";
 201                 };
 202
 203                 pd_g3d: power-domain@10023c60 {
 204                         compatible = "samsung,exynos4210-pd";
 205                         reg = <0x10023C60 0x20>;
 206                         #power-domain-cells = <0>;
 207                         label = "G3D";
 208                 };
 209
 210                 pd_lcd0: power-domain@10023c80 {
 211                         compatible = "samsung,exynos4210-pd";
 212                         reg = <0x10023C80 0x20>;
 213                         #power-domain-cells = <0>;
 214                         label = "LCD0";
 215                 };
 216
 217                 pd_isp: power-domain@10023ca0 {
 218                         compatible = "samsung,exynos4210-pd";
 219                         reg = <0x10023CA0 0x20>;
 220                         #power-domain-cells = <0>;
 221                         label = "ISP";
 222                 };
 223
 224                 cmu: clock-controller@10030000 {
 225                         compatible = "samsung,exynos3250-cmu";
 226                         reg = <0x10030000 0x20000>;
 227                         #clock-cells = <1>;
 228                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 229                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 230                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 231                                                  <&cmu CLK_FIN_PLL>;
 232                 };
 233
 234                 cmu_dmc: clock-controller@105c0000 {
 235                         compatible = "samsung,exynos3250-cmu-dmc";
 236                         reg = <0x105C0000 0x2000>;
 237                         #clock-cells = <1>;
 238                 };
 239
 240                 rtc: rtc@10070000 {
 241                         compatible = "samsung,s3c6410-rtc";
 242                         reg = <0x10070000 0x100>;
 243                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 245                         interrupt-parent = <&pmu_system_controller>;
 246                         status = "disabled";
 247                 };
 248
 249                 tmu: tmu@100c0000 {
 250                         compatible = "samsung,exynos3250-tmu";
 251                         reg = <0x100C0000 0x100>;
 252                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&cmu CLK_TMU_APBIF>;
 254                         clock-names = "tmu_apbif";
 255                         #thermal-sensor-cells = <0>;
 256                         status = "disabled";
 257                 };
 258
 259                 gic: interrupt-controller@10481000 {
 260                         compatible = "arm,cortex-a15-gic";
 261                         #interrupt-cells = <3>;
 262                         interrupt-controller;
 263                         reg = <0x10481000 0x1000>,
 264                               <0x10482000 0x2000>,
 265                               <0x10484000 0x2000>,
 266                               <0x10486000 0x2000>;
 267                         interrupts = <GIC_PPI 9
 268                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 269                 };
 270
 271                 timer@10050000 {
 272                         compatible = "samsung,exynos3250-mct",
 273                                      "samsung,exynos4210-mct";
 274                         reg = <0x10050000 0x800>;
 275                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 279                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 284                         clock-names = "fin_pll", "mct";
 285                 };
 286
 287                 pinctrl_1: pinctrl@11000000 {
 288                         compatible = "samsung,exynos3250-pinctrl";
 289                         reg = <0x11000000 0x1000>;
 290                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 291
 292                         wakeup-interrupt-controller {
 293                                 compatible = "samsung,exynos4210-wakeup-eint";
 294                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 295                         };
 296                 };
 297
 298                 pinctrl_0: pinctrl@11400000 {
 299                         compatible = "samsung,exynos3250-pinctrl";
 300                         reg = <0x11400000 0x1000>;
 301                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 302                 };
 303
 304                 jpeg: codec@11830000 {
 305                         compatible = "samsung,exynos3250-jpeg";
 306                         reg = <0x11830000 0x1000>;
 307                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 309                         clock-names = "jpeg", "sclk";
 310                         power-domains = <&pd_cam>;
 311                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 312                         assigned-clock-rates = <0>, <150000000>;
 313                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 314                         iommus = <&sysmmu_jpeg>;
 315                         status = "disabled";
 316                 };
 317
 318                 sysmmu_jpeg: sysmmu@11a60000 {
 319                         compatible = "samsung,exynos-sysmmu";
 320                         reg = <0x11a60000 0x1000>;
 321                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 322                         clock-names = "sysmmu", "master";
 323                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 324                         power-domains = <&pd_cam>;
 325                         #iommu-cells = <0>;
 326                 };
 327
 328                 fimd: fimd@11c00000 {
 329                         compatible = "samsung,exynos3250-fimd";
 330                         reg = <0x11c00000 0x30000>;
 331                         interrupt-names = "fifo", "vsync", "lcd_sys";
 332                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 336                         clock-names = "sclk_fimd", "fimd";
 337                         power-domains = <&pd_lcd0>;
 338                         iommus = <&sysmmu_fimd0>;
 339                         samsung,sysreg = <&sys_reg>;
 340                         status = "disabled";
 341                 };
 342
 343                 dsi_0: dsi@11c80000 {
 344                         compatible = "samsung,exynos3250-mipi-dsi";
 345                         reg = <0x11C80000 0x10000>;
 346                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 347                         samsung,phy-type = <0>;
 348                         power-domains = <&pd_lcd0>;
 349                         phys = <&mipi_phy 1>;
 350                         phy-names = "dsim";
 351                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 352                         clock-names = "bus_clk", "pll_clk";
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         status = "disabled";
 356                 };
 357
 358                 sysmmu_fimd0: sysmmu@11e20000 {
 359                         compatible = "samsung,exynos-sysmmu";
 360                         reg = <0x11e20000 0x1000>;
 361                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 362                         clock-names = "sysmmu", "master";
 363                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 364                         power-domains = <&pd_lcd0>;
 365                         #iommu-cells = <0>;
 366                 };
 367
 368                 hsotg: hsotg@12480000 {
 369                         compatible = "samsung,s3c6400-hsotg";
 370                         reg = <0x12480000 0x20000>;
 371                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&cmu CLK_USBOTG>;
 373                         clock-names = "otg";
 374                         phys = <&exynos_usbphy 0>;
 375                         phy-names = "usb2-phy";
 376                         status = "disabled";
 377                 };
 378
 379                 mshc_0: mmc@12510000 {
 380                         compatible = "samsung,exynos5420-dw-mshc";
 381                         reg = <0x12510000 0x1000>;
 382                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 384                         clock-names = "biu", "ciu";
 385                         fifo-depth = <0x80>;
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         status = "disabled";
 389                 };
 390
 391                 mshc_1: mmc@12520000 {
 392                         compatible = "samsung,exynos5420-dw-mshc";
 393                         reg = <0x12520000 0x1000>;
 394                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 396                         clock-names = "biu", "ciu";
 397                         fifo-depth = <0x80>;
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         status = "disabled";
 401                 };
 402
 403                 mshc_2: mmc@12530000 {
 404                         compatible = "samsung,exynos5250-dw-mshc";
 405                         reg = <0x12530000 0x1000>;
 406                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 408                         clock-names = "biu", "ciu";
 409                         fifo-depth = <0x80>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         status = "disabled";
 413                 };
 414
 415                 exynos_usbphy: exynos-usbphy@125b0000 {
 416                         compatible = "samsung,exynos3250-usb2-phy";
 417                         reg = <0x125B0000 0x100>;
 418                         samsung,pmureg-phandle = <&pmu_system_controller>;
 419                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 420                         clock-names = "phy", "ref";
 421                         #phy-cells = <1>;
 422                         status = "disabled";
 423                 };
 424
 425                 pdma0: dma-controller@12680000 {
 426                         compatible = "arm,pl330", "arm,primecell";
 427                         reg = <0x12680000 0x1000>;
 428                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&cmu CLK_PDMA0>;
 430                         clock-names = "apb_pclk";
 431                         #dma-cells = <1>;
 432                 };
 433
 434                 pdma1: dma-controller@12690000 {
 435                         compatible = "arm,pl330", "arm,primecell";
 436                         reg = <0x12690000 0x1000>;
 437                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&cmu CLK_PDMA1>;
 439                         clock-names = "apb_pclk";
 440                         #dma-cells = <1>;
 441                 };
 442
 443                 adc: adc@126c0000 {
 444                         compatible = "samsung,exynos3250-adc";
 445                         reg = <0x126C0000 0x100>;
 446                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 447                         clock-names = "adc", "sclk";
 448                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 449                         #io-channel-cells = <1>;
 450                         samsung,syscon-phandle = <&pmu_system_controller>;
 451                         status = "disabled";
 452                 };
 453
 454                 gpu: gpu@13000000 {
 455                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
 456                         reg = <0x13000000 0x10000>;
 457                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 459                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 460                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 463                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 464                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 465                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 466                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 467                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 468                         interrupt-names = "gp",
 469                                           "gpmmu",
 470                                           "pp0",
 471                                           "ppmmu0",
 472                                           "pp1",
 473                                           "ppmmu1",
 474                                           "pp2",
 475                                           "ppmmu2",
 476                                           "pp3",
 477                                           "ppmmu3",
 478                                           "pmu";
 479                         clocks = <&cmu CLK_G3D>,
 480                                  <&cmu CLK_SCLK_G3D>;
 481                         clock-names = "bus", "core";
 482                         power-domains = <&pd_g3d>;
 483                         status = "disabled";
 484                         /* TODO: operating points for DVFS, assigned clock as 134 MHz */
 485                 };
 486
 487                 mfc: codec@13400000 {
 488                         compatible = "samsung,mfc-v7";
 489                         reg = <0x13400000 0x10000>;
 490                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 491                         clock-names = "mfc", "sclk_mfc";
 492                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 493                         power-domains = <&pd_mfc>;
 494                         iommus = <&sysmmu_mfc>;
 495                 };
 496
 497                 sysmmu_mfc: sysmmu@13620000 {
 498                         compatible = "samsung,exynos-sysmmu";
 499                         reg = <0x13620000 0x1000>;
 500                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 501                         clock-names = "sysmmu", "master";
 502                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 503                         power-domains = <&pd_mfc>;
 504                         #iommu-cells = <0>;
 505                 };
 506
 507                 serial_0: serial@13800000 {
 508                         compatible = "samsung,exynos4210-uart";
 509                         reg = <0x13800000 0x100>;
 510                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 512                         clock-names = "uart", "clk_uart_baud0";
 513                         pinctrl-names = "default";
 514                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 515                         status = "disabled";
 516                 };
 517
 518                 serial_1: serial@13810000 {
 519                         compatible = "samsung,exynos4210-uart";
 520                         reg = <0x13810000 0x100>;
 521                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 523                         clock-names = "uart", "clk_uart_baud0";
 524                         pinctrl-names = "default";
 525                         pinctrl-0 = <&uart1_data>;
 526                         status = "disabled";
 527                 };
 528
 529                 serial_2: serial@13820000 {
 530                         compatible = "samsung,exynos4210-uart";
 531                         reg = <0x13820000 0x100>;
 532                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 534                         clock-names = "uart", "clk_uart_baud0";
 535                         pinctrl-names = "default";
 536                         pinctrl-0 = <&uart2_data>;
 537                         status = "disabled";
 538                 };
 539
 540                 i2c_0: i2c@13860000 {
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         compatible = "samsung,s3c2440-i2c";
 544                         reg = <0x13860000 0x100>;
 545                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 546                         clocks = <&cmu CLK_I2C0>;
 547                         clock-names = "i2c";
 548                         pinctrl-names = "default";
 549                         pinctrl-0 = <&i2c0_bus>;
 550                         status = "disabled";
 551                 };
 552
 553                 i2c_1: i2c@13870000 {
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         compatible = "samsung,s3c2440-i2c";
 557                         reg = <0x13870000 0x100>;
 558                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 559                         clocks = <&cmu CLK_I2C1>;
 560                         clock-names = "i2c";
 561                         pinctrl-names = "default";
 562                         pinctrl-0 = <&i2c1_bus>;
 563                         status = "disabled";
 564                 };
 565
 566                 i2c_2: i2c@13880000 {
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         compatible = "samsung,s3c2440-i2c";
 570                         reg = <0x13880000 0x100>;
 571                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&cmu CLK_I2C2>;
 573                         clock-names = "i2c";
 574                         pinctrl-names = "default";
 575                         pinctrl-0 = <&i2c2_bus>;
 576                         status = "disabled";
 577                 };
 578
 579                 i2c_3: i2c@13890000 {
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         compatible = "samsung,s3c2440-i2c";
 583                         reg = <0x13890000 0x100>;
 584                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&cmu CLK_I2C3>;
 586                         clock-names = "i2c";
 587                         pinctrl-names = "default";
 588                         pinctrl-0 = <&i2c3_bus>;
 589                         status = "disabled";
 590                 };
 591
 592                 i2c_4: i2c@138a0000 {
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         compatible = "samsung,s3c2440-i2c";
 596                         reg = <0x138A0000 0x100>;
 597                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&cmu CLK_I2C4>;
 599                         clock-names = "i2c";
 600                         pinctrl-names = "default";
 601                         pinctrl-0 = <&i2c4_bus>;
 602                         status = "disabled";
 603                 };
 604
 605                 i2c_5: i2c@138b0000 {
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         compatible = "samsung,s3c2440-i2c";
 609                         reg = <0x138B0000 0x100>;
 610                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 611                         clocks = <&cmu CLK_I2C5>;
 612                         clock-names = "i2c";
 613                         pinctrl-names = "default";
 614                         pinctrl-0 = <&i2c5_bus>;
 615                         status = "disabled";
 616                 };
 617
 618                 i2c_6: i2c@138c0000 {
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         compatible = "samsung,s3c2440-i2c";
 622                         reg = <0x138C0000 0x100>;
 623                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 624                         clocks = <&cmu CLK_I2C6>;
 625                         clock-names = "i2c";
 626                         pinctrl-names = "default";
 627                         pinctrl-0 = <&i2c6_bus>;
 628                         status = "disabled";
 629                 };
 630
 631                 i2c_7: i2c@138d0000 {
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                         compatible = "samsung,s3c2440-i2c";
 635                         reg = <0x138D0000 0x100>;
 636                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 637                         clocks = <&cmu CLK_I2C7>;
 638                         clock-names = "i2c";
 639                         pinctrl-names = "default";
 640                         pinctrl-0 = <&i2c7_bus>;
 641                         status = "disabled";
 642                 };
 643
 644                 spi_0: spi@13920000 {
 645                         compatible = "samsung,exynos4210-spi";
 646                         reg = <0x13920000 0x100>;
 647                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 648                         dmas = <&pdma0 7>, <&pdma0 6>;
 649                         dma-names = "tx", "rx";
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 653                         clock-names = "spi", "spi_busclk0";
 654                         samsung,spi-src-clk = <0>;
 655                         pinctrl-names = "default";
 656                         pinctrl-0 = <&spi0_bus>;
 657                         status = "disabled";
 658                 };
 659
 660                 spi_1: spi@13930000 {
 661                         compatible = "samsung,exynos4210-spi";
 662                         reg = <0x13930000 0x100>;
 663                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 664                         dmas = <&pdma1 7>, <&pdma1 6>;
 665                         dma-names = "tx", "rx";
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 669                         clock-names = "spi", "spi_busclk0";
 670                         samsung,spi-src-clk = <0>;
 671                         pinctrl-names = "default";
 672                         pinctrl-0 = <&spi1_bus>;
 673                         status = "disabled";
 674                 };
 675
 676                 i2s2: i2s@13970000 {
 677                         compatible = "samsung,s3c6410-i2s";
 678                         reg = <0x13970000 0x100>;
 679                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 681                         clock-names = "iis", "i2s_opclk0";
 682                         dmas = <&pdma0 14>, <&pdma0 13>;
 683                         dma-names = "tx", "rx";
 684                         pinctrl-0 = <&i2s2_bus>;
 685                         pinctrl-names = "default";
 686                         status = "disabled";
 687                 };
 688
 689                 pwm: pwm@139d0000 {
 690                         compatible = "samsung,exynos4210-pwm";
 691                         reg = <0x139D0000 0x1000>;
 692                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 697                         #pwm-cells = <3>;
 698                         status = "disabled";
 699                 };
 700
 701                 ppmu_dmc0: ppmu@106a0000 {
 702                         compatible = "samsung,exynos-ppmu";
 703                         reg = <0x106a0000 0x2000>;
 704                         status = "disabled";
 705                 };
 706
 707                 ppmu_dmc1: ppmu@106b0000 {
 708                         compatible = "samsung,exynos-ppmu";
 709                         reg = <0x106b0000 0x2000>;
 710                         status = "disabled";
 711                 };
 712
 713                 ppmu_cpu: ppmu@106c0000 {
 714                         compatible = "samsung,exynos-ppmu";
 715                         reg = <0x106c0000 0x2000>;
 716                         status = "disabled";
 717                 };
 718
 719                 ppmu_rightbus: ppmu@112a0000 {
 720                         compatible = "samsung,exynos-ppmu";
 721                         reg = <0x112a0000 0x2000>;
 722                         clocks = <&cmu CLK_PPMURIGHT>;
 723                         clock-names = "ppmu";
 724                         status = "disabled";
 725                 };
 726
 727                 ppmu_leftbus: ppmu@116a0000 {
 728                         compatible = "samsung,exynos-ppmu";
 729                         reg = <0x116a0000 0x2000>;
 730                         clocks = <&cmu CLK_PPMULEFT>;
 731                         clock-names = "ppmu";
 732                         status = "disabled";
 733                 };
 734
 735                 ppmu_camif: ppmu@11ac0000 {
 736                         compatible = "samsung,exynos-ppmu";
 737                         reg = <0x11ac0000 0x2000>;
 738                         clocks = <&cmu CLK_PPMUCAMIF>;
 739                         clock-names = "ppmu";
 740                         status = "disabled";
 741                 };
 742
 743                 ppmu_lcd0: ppmu@11e40000 {
 744                         compatible = "samsung,exynos-ppmu";
 745                         reg = <0x11e40000 0x2000>;
 746                         clocks = <&cmu CLK_PPMULCD0>;
 747                         clock-names = "ppmu";
 748                         status = "disabled";
 749                 };
 750
 751                 ppmu_fsys: ppmu@12630000 {
 752                         compatible = "samsung,exynos-ppmu";
 753                         reg = <0x12630000 0x2000>;
 754                         clocks = <&cmu CLK_PPMUFILE>;
 755                         clock-names = "ppmu";
 756                         status = "disabled";
 757                 };
 758
 759                 ppmu_g3d: ppmu@13220000 {
 760                         compatible = "samsung,exynos-ppmu";
 761                         reg = <0x13220000 0x2000>;
 762                         clocks = <&cmu CLK_PPMUG3D>;
 763                         clock-names = "ppmu";
 764                         status = "disabled";
 765                 };
 766
 767                 ppmu_mfc: ppmu@13660000 {
 768                         compatible = "samsung,exynos-ppmu";
 769                         reg = <0x13660000 0x2000>;
 770                         clocks = <&cmu CLK_PPMUMFC_L>;
 771                         clock-names = "ppmu";
 772                         status = "disabled";
 773                 };
 774
 775                 bus_dmc: bus-dmc {
 776                         compatible = "samsung,exynos-bus";
 777                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 778                         clock-names = "bus";
 779                         operating-points-v2 = <&bus_dmc_opp_table>;
 780                         status = "disabled";
 781                 };
 782
 783                 bus_dmc_opp_table: opp-table1 {
 784                         compatible = "operating-points-v2";
 785
 786                         opp-50000000 {
 787                                 opp-hz = /bits/ 64 <50000000>;
 788                                 opp-microvolt = <800000>;
 789                         };
 790                         opp-100000000 {
 791                                 opp-hz = /bits/ 64 <100000000>;
 792                                 opp-microvolt = <800000>;
 793                         };
 794                         opp-134000000 {
 795                                 opp-hz = /bits/ 64 <134000000>;
 796                                 opp-microvolt = <800000>;
 797                         };
 798                         opp-200000000 {
 799                                 opp-hz = /bits/ 64 <200000000>;
 800                                 opp-microvolt = <825000>;
 801                         };
 802                         opp-400000000 {
 803                                 opp-hz = /bits/ 64 <400000000>;
 804                                 opp-microvolt = <875000>;
 805                         };
 806                 };
 807
 808                 bus_leftbus: bus-leftbus {
 809                         compatible = "samsung,exynos-bus";
 810                         clocks = <&cmu CLK_DIV_GDL>;
 811                         clock-names = "bus";
 812                         operating-points-v2 = <&bus_leftbus_opp_table>;
 813                         status = "disabled";
 814                 };
 815
 816                 bus_rightbus: bus-rightbus {
 817                         compatible = "samsung,exynos-bus";
 818                         clocks = <&cmu CLK_DIV_GDR>;
 819                         clock-names = "bus";
 820                         operating-points-v2 = <&bus_leftbus_opp_table>;
 821                         status = "disabled";
 822                 };
 823
 824                 bus_lcd0: bus-lcd0 {
 825                         compatible = "samsung,exynos-bus";
 826                         clocks = <&cmu CLK_DIV_ACLK_160>;
 827                         clock-names = "bus";
 828                         operating-points-v2 = <&bus_leftbus_opp_table>;
 829                         status = "disabled";
 830                 };
 831
 832                 bus_fsys: bus-fsys {
 833                         compatible = "samsung,exynos-bus";
 834                         clocks = <&cmu CLK_DIV_ACLK_200>;
 835                         clock-names = "bus";
 836                         operating-points-v2 = <&bus_leftbus_opp_table>;
 837                         status = "disabled";
 838                 };
 839
 840                 bus_mcuisp: bus-mcuisp {
 841                         compatible = "samsung,exynos-bus";
 842                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 843                         clock-names = "bus";
 844                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 845                         status = "disabled";
 846                 };
 847
 848                 bus_isp: bus-isp {
 849                         compatible = "samsung,exynos-bus";
 850                         clocks = <&cmu CLK_DIV_ACLK_266>;
 851                         clock-names = "bus";
 852                         operating-points-v2 = <&bus_isp_opp_table>;
 853                         status = "disabled";
 854                 };
 855
 856                 bus_peril: bus-peril {
 857                         compatible = "samsung,exynos-bus";
 858                         clocks = <&cmu CLK_DIV_ACLK_100>;
 859                         clock-names = "bus";
 860                         operating-points-v2 = <&bus_peril_opp_table>;
 861                         status = "disabled";
 862                 };
 863
 864                 bus_mfc: bus-mfc {
 865                         compatible = "samsung,exynos-bus";
 866                         clocks = <&cmu CLK_SCLK_MFC>;
 867                         clock-names = "bus";
 868                         operating-points-v2 = <&bus_leftbus_opp_table>;
 869                         status = "disabled";
 870                 };
 871
 872                 bus_leftbus_opp_table: opp-table2 {
 873                         compatible = "operating-points-v2";
 874
 875                         opp-50000000 {
 876                                 opp-hz = /bits/ 64 <50000000>;
 877                                 opp-microvolt = <900000>;
 878                         };
 879                         opp-80000000 {
 880                                 opp-hz = /bits/ 64 <80000000>;
 881                                 opp-microvolt = <900000>;
 882                         };
 883                         opp-100000000 {
 884                                 opp-hz = /bits/ 64 <100000000>;
 885                                 opp-microvolt = <1000000>;
 886                         };
 887                         opp-134000000 {
 888                                 opp-hz = /bits/ 64 <134000000>;
 889                                 opp-microvolt = <1000000>;
 890                         };
 891                         opp-200000000 {
 892                                 opp-hz = /bits/ 64 <200000000>;
 893                                 opp-microvolt = <1000000>;
 894                         };
 895                 };
 896
 897                 bus_mcuisp_opp_table: opp-table3 {
 898                         compatible = "operating-points-v2";
 899
 900                         opp-50000000 {
 901                                 opp-hz = /bits/ 64 <50000000>;
 902                         };
 903                         opp-80000000 {
 904                                 opp-hz = /bits/ 64 <80000000>;
 905                         };
 906                         opp-100000000 {
 907                                 opp-hz = /bits/ 64 <100000000>;
 908                         };
 909                         opp-200000000 {
 910                                 opp-hz = /bits/ 64 <200000000>;
 911                         };
 912                         opp-400000000 {
 913                                 opp-hz = /bits/ 64 <400000000>;
 914                         };
 915                 };
 916
 917                 bus_isp_opp_table: opp-table4 {
 918                         compatible = "operating-points-v2";
 919
 920                         opp-50000000 {
 921                                 opp-hz = /bits/ 64 <50000000>;
 922                         };
 923                         opp-80000000 {
 924                                 opp-hz = /bits/ 64 <80000000>;
 925                         };
 926                         opp-100000000 {
 927                                 opp-hz = /bits/ 64 <100000000>;
 928                         };
 929                         opp-200000000 {
 930                                 opp-hz = /bits/ 64 <200000000>;
 931                         };
 932                         opp-300000000 {
 933                                 opp-hz = /bits/ 64 <300000000>;
 934                         };
 935                 };
 936
 937                 bus_peril_opp_table: opp-table5 {
 938                         compatible = "operating-points-v2";
 939
 940                         opp-50000000 {
 941                                 opp-hz = /bits/ 64 <50000000>;
 942                         };
 943                         opp-80000000 {
 944                                 opp-hz = /bits/ 64 <80000000>;
 945                         };
 946                         opp-100000000 {
 947                                 opp-hz = /bits/ 64 <100000000>;
 948                         };
 949                 };
 950         };
 951 };
 952
 953 #include "exynos3250-pinctrl.dtsi"
 954 #include "exynos-syscon-restart.dtsi"