arch/arm/boot/dts/en7523.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/clock/en7523-clk.h>
   7
   8 / {
   9         interrupt-parent = <&gic>;
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12
  13         reserved-memory {
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges;
  17
  18                 npu_binary@84000000 {
  19                         no-map;
  20                         reg = <0x84000000 0xA00000>;
  21                 };
  22
  23                 npu_flag@84B0000 {
  24                         no-map;
  25                         reg = <0x84B00000 0x100000>;
  26                 };
  27
  28                 npu_pkt@85000000 {
  29                         no-map;
  30                         reg = <0x85000000 0x1A00000>;
  31                 };
  32
  33                 npu_phyaddr@86B00000 {
  34                         no-map;
  35                         reg = <0x86B00000 0x100000>;
  36                 };
  37
  38                 npu_rxdesc@86D00000 {
  39                         no-map;
  40                         reg = <0x86D00000 0x100000>;
  41                 };
  42         };
  43
  44         psci {
  45                 compatible = "arm,psci-0.2";
  46                 method = "smc";
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu-map {
  54                         cluster0 {
  55                                 core0 {
  56                                         cpu = <&cpu0>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu1>;
  60                                 };
  61                         };
  62                 };
  63
  64                 cpu0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x0>;
  68                         enable-method = "psci";
  69                         clock-frequency = <80000000>;
  70                         next-level-cache = <&L2_0>;
  71                 };
  72
  73                 cpu1: cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0x1>;
  77                         enable-method = "psci";
  78                         clock-frequency = <80000000>;
  79                         next-level-cache = <&L2_0>;
  80                 };
  81
  82                 L2_0: l2-cache0 {
  83                         compatible = "cache";
  84                 };
  85         };
  86
  87         scu: system-controller@1fa20000 {
  88                 compatible = "airoha,en7523-scu";
  89                 reg = <0x1fa20000 0x400>,
  90                       <0x1fb00000 0x1000>;
  91                 #clock-cells = <1>;
  92         };
  93
  94         gic: interrupt-controller@9000000 {
  95                 compatible = "arm,gic-v3";
  96                 interrupt-controller;
  97                 #interrupt-cells = <3>;
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 reg = <0x09000000 0x20000>,
 101                       <0x09080000 0x80000>,
 102                       <0x09400000 0x2000>,
 103                       <0x09500000 0x2000>,
 104                       <0x09600000 0x20000>;
 105                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 106         };
 107
 108         timer {
 109                 compatible = "arm,armv8-timer";
 110                 interrupt-parent = <&gic>;
 111                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 112                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 113                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 114                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 115         };
 116
 117         uart1: serial@1fbf0000 {
 118                 compatible = "ns16550";
 119                 reg = <0x1fbf0000 0x30>;
 120                 reg-io-width = <4>;
 121                 reg-shift = <2>;
 122                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 123                 clock-frequency = <1843200>;
 124                 status = "okay";
 125         };
 126
 127         gpio0: gpio@1fbf0200 {
 128                 compatible = "airoha,en7523-gpio";
 129                 reg = <0x1fbf0204 0x4>,
 130                       <0x1fbf0200 0x4>,
 131                       <0x1fbf0220 0x4>,
 132                       <0x1fbf0214 0x4>;
 133                 gpio-controller;
 134                 #gpio-cells = <2>;
 135         };
 136
 137         gpio1: gpio@1fbf0270 {
 138                 compatible = "airoha,en7523-gpio";
 139                 reg = <0x1fbf0270 0x4>,
 140                       <0x1fbf0260 0x4>,
 141                       <0x1fbf0264 0x4>,
 142                       <0x1fbf0278 0x4>;
 143                 gpio-controller;
 144                 #gpio-cells = <2>;
 145         };
 146
 147         pcie0: pcie@1fa91000 {
 148                 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
 149                 device_type = "pci";
 150                 reg = <0x1fa91000 0x1000>;
 151                 reg-names = "port0";
 152                 linux,pci-domain = <0>;
 153                 #address-cells = <3>;
 154                 #size-cells = <2>;
 155                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 156                 interrupt-names = "pcie_irq";
 157                 clocks = <&scu EN7523_CLK_PCIE>;
 158                 clock-names = "sys_ck0";
 159                 bus-range = <0x00 0xff>;
 160                 ranges = <0x82000000 0 0x20000000  0x20000000  0 0x8000000>;
 161                 status = "disabled";
 162
 163                 #interrupt-cells = <1>;
 164                 interrupt-map-mask = <0 0 0 7>;
 165                 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 166                                 <0 0 0 2 &pcie_intc0 1>,
 167                                 <0 0 0 3 &pcie_intc0 2>,
 168                                 <0 0 0 4 &pcie_intc0 3>;
 169                 pcie_intc0: interrupt-controller {
 170                         interrupt-controller;
 171                         #address-cells = <0>;
 172                         #interrupt-cells = <1>;
 173                 };
 174         };
 175
 176         pcie1: pcie@1fa92000 {
 177                 compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
 178                 device_type = "pci";
 179                 reg = <0x1fa92000 0x1000>;
 180                 reg-names = "port1";
 181                 linux,pci-domain = <1>;
 182                 #address-cells = <3>;
 183                 #size-cells = <2>;
 184                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 185                 interrupt-names = "pcie_irq";
 186                 clocks = <&scu EN7523_CLK_PCIE>;
 187                 clock-names = "sys_ck1";
 188                 bus-range = <0x00 0xff>;
 189                 ranges = <0x82000000 0 0x28000000  0x28000000  0 0x8000000>;
 190                 status = "disabled";
 191
 192                 #interrupt-cells = <1>;
 193                 interrupt-map-mask = <0 0 0 7>;
 194                 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 195                                 <0 0 0 2 &pcie_intc1 1>,
 196                                 <0 0 0 3 &pcie_intc1 2>,
 197                                 <0 0 0 4 &pcie_intc1 3>;
 198                 pcie_intc1: interrupt-controller {
 199                         interrupt-controller;
 200                         #address-cells = <0>;
 201                         #interrupt-cells = <1>;
 202                 };
 203         };
 204 };