GNU Linux-libre 4.19.264-gnu1
[releases.git] / arch / arm / boot / dts / emev2.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for the EMEV2 SoC
4  *
5  * Copyright (C) 2012 Renesas Solutions Corp.
6  */
7
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10
11 / {
12         compatible = "renesas,emev2";
13         interrupt-parent = <&gic>;
14         #address-cells = <1>;
15         #size-cells = <1>;
16
17         aliases {
18                 gpio0 = &gpio0;
19                 gpio1 = &gpio1;
20                 gpio2 = &gpio2;
21                 gpio3 = &gpio3;
22                 gpio4 = &gpio4;
23                 i2c0 = &iic0;
24                 i2c1 = &iic1;
25         };
26
27         cpus {
28                 #address-cells = <1>;
29                 #size-cells = <0>;
30
31                 cpu0: cpu@0 {
32                         device_type = "cpu";
33                         compatible = "arm,cortex-a9";
34                         reg = <0>;
35                         clock-frequency = <533000000>;
36                 };
37                 cpu1: cpu@1 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a9";
40                         reg = <1>;
41                         clock-frequency = <533000000>;
42                 };
43         };
44
45         gic: interrupt-controller@e0020000 {
46                 compatible = "arm,pl390";
47                 interrupt-controller;
48                 #interrupt-cells = <3>;
49                 reg = <0xe0028000 0x1000>,
50                       <0xe0020000 0x0100>;
51         };
52
53         pmu {
54                 compatible = "arm,cortex-a9-pmu";
55                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
56                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
57                 interrupt-affinity = <&cpu0>, <&cpu1>;
58         };
59
60         clocks@e0110000 {
61                 compatible = "renesas,emev2-smu";
62                 reg = <0xe0110000 0x10000>;
63                 #address-cells = <2>;
64                 #size-cells = <0>;
65
66                 c32ki: c32ki {
67                         compatible = "fixed-clock";
68                         clock-frequency = <32768>;
69                         #clock-cells = <0>;
70                 };
71                 iic0_sclkdiv: iic0_sclkdiv@624,0 {
72                         compatible = "renesas,emev2-smu-clkdiv";
73                         reg = <0x624 0>;
74                         clocks = <&pll3_fo>;
75                         #clock-cells = <0>;
76                 };
77                 iic0_sclk: iic0_sclk@48c,1 {
78                         compatible = "renesas,emev2-smu-gclk";
79                         reg = <0x48c 1>;
80                         clocks = <&iic0_sclkdiv>;
81                         #clock-cells = <0>;
82                 };
83                 iic1_sclkdiv: iic1_sclkdiv@624,16 {
84                         compatible = "renesas,emev2-smu-clkdiv";
85                         reg = <0x624 16>;
86                         clocks = <&pll3_fo>;
87                         #clock-cells = <0>;
88                 };
89                 iic1_sclk: iic1_sclk@490,1 {
90                         compatible = "renesas,emev2-smu-gclk";
91                         reg = <0x490 1>;
92                         clocks = <&iic1_sclkdiv>;
93                         #clock-cells = <0>;
94                 };
95                 pll3_fo: pll3_fo {
96                         compatible = "fixed-factor-clock";
97                         clocks = <&c32ki>;
98                         clock-div = <1>;
99                         clock-mult = <7000>;
100                         #clock-cells = <0>;
101                 };
102                 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
103                         compatible = "renesas,emev2-smu-clkdiv";
104                         reg = <0x610 0>;
105                         clocks = <&pll3_fo>;
106                         #clock-cells = <0>;
107                 };
108                 usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
109                         compatible = "renesas,emev2-smu-clkdiv";
110                         reg = <0x65c 0>;
111                         clocks = <&pll3_fo>;
112                         #clock-cells = <0>;
113                 };
114                 usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
115                         compatible = "renesas,emev2-smu-clkdiv";
116                         reg = <0x65c 16>;
117                         clocks = <&pll3_fo>;
118                         #clock-cells = <0>;
119                 };
120                 usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
121                         compatible = "renesas,emev2-smu-clkdiv";
122                         reg = <0x660 0>;
123                         clocks = <&pll3_fo>;
124                         #clock-cells = <0>;
125                 };
126                 usia_u0_sclk: usia_u0_sclk@4a0,1 {
127                         compatible = "renesas,emev2-smu-gclk";
128                         reg = <0x4a0 1>;
129                         clocks = <&usia_u0_sclkdiv>;
130                         #clock-cells = <0>;
131                 };
132                 usib_u1_sclk: usib_u1_sclk@4b8,1 {
133                         compatible = "renesas,emev2-smu-gclk";
134                         reg = <0x4b8 1>;
135                         clocks = <&usib_u1_sclkdiv>;
136                         #clock-cells = <0>;
137                 };
138                 usib_u2_sclk: usib_u2_sclk@4bc,1 {
139                         compatible = "renesas,emev2-smu-gclk";
140                         reg = <0x4bc 1>;
141                         clocks = <&usib_u2_sclkdiv>;
142                         #clock-cells = <0>;
143                 };
144                 usib_u3_sclk: usib_u3_sclk@4c0,1 {
145                         compatible = "renesas,emev2-smu-gclk";
146                         reg = <0x4c0 1>;
147                         clocks = <&usib_u3_sclkdiv>;
148                         #clock-cells = <0>;
149                 };
150                 sti_sclk: sti_sclk@528,1 {
151                         compatible = "renesas,emev2-smu-gclk";
152                         reg = <0x528 1>;
153                         clocks = <&c32ki>;
154                         #clock-cells = <0>;
155                 };
156         };
157
158         timer@e0180000 {
159                 compatible = "renesas,em-sti";
160                 reg = <0xe0180000 0x54>;
161                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
162                 clocks = <&sti_sclk>;
163                 clock-names = "sclk";
164         };
165
166         uart0: serial@e1020000 {
167                 compatible = "renesas,em-uart";
168                 reg = <0xe1020000 0x38>;
169                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
170                 clocks = <&usia_u0_sclk>;
171                 clock-names = "sclk";
172         };
173
174         uart1: serial@e1030000 {
175                 compatible = "renesas,em-uart";
176                 reg = <0xe1030000 0x38>;
177                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
178                 clocks = <&usib_u1_sclk>;
179                 clock-names = "sclk";
180         };
181
182         uart2: serial@e1040000 {
183                 compatible = "renesas,em-uart";
184                 reg = <0xe1040000 0x38>;
185                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
186                 clocks = <&usib_u2_sclk>;
187                 clock-names = "sclk";
188         };
189
190         uart3: serial@e1050000 {
191                 compatible = "renesas,em-uart";
192                 reg = <0xe1050000 0x38>;
193                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
194                 clocks = <&usib_u3_sclk>;
195                 clock-names = "sclk";
196         };
197
198         pfc: pin-controller@e0140200 {
199                 compatible = "renesas,pfc-emev2";
200                 reg = <0xe0140200 0x100>;
201         };
202
203         gpio0: gpio@e0050000 {
204                 compatible = "renesas,em-gio";
205                 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
206                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
207                              <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
208                 gpio-controller;
209                 gpio-ranges = <&pfc 0 0 32>;
210                 #gpio-cells = <2>;
211                 ngpios = <32>;
212                 interrupt-controller;
213                 #interrupt-cells = <2>;
214         };
215         gpio1: gpio@e0050080 {
216                 compatible = "renesas,em-gio";
217                 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
218                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
219                              <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
220                 gpio-controller;
221                 gpio-ranges = <&pfc 0 32 32>;
222                 #gpio-cells = <2>;
223                 ngpios = <32>;
224                 interrupt-controller;
225                 #interrupt-cells = <2>;
226         };
227         gpio2: gpio@e0050100 {
228                 compatible = "renesas,em-gio";
229                 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
230                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
231                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
232                 gpio-controller;
233                 gpio-ranges = <&pfc 0 64 32>;
234                 #gpio-cells = <2>;
235                 ngpios = <32>;
236                 interrupt-controller;
237                 #interrupt-cells = <2>;
238         };
239         gpio3: gpio@e0050180 {
240                 compatible = "renesas,em-gio";
241                 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
242                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
243                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
244                 gpio-controller;
245                 gpio-ranges = <&pfc 0 96 32>;
246                 #gpio-cells = <2>;
247                 ngpios = <32>;
248                 interrupt-controller;
249                 #interrupt-cells = <2>;
250         };
251         gpio4: gpio@e0050200 {
252                 compatible = "renesas,em-gio";
253                 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
254                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
255                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
256                 gpio-controller;
257                 gpio-ranges = <&pfc 0 128 31>;
258                 #gpio-cells = <2>;
259                 ngpios = <31>;
260                 interrupt-controller;
261                 #interrupt-cells = <2>;
262         };
263
264         iic0: i2c@e0070000 {
265                 #address-cells = <1>;
266                 #size-cells = <0>;
267                 compatible = "renesas,iic-emev2";
268                 reg = <0xe0070000 0x28>;
269                 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
270                 clocks = <&iic0_sclk>;
271                 clock-names = "sclk";
272                 status = "disabled";
273         };
274
275         iic1: i2c@e10a0000 {
276                 #address-cells = <1>;
277                 #size-cells = <0>;
278                 compatible = "renesas,iic-emev2";
279                 reg = <0xe10a0000 0x28>;
280                 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
281                 clocks = <&iic1_sclk>;
282                 clock-names = "sclk";
283                 status = "disabled";
284         };
285 };