2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
21 compatible = "ti,dra7xx";
22 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 #interrupt-cells = <3>;
71 reg = <0x48281000 0x1000>;
72 interrupt-parent = <&gic>;
76 * The soc node represents the soc top level view. It is used for IPs
77 * that are not memory mapped in the MPU view or for the MPU itself.
80 compatible = "ti,omap-infra";
82 compatible = "ti,omap5-mpu";
88 * XXX: Use a flat representation of the SOC interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since it will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
95 compatible = "ti,dra7-l3-noc", "simple-bus";
99 ti,hwmods = "l3_main_1", "l3_main_2";
100 reg = <0x44000000 0x1000000>,
102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
105 l4_cfg: l4@4a000000 {
106 compatible = "ti,dra7-l4-cfg", "simple-bus";
107 #address-cells = <1>;
109 ranges = <0 0x4a000000 0x22c000>;
112 compatible = "ti,dra7-scm-core", "simple-bus";
113 reg = <0x2000 0x2000>;
114 #address-cells = <1>;
116 ranges = <0 0x2000 0x2000>;
118 scm_conf: scm_conf@0 {
119 compatible = "syscon", "simple-bus";
121 #address-cells = <1>;
123 ranges = <0 0x0 0x1400>;
125 pbias_regulator: pbias_regulator {
126 compatible = "ti,pbias-dra7", "ti,pbias-omap";
128 syscon = <&scm_conf>;
129 pbias_mmc_reg: pbias_mmc_omap5 {
130 regulator-name = "pbias_mmc_omap5";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <3000000>;
136 scm_conf_clocks: clocks {
137 #address-cells = <1>;
142 dra7_pmx_core: pinmux@1400 {
143 compatible = "ti,dra7-padconf",
145 reg = <0x1400 0x0468>;
146 #address-cells = <1>;
148 #interrupt-cells = <1>;
149 interrupt-controller;
150 pinctrl-single,register-width = <32>;
151 pinctrl-single,function-mask = <0x3fffffff>;
154 scm_conf1: scm_conf@1c04 {
155 compatible = "syscon";
156 reg = <0x1c04 0x0020>;
160 cm_core_aon: cm_core_aon@5000 {
161 compatible = "ti,dra7-cm-core-aon";
162 reg = <0x5000 0x2000>;
164 cm_core_aon_clocks: clocks {
165 #address-cells = <1>;
169 cm_core_aon_clockdomains: clockdomains {
173 cm_core: cm_core@8000 {
174 compatible = "ti,dra7-cm-core";
175 reg = <0x8000 0x3000>;
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
182 cm_core_clockdomains: clockdomains {
187 l4_wkup: l4@4ae00000 {
188 compatible = "ti,dra7-l4-wkup", "simple-bus";
189 #address-cells = <1>;
191 ranges = <0 0x4ae00000 0x3f000>;
193 counter32k: counter@4000 {
194 compatible = "ti,omap-counter32k";
196 ti,hwmods = "counter_32k";
200 compatible = "ti,dra7-prm";
201 reg = <0x6000 0x3000>;
202 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
209 prm_clockdomains: clockdomains {
215 compatible = "simple-bus";
217 #address-cells = <1>;
218 ranges = <0x51000000 0x51000000 0x3000
219 0x0 0x20000000 0x10000000>;
220 pcie1: pcie@51000000 {
221 compatible = "ti,dra7-pcie";
222 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
223 reg-names = "rc_dbics", "ti_conf", "config";
224 interrupts = <0 232 0x4>, <0 233 0x4>;
225 #address-cells = <3>;
228 ranges = <0x81000000 0 0 0x03000 0 0x00010000
229 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
230 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
231 bus-range = <0x00 0xff>;
232 #interrupt-cells = <1>;
236 phy-names = "pcie-phy0";
237 interrupt-map-mask = <0 0 0 7>;
238 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
239 <0 0 0 2 &pcie1_intc 2>,
240 <0 0 0 3 &pcie1_intc 3>,
241 <0 0 0 4 &pcie1_intc 4>;
242 pcie1_intc: interrupt-controller {
243 interrupt-controller;
244 #address-cells = <0>;
245 #interrupt-cells = <1>;
251 compatible = "simple-bus";
253 #address-cells = <1>;
254 ranges = <0x51800000 0x51800000 0x3000
255 0x0 0x30000000 0x10000000>;
258 compatible = "ti,dra7-pcie";
259 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
260 reg-names = "rc_dbics", "ti_conf", "config";
261 interrupts = <0 355 0x4>, <0 356 0x4>;
262 #address-cells = <3>;
265 ranges = <0x81000000 0 0 0x03000 0 0x00010000
266 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
267 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
268 bus-range = <0x00 0xff>;
269 #interrupt-cells = <1>;
273 phy-names = "pcie-phy0";
274 interrupt-map-mask = <0 0 0 7>;
275 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
276 <0 0 0 2 &pcie2_intc 2>,
277 <0 0 0 3 &pcie2_intc 3>,
278 <0 0 0 4 &pcie2_intc 4>;
279 pcie2_intc: interrupt-controller {
280 interrupt-controller;
281 #address-cells = <0>;
282 #interrupt-cells = <1>;
287 bandgap: bandgap@4a0021e0 {
288 reg = <0x4a0021e0 0xc
294 compatible = "ti,dra752-bandgap";
295 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
296 #thermal-sensor-cells = <1>;
299 dsp1_system: dsp_system@40d00000 {
300 compatible = "syscon";
301 reg = <0x40d00000 0x100>;
304 sdma: dma-controller@4a056000 {
305 compatible = "ti,omap4430-sdma";
306 reg = <0x4a056000 0x1000>;
307 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
313 dma-requests = <127>;
316 sdma_xbar: dma-router@4a002b78 {
317 compatible = "ti,dra7-dma-crossbar";
318 reg = <0x4a002b78 0xfc>;
320 dma-requests = <205>;
321 ti,dma-safe-map = <0>;
322 dma-masters = <&sdma>;
325 gpio1: gpio@4ae10000 {
326 compatible = "ti,omap4-gpio";
327 reg = <0x4ae10000 0x200>;
328 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
336 gpio2: gpio@48055000 {
337 compatible = "ti,omap4-gpio";
338 reg = <0x48055000 0x200>;
339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
347 gpio3: gpio@48057000 {
348 compatible = "ti,omap4-gpio";
349 reg = <0x48057000 0x200>;
350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
358 gpio4: gpio@48059000 {
359 compatible = "ti,omap4-gpio";
360 reg = <0x48059000 0x200>;
361 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-controller;
366 #interrupt-cells = <2>;
369 gpio5: gpio@4805b000 {
370 compatible = "ti,omap4-gpio";
371 reg = <0x4805b000 0x200>;
372 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
380 gpio6: gpio@4805d000 {
381 compatible = "ti,omap4-gpio";
382 reg = <0x4805d000 0x200>;
383 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
391 gpio7: gpio@48051000 {
392 compatible = "ti,omap4-gpio";
393 reg = <0x48051000 0x200>;
394 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
402 gpio8: gpio@48053000 {
403 compatible = "ti,omap4-gpio";
404 reg = <0x48053000 0x200>;
405 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
413 uart1: serial@4806a000 {
414 compatible = "ti,dra742-uart", "ti,omap4-uart";
415 reg = <0x4806a000 0x100>;
416 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
418 clock-frequency = <48000000>;
420 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
421 dma-names = "tx", "rx";
424 uart2: serial@4806c000 {
425 compatible = "ti,dra742-uart", "ti,omap4-uart";
426 reg = <0x4806c000 0x100>;
427 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
429 clock-frequency = <48000000>;
431 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
432 dma-names = "tx", "rx";
435 uart3: serial@48020000 {
436 compatible = "ti,dra742-uart", "ti,omap4-uart";
437 reg = <0x48020000 0x100>;
438 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
440 clock-frequency = <48000000>;
442 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
443 dma-names = "tx", "rx";
446 uart4: serial@4806e000 {
447 compatible = "ti,dra742-uart", "ti,omap4-uart";
448 reg = <0x4806e000 0x100>;
449 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
451 clock-frequency = <48000000>;
453 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
454 dma-names = "tx", "rx";
457 uart5: serial@48066000 {
458 compatible = "ti,dra742-uart", "ti,omap4-uart";
459 reg = <0x48066000 0x100>;
460 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
462 clock-frequency = <48000000>;
464 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
465 dma-names = "tx", "rx";
468 uart6: serial@48068000 {
469 compatible = "ti,dra742-uart", "ti,omap4-uart";
470 reg = <0x48068000 0x100>;
471 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
473 clock-frequency = <48000000>;
475 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
476 dma-names = "tx", "rx";
479 uart7: serial@48420000 {
480 compatible = "ti,dra742-uart", "ti,omap4-uart";
481 reg = <0x48420000 0x100>;
482 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
484 clock-frequency = <48000000>;
488 uart8: serial@48422000 {
489 compatible = "ti,dra742-uart", "ti,omap4-uart";
490 reg = <0x48422000 0x100>;
491 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
493 clock-frequency = <48000000>;
497 uart9: serial@48424000 {
498 compatible = "ti,dra742-uart", "ti,omap4-uart";
499 reg = <0x48424000 0x100>;
500 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
502 clock-frequency = <48000000>;
506 uart10: serial@4ae2b000 {
507 compatible = "ti,dra742-uart", "ti,omap4-uart";
508 reg = <0x4ae2b000 0x100>;
509 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
510 ti,hwmods = "uart10";
511 clock-frequency = <48000000>;
515 mailbox1: mailbox@4a0f4000 {
516 compatible = "ti,omap4-mailbox";
517 reg = <0x4a0f4000 0x200>;
518 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
521 ti,hwmods = "mailbox1";
523 ti,mbox-num-users = <3>;
524 ti,mbox-num-fifos = <8>;
528 mailbox2: mailbox@4883a000 {
529 compatible = "ti,omap4-mailbox";
530 reg = <0x4883a000 0x200>;
531 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
535 ti,hwmods = "mailbox2";
537 ti,mbox-num-users = <4>;
538 ti,mbox-num-fifos = <12>;
542 mailbox3: mailbox@4883c000 {
543 compatible = "ti,omap4-mailbox";
544 reg = <0x4883c000 0x200>;
545 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
549 ti,hwmods = "mailbox3";
551 ti,mbox-num-users = <4>;
552 ti,mbox-num-fifos = <12>;
556 mailbox4: mailbox@4883e000 {
557 compatible = "ti,omap4-mailbox";
558 reg = <0x4883e000 0x200>;
559 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "mailbox4";
565 ti,mbox-num-users = <4>;
566 ti,mbox-num-fifos = <12>;
570 mailbox5: mailbox@48840000 {
571 compatible = "ti,omap4-mailbox";
572 reg = <0x48840000 0x200>;
573 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
577 ti,hwmods = "mailbox5";
579 ti,mbox-num-users = <4>;
580 ti,mbox-num-fifos = <12>;
584 mailbox6: mailbox@48842000 {
585 compatible = "ti,omap4-mailbox";
586 reg = <0x48842000 0x200>;
587 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
591 ti,hwmods = "mailbox6";
593 ti,mbox-num-users = <4>;
594 ti,mbox-num-fifos = <12>;
598 mailbox7: mailbox@48844000 {
599 compatible = "ti,omap4-mailbox";
600 reg = <0x48844000 0x200>;
601 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "mailbox7";
607 ti,mbox-num-users = <4>;
608 ti,mbox-num-fifos = <12>;
612 mailbox8: mailbox@48846000 {
613 compatible = "ti,omap4-mailbox";
614 reg = <0x48846000 0x200>;
615 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
619 ti,hwmods = "mailbox8";
621 ti,mbox-num-users = <4>;
622 ti,mbox-num-fifos = <12>;
626 mailbox9: mailbox@4885e000 {
627 compatible = "ti,omap4-mailbox";
628 reg = <0x4885e000 0x200>;
629 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
633 ti,hwmods = "mailbox9";
635 ti,mbox-num-users = <4>;
636 ti,mbox-num-fifos = <12>;
640 mailbox10: mailbox@48860000 {
641 compatible = "ti,omap4-mailbox";
642 reg = <0x48860000 0x200>;
643 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
647 ti,hwmods = "mailbox10";
649 ti,mbox-num-users = <4>;
650 ti,mbox-num-fifos = <12>;
654 mailbox11: mailbox@48862000 {
655 compatible = "ti,omap4-mailbox";
656 reg = <0x48862000 0x200>;
657 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
661 ti,hwmods = "mailbox11";
663 ti,mbox-num-users = <4>;
664 ti,mbox-num-fifos = <12>;
668 mailbox12: mailbox@48864000 {
669 compatible = "ti,omap4-mailbox";
670 reg = <0x48864000 0x200>;
671 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
675 ti,hwmods = "mailbox12";
677 ti,mbox-num-users = <4>;
678 ti,mbox-num-fifos = <12>;
682 mailbox13: mailbox@48802000 {
683 compatible = "ti,omap4-mailbox";
684 reg = <0x48802000 0x200>;
685 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
689 ti,hwmods = "mailbox13";
691 ti,mbox-num-users = <4>;
692 ti,mbox-num-fifos = <12>;
696 timer1: timer@4ae18000 {
697 compatible = "ti,omap5430-timer";
698 reg = <0x4ae18000 0x80>;
699 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
700 ti,hwmods = "timer1";
704 timer2: timer@48032000 {
705 compatible = "ti,omap5430-timer";
706 reg = <0x48032000 0x80>;
707 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
708 ti,hwmods = "timer2";
711 timer3: timer@48034000 {
712 compatible = "ti,omap5430-timer";
713 reg = <0x48034000 0x80>;
714 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
715 ti,hwmods = "timer3";
718 timer4: timer@48036000 {
719 compatible = "ti,omap5430-timer";
720 reg = <0x48036000 0x80>;
721 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
722 ti,hwmods = "timer4";
725 timer5: timer@48820000 {
726 compatible = "ti,omap5430-timer";
727 reg = <0x48820000 0x80>;
728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
729 ti,hwmods = "timer5";
732 timer6: timer@48822000 {
733 compatible = "ti,omap5430-timer";
734 reg = <0x48822000 0x80>;
735 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
736 ti,hwmods = "timer6";
739 timer7: timer@48824000 {
740 compatible = "ti,omap5430-timer";
741 reg = <0x48824000 0x80>;
742 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
743 ti,hwmods = "timer7";
746 timer8: timer@48826000 {
747 compatible = "ti,omap5430-timer";
748 reg = <0x48826000 0x80>;
749 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
750 ti,hwmods = "timer8";
753 timer9: timer@4803e000 {
754 compatible = "ti,omap5430-timer";
755 reg = <0x4803e000 0x80>;
756 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
757 ti,hwmods = "timer9";
760 timer10: timer@48086000 {
761 compatible = "ti,omap5430-timer";
762 reg = <0x48086000 0x80>;
763 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
764 ti,hwmods = "timer10";
767 timer11: timer@48088000 {
768 compatible = "ti,omap5430-timer";
769 reg = <0x48088000 0x80>;
770 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
771 ti,hwmods = "timer11";
774 timer13: timer@48828000 {
775 compatible = "ti,omap5430-timer";
776 reg = <0x48828000 0x80>;
777 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
778 ti,hwmods = "timer13";
782 timer14: timer@4882a000 {
783 compatible = "ti,omap5430-timer";
784 reg = <0x4882a000 0x80>;
785 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
786 ti,hwmods = "timer14";
790 timer15: timer@4882c000 {
791 compatible = "ti,omap5430-timer";
792 reg = <0x4882c000 0x80>;
793 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
794 ti,hwmods = "timer15";
798 timer16: timer@4882e000 {
799 compatible = "ti,omap5430-timer";
800 reg = <0x4882e000 0x80>;
801 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
802 ti,hwmods = "timer16";
807 compatible = "ti,omap3-wdt";
808 reg = <0x4ae14000 0x80>;
809 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
810 ti,hwmods = "wd_timer2";
813 hwspinlock: spinlock@4a0f6000 {
814 compatible = "ti,omap4-hwspinlock";
815 reg = <0x4a0f6000 0x1000>;
816 ti,hwmods = "spinlock";
821 compatible = "ti,omap5-dmm";
822 reg = <0x4e000000 0x800>;
823 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
828 compatible = "ti,omap4-i2c";
829 reg = <0x48070000 0x100>;
830 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
831 #address-cells = <1>;
838 compatible = "ti,omap4-i2c";
839 reg = <0x48072000 0x100>;
840 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
841 #address-cells = <1>;
848 compatible = "ti,omap4-i2c";
849 reg = <0x48060000 0x100>;
850 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
851 #address-cells = <1>;
858 compatible = "ti,omap4-i2c";
859 reg = <0x4807a000 0x100>;
860 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
861 #address-cells = <1>;
868 compatible = "ti,omap4-i2c";
869 reg = <0x4807c000 0x100>;
870 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
871 #address-cells = <1>;
878 compatible = "ti,omap4-hsmmc";
879 reg = <0x4809c000 0x400>;
880 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
883 ti,needs-special-reset;
884 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
885 dma-names = "tx", "rx";
887 pbias-supply = <&pbias_mmc_reg>;
891 compatible = "ti,omap4-hsmmc";
892 reg = <0x480b4000 0x400>;
893 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
895 ti,needs-special-reset;
896 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
897 dma-names = "tx", "rx";
902 compatible = "ti,omap4-hsmmc";
903 reg = <0x480ad000 0x400>;
904 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
906 ti,needs-special-reset;
907 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
908 dma-names = "tx", "rx";
913 compatible = "ti,omap4-hsmmc";
914 reg = <0x480d1000 0x400>;
915 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
917 ti,needs-special-reset;
918 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
919 dma-names = "tx", "rx";
923 mmu0_dsp1: mmu@40d01000 {
924 compatible = "ti,dra7-dsp-iommu";
925 reg = <0x40d01000 0x100>;
926 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
927 ti,hwmods = "mmu0_dsp1";
929 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
933 mmu1_dsp1: mmu@40d02000 {
934 compatible = "ti,dra7-dsp-iommu";
935 reg = <0x40d02000 0x100>;
936 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
937 ti,hwmods = "mmu1_dsp1";
939 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
943 mmu_ipu1: mmu@58882000 {
944 compatible = "ti,dra7-iommu";
945 reg = <0x58882000 0x100>;
946 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
947 ti,hwmods = "mmu_ipu1";
949 ti,iommu-bus-err-back;
953 mmu_ipu2: mmu@55082000 {
954 compatible = "ti,dra7-iommu";
955 reg = <0x55082000 0x100>;
956 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
957 ti,hwmods = "mmu_ipu2";
959 ti,iommu-bus-err-back;
963 abb_mpu: regulator-abb-mpu {
964 compatible = "ti,abb-v3";
965 regulator-name = "abb_mpu";
966 #address-cells = <0>;
968 clocks = <&sys_clkin1>;
969 ti,settling-time = <50>;
970 ti,clock-cycles = <16>;
972 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
973 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
975 reg-names = "setup-address", "control-address",
976 "int-address", "efuse-address",
978 ti,tranxdone-status-mask = <0x80>;
979 /* LDOVBBMPU_FBB_MUX_CTRL */
980 ti,ldovbb-override-mask = <0x400>;
981 /* LDOVBBMPU_FBB_VSET_OUT */
982 ti,ldovbb-vset-mask = <0x1F>;
985 * NOTE: only FBB mode used but actual vset will
986 * determine final biasing
989 /*uV ABB efuse rbb_m fbb_m vset_m*/
990 1060000 0 0x0 0 0x02000000 0x01F00000
991 1160000 0 0x4 0 0x02000000 0x01F00000
992 1210000 0 0x8 0 0x02000000 0x01F00000
996 abb_ivahd: regulator-abb-ivahd {
997 compatible = "ti,abb-v3";
998 regulator-name = "abb_ivahd";
999 #address-cells = <0>;
1001 clocks = <&sys_clkin1>;
1002 ti,settling-time = <50>;
1003 ti,clock-cycles = <16>;
1005 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1006 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1008 reg-names = "setup-address", "control-address",
1009 "int-address", "efuse-address",
1011 ti,tranxdone-status-mask = <0x40000000>;
1012 /* LDOVBBIVA_FBB_MUX_CTRL */
1013 ti,ldovbb-override-mask = <0x400>;
1014 /* LDOVBBIVA_FBB_VSET_OUT */
1015 ti,ldovbb-vset-mask = <0x1F>;
1018 * NOTE: only FBB mode used but actual vset will
1019 * determine final biasing
1022 /*uV ABB efuse rbb_m fbb_m vset_m*/
1023 1055000 0 0x0 0 0x02000000 0x01F00000
1024 1150000 0 0x4 0 0x02000000 0x01F00000
1025 1250000 0 0x8 0 0x02000000 0x01F00000
1029 abb_dspeve: regulator-abb-dspeve {
1030 compatible = "ti,abb-v3";
1031 regulator-name = "abb_dspeve";
1032 #address-cells = <0>;
1034 clocks = <&sys_clkin1>;
1035 ti,settling-time = <50>;
1036 ti,clock-cycles = <16>;
1038 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1039 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1041 reg-names = "setup-address", "control-address",
1042 "int-address", "efuse-address",
1044 ti,tranxdone-status-mask = <0x20000000>;
1045 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1046 ti,ldovbb-override-mask = <0x400>;
1047 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1048 ti,ldovbb-vset-mask = <0x1F>;
1051 * NOTE: only FBB mode used but actual vset will
1052 * determine final biasing
1055 /*uV ABB efuse rbb_m fbb_m vset_m*/
1056 1055000 0 0x0 0 0x02000000 0x01F00000
1057 1150000 0 0x4 0 0x02000000 0x01F00000
1058 1250000 0 0x8 0 0x02000000 0x01F00000
1062 abb_gpu: regulator-abb-gpu {
1063 compatible = "ti,abb-v3";
1064 regulator-name = "abb_gpu";
1065 #address-cells = <0>;
1067 clocks = <&sys_clkin1>;
1068 ti,settling-time = <50>;
1069 ti,clock-cycles = <16>;
1071 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1072 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1074 reg-names = "setup-address", "control-address",
1075 "int-address", "efuse-address",
1077 ti,tranxdone-status-mask = <0x10000000>;
1078 /* LDOVBBGPU_FBB_MUX_CTRL */
1079 ti,ldovbb-override-mask = <0x400>;
1080 /* LDOVBBGPU_FBB_VSET_OUT */
1081 ti,ldovbb-vset-mask = <0x1F>;
1084 * NOTE: only FBB mode used but actual vset will
1085 * determine final biasing
1088 /*uV ABB efuse rbb_m fbb_m vset_m*/
1089 1090000 0 0x0 0 0x02000000 0x01F00000
1090 1210000 0 0x4 0 0x02000000 0x01F00000
1091 1280000 0 0x8 0 0x02000000 0x01F00000
1095 mcspi1: spi@48098000 {
1096 compatible = "ti,omap4-mcspi";
1097 reg = <0x48098000 0x200>;
1098 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1099 #address-cells = <1>;
1101 ti,hwmods = "mcspi1";
1102 ti,spi-num-cs = <4>;
1103 dmas = <&sdma_xbar 35>,
1111 dma-names = "tx0", "rx0", "tx1", "rx1",
1112 "tx2", "rx2", "tx3", "rx3";
1113 status = "disabled";
1116 mcspi2: spi@4809a000 {
1117 compatible = "ti,omap4-mcspi";
1118 reg = <0x4809a000 0x200>;
1119 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1120 #address-cells = <1>;
1122 ti,hwmods = "mcspi2";
1123 ti,spi-num-cs = <2>;
1124 dmas = <&sdma_xbar 43>,
1128 dma-names = "tx0", "rx0", "tx1", "rx1";
1129 status = "disabled";
1132 mcspi3: spi@480b8000 {
1133 compatible = "ti,omap4-mcspi";
1134 reg = <0x480b8000 0x200>;
1135 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1136 #address-cells = <1>;
1138 ti,hwmods = "mcspi3";
1139 ti,spi-num-cs = <2>;
1140 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1141 dma-names = "tx0", "rx0";
1142 status = "disabled";
1145 mcspi4: spi@480ba000 {
1146 compatible = "ti,omap4-mcspi";
1147 reg = <0x480ba000 0x200>;
1148 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1149 #address-cells = <1>;
1151 ti,hwmods = "mcspi4";
1152 ti,spi-num-cs = <1>;
1153 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1154 dma-names = "tx0", "rx0";
1155 status = "disabled";
1158 qspi: qspi@4b300000 {
1159 compatible = "ti,dra7xxx-qspi";
1160 reg = <0x4b300000 0x100>;
1161 reg-names = "qspi_base";
1162 #address-cells = <1>;
1165 clocks = <&qspi_gfclk_div>;
1166 clock-names = "fck";
1168 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1169 status = "disabled";
1172 omap_control_sata: control-phy@4a002374 {
1173 compatible = "ti,control-phy-pipe3";
1174 reg = <0x4a002374 0x4>;
1175 reg-names = "power";
1176 clocks = <&sys_clkin1>;
1177 clock-names = "sysclk";
1182 compatible = "ti,omap-ocp2scp";
1183 #address-cells = <1>;
1186 reg = <0x4a090000 0x20>;
1187 ti,hwmods = "ocp2scp3";
1188 sata_phy: phy@4A096000 {
1189 compatible = "ti,phy-pipe3-sata";
1190 reg = <0x4A096000 0x80>, /* phy_rx */
1191 <0x4A096400 0x64>, /* phy_tx */
1192 <0x4A096800 0x40>; /* pll_ctrl */
1193 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1194 ctrl-module = <&omap_control_sata>;
1195 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1196 clock-names = "sysclk", "refclk";
1197 syscon-pllreset = <&scm_conf 0x3fc>;
1201 pcie1_phy: pciephy@4a094000 {
1202 compatible = "ti,phy-pipe3-pcie";
1203 reg = <0x4a094000 0x80>, /* phy_rx */
1204 <0x4a094400 0x64>; /* phy_tx */
1205 reg-names = "phy_rx", "phy_tx";
1206 ctrl-module = <&omap_control_pcie1phy>;
1207 clocks = <&dpll_pcie_ref_ck>,
1208 <&dpll_pcie_ref_m2ldo_ck>,
1209 <&optfclk_pciephy1_32khz>,
1210 <&optfclk_pciephy1_clk>,
1211 <&optfclk_pciephy1_div_clk>,
1212 <&optfclk_pciephy_div>;
1213 clock-names = "dpll_ref", "dpll_ref_m2",
1214 "wkupclk", "refclk",
1215 "div-clk", "phy-div";
1219 pcie2_phy: pciephy@4a095000 {
1220 compatible = "ti,phy-pipe3-pcie";
1221 reg = <0x4a095000 0x80>, /* phy_rx */
1222 <0x4a095400 0x64>; /* phy_tx */
1223 reg-names = "phy_rx", "phy_tx";
1224 ctrl-module = <&omap_control_pcie2phy>;
1225 clocks = <&dpll_pcie_ref_ck>,
1226 <&dpll_pcie_ref_m2ldo_ck>,
1227 <&optfclk_pciephy2_32khz>,
1228 <&optfclk_pciephy2_clk>,
1229 <&optfclk_pciephy2_div_clk>,
1230 <&optfclk_pciephy_div>;
1231 clock-names = "dpll_ref", "dpll_ref_m2",
1232 "wkupclk", "refclk",
1233 "div-clk", "phy-div";
1235 status = "disabled";
1239 sata: sata@4a141100 {
1240 compatible = "snps,dwc-ahci";
1241 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1242 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1244 phy-names = "sata-phy";
1245 clocks = <&sata_ref_clk>;
1249 omap_control_pcie1phy: control-phy@0x4a003c40 {
1250 compatible = "ti,control-phy-pcie";
1251 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1252 reg-names = "power", "control_sma", "pcie_pcs";
1253 clocks = <&sys_clkin1>;
1254 clock-names = "sysclk";
1257 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1258 compatible = "ti,control-phy-pcie";
1259 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1260 reg-names = "power", "control_sma", "pcie_pcs";
1261 clocks = <&sys_clkin1>;
1262 clock-names = "sysclk";
1263 status = "disabled";
1267 compatible = "ti,am3352-rtc";
1268 reg = <0x48838000 0x100>;
1269 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1271 ti,hwmods = "rtcss";
1272 clocks = <&sys_32k_ck>;
1275 omap_control_usb2phy1: control-phy@4a002300 {
1276 compatible = "ti,control-phy-usb2";
1277 reg = <0x4a002300 0x4>;
1278 reg-names = "power";
1281 omap_control_usb3phy1: control-phy@4a002370 {
1282 compatible = "ti,control-phy-pipe3";
1283 reg = <0x4a002370 0x4>;
1284 reg-names = "power";
1287 omap_control_usb2phy2: control-phy@0x4a002e74 {
1288 compatible = "ti,control-phy-usb2-dra7";
1289 reg = <0x4a002e74 0x4>;
1290 reg-names = "power";
1295 compatible = "ti,omap-ocp2scp";
1296 #address-cells = <1>;
1299 reg = <0x4a080000 0x20>;
1300 ti,hwmods = "ocp2scp1";
1302 usb2_phy1: phy@4a084000 {
1303 compatible = "ti,omap-usb2";
1304 reg = <0x4a084000 0x400>;
1305 ctrl-module = <&omap_control_usb2phy1>;
1306 clocks = <&usb_phy1_always_on_clk32k>,
1307 <&usb_otg_ss1_refclk960m>;
1308 clock-names = "wkupclk",
1313 usb2_phy2: phy@4a085000 {
1314 compatible = "ti,omap-usb2";
1315 reg = <0x4a085000 0x400>;
1316 ctrl-module = <&omap_control_usb2phy2>;
1317 clocks = <&usb_phy2_always_on_clk32k>,
1318 <&usb_otg_ss2_refclk960m>;
1319 clock-names = "wkupclk",
1324 usb3_phy1: phy@4a084400 {
1325 compatible = "ti,omap-usb3";
1326 reg = <0x4a084400 0x80>,
1329 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1330 ctrl-module = <&omap_control_usb3phy1>;
1331 clocks = <&usb_phy3_always_on_clk32k>,
1333 <&usb_otg_ss1_refclk960m>;
1334 clock-names = "wkupclk",
1341 omap_dwc3_1: omap_dwc3_1@48880000 {
1342 compatible = "ti,dwc3";
1343 ti,hwmods = "usb_otg_ss1";
1344 reg = <0x48880000 0x10000>;
1345 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1346 #address-cells = <1>;
1350 usb1: usb@48890000 {
1351 compatible = "snps,dwc3";
1352 reg = <0x48890000 0x17000>;
1353 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1356 interrupt-names = "peripheral",
1359 phys = <&usb2_phy1>, <&usb3_phy1>;
1360 phy-names = "usb2-phy", "usb3-phy";
1362 maximum-speed = "super-speed";
1364 snps,dis_u3_susphy_quirk;
1365 snps,dis_u2_susphy_quirk;
1369 omap_dwc3_2: omap_dwc3_2@488c0000 {
1370 compatible = "ti,dwc3";
1371 ti,hwmods = "usb_otg_ss2";
1372 reg = <0x488c0000 0x10000>;
1373 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1374 #address-cells = <1>;
1378 usb2: usb@488d0000 {
1379 compatible = "snps,dwc3";
1380 reg = <0x488d0000 0x17000>;
1381 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1384 interrupt-names = "peripheral",
1387 phys = <&usb2_phy2>;
1388 phy-names = "usb2-phy";
1390 maximum-speed = "high-speed";
1392 snps,dis_u3_susphy_quirk;
1393 snps,dis_u2_susphy_quirk;
1397 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1398 omap_dwc3_3: omap_dwc3_3@48900000 {
1399 compatible = "ti,dwc3";
1400 ti,hwmods = "usb_otg_ss3";
1401 reg = <0x48900000 0x10000>;
1402 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1403 #address-cells = <1>;
1407 status = "disabled";
1408 usb3: usb@48910000 {
1409 compatible = "snps,dwc3";
1410 reg = <0x48910000 0x17000>;
1411 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1414 interrupt-names = "peripheral",
1418 maximum-speed = "high-speed";
1420 snps,dis_u3_susphy_quirk;
1421 snps,dis_u2_susphy_quirk;
1426 compatible = "ti,am3352-elm";
1427 reg = <0x48078000 0xfc0>; /* device IO registers */
1428 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1430 status = "disabled";
1433 gpmc: gpmc@50000000 {
1434 compatible = "ti,am3352-gpmc";
1436 reg = <0x50000000 0x37c>; /* device IO registers */
1437 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1439 gpmc,num-waitpins = <2>;
1440 #address-cells = <2>;
1442 status = "disabled";
1446 compatible = "ti,dra7-atl";
1447 reg = <0x4843c000 0x3ff>;
1449 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1450 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1451 clocks = <&atl_gfclk_mux>;
1452 clock-names = "fck";
1453 status = "disabled";
1456 mcasp3: mcasp@48468000 {
1457 compatible = "ti,dra7-mcasp-audio";
1458 ti,hwmods = "mcasp3";
1459 reg = <0x48468000 0x2000>;
1461 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1463 interrupt-names = "tx", "rx";
1464 dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
1465 dma-names = "tx", "rx";
1466 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1467 clock-names = "fck", "ahclkx";
1468 status = "disabled";
1471 crossbar_mpu: crossbar@4a002a48 {
1472 compatible = "ti,irq-crossbar";
1473 reg = <0x4a002a48 0x130>;
1474 interrupt-controller;
1475 interrupt-parent = <&wakeupgen>;
1476 #interrupt-cells = <3>;
1477 ti,max-irqs = <160>;
1478 ti,max-crossbar-sources = <MAX_SOURCES>;
1480 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1481 ti,irqs-skip = <10 133 139 140>;
1482 ti,irqs-safe-map = <0>;
1485 mac: ethernet@48484000 {
1486 compatible = "ti,dra7-cpsw","ti,cpsw";
1488 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1489 clock-names = "fck", "cpts";
1490 cpdma_channels = <8>;
1491 ale_entries = <1024>;
1492 bd_ram_size = <0x2000>;
1495 mac_control = <0x20>;
1498 cpts_clock_mult = <0x80000000>;
1499 cpts_clock_shift = <29>;
1500 reg = <0x48484000 0x1000
1502 #address-cells = <1>;
1506 * Do not allow gating of cpsw clock as workaround
1507 * for errata i877. Keeping internal clock disabled
1508 * causes the device switching characteristics
1509 * to degrade over time and eventually fail to meet
1510 * the data manual delay time/skew specs.
1520 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1525 syscon = <&scm_conf>;
1526 status = "disabled";
1528 davinci_mdio: mdio@48485000 {
1529 compatible = "ti,davinci_mdio";
1530 #address-cells = <1>;
1532 ti,hwmods = "davinci_mdio";
1533 bus_freq = <1000000>;
1534 reg = <0x48485000 0x100>;
1537 cpsw_emac0: slave@48480200 {
1538 /* Filled in by U-Boot */
1539 mac-address = [ 00 00 00 00 00 00 ];
1542 cpsw_emac1: slave@48480300 {
1543 /* Filled in by U-Boot */
1544 mac-address = [ 00 00 00 00 00 00 ];
1547 phy_sel: cpsw-phy-sel@4a002554 {
1548 compatible = "ti,dra7xx-cpsw-phy-sel";
1549 reg= <0x4a002554 0x4>;
1550 reg-names = "gmii-sel";
1554 dcan1: can@4ae3c000 {
1555 compatible = "ti,dra7-d_can";
1556 ti,hwmods = "dcan1";
1557 reg = <0x4ae3c000 0x2000>;
1558 syscon-raminit = <&scm_conf 0x558 0>;
1559 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1560 clocks = <&dcan1_sys_clk_mux>;
1561 status = "disabled";
1564 dcan2: can@48480000 {
1565 compatible = "ti,dra7-d_can";
1566 ti,hwmods = "dcan2";
1567 reg = <0x48480000 0x2000>;
1568 syscon-raminit = <&scm_conf 0x558 1>;
1569 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1570 clocks = <&sys_clkin1>;
1571 status = "disabled";
1575 compatible = "ti,dra7-dss";
1576 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1577 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1578 status = "disabled";
1579 ti,hwmods = "dss_core";
1580 /* CTRL_CORE_DSS_PLL_CONTROL */
1581 syscon-pll-ctrl = <&scm_conf 0x538>;
1582 #address-cells = <1>;
1587 compatible = "ti,dra7-dispc";
1588 reg = <0x58001000 0x1000>;
1589 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1590 ti,hwmods = "dss_dispc";
1591 clocks = <&dss_dss_clk>;
1592 clock-names = "fck";
1593 /* CTRL_CORE_SMA_SW_1 */
1594 syscon-pol = <&scm_conf 0x534>;
1597 hdmi: encoder@58060000 {
1598 compatible = "ti,dra7-hdmi";
1599 reg = <0x58040000 0x200>,
1602 <0x58060000 0x19000>;
1603 reg-names = "wp", "pll", "phy", "core";
1604 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1605 status = "disabled";
1606 ti,hwmods = "dss_hdmi";
1607 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1608 clock-names = "fck", "sys_clk";
1613 thermal_zones: thermal-zones {
1614 #include "omap4-cpu-thermal.dtsi"
1615 #include "omap5-gpu-thermal.dtsi"
1616 #include "omap5-core-thermal.dtsi"
1622 polling-delay = <500>; /* milliseconds */
1625 /include/ "dra7xx-clocks.dtsi"