1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
14 #define MAX_SOURCES 400
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
48 compatible = "arm,armv7-timer";
49 status = "disabled"; /* See ARM architected timer wrap erratum i940 */
50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
54 interrupt-parent = <&gic>;
57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
60 #interrupt-cells = <3>;
61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
66 interrupt-parent = <&gic>;
69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
72 #interrupt-cells = <3>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
74 interrupt-parent = <&gic>;
83 compatible = "arm,cortex-a15";
86 operating-points-v2 = <&cpu0_opp_table>;
88 clocks = <&dpll_mpu_ck>;
91 clock-latency = <300000>; /* From omap-cpufreq driver */
94 #cooling-cells = <2>; /* min followed by max */
96 vbb-supply = <&abb_mpu>;
100 cpu0_opp_table: opp-table {
101 compatible = "operating-points-v2-ti-cpu";
102 syscon = <&scm_wkup>;
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
107 <1060000 850000 1150000>;
108 opp-supported-hw = <0xFF 0x01>;
113 opp-hz = /bits/ 64 <1176000000>;
114 opp-microvolt = <1160000 885000 1160000>,
115 <1160000 885000 1160000>;
117 opp-supported-hw = <0xFF 0x02>;
120 opp_high@1500000000 {
121 opp-hz = /bits/ 64 <1500000000>;
122 opp-microvolt = <1210000 950000 1250000>,
123 <1210000 950000 1250000>;
124 opp-supported-hw = <0xFF 0x04>;
129 * The soc node represents the soc top level view. It is used for IPs
130 * that are not memory mapped in the MPU view or for the MPU itself.
133 compatible = "ti,omap-infra";
135 compatible = "ti,omap5-mpu";
141 * XXX: Use a flat representation of the SOC interconnect.
142 * The real OMAP interconnect network is quite complex.
143 * Since it will not bring real advantage to represent that in DT for
144 * the moment, just use a fake OCP bus entry to represent the whole bus
148 compatible = "ti,dra7-l3-noc", "simple-bus";
149 #address-cells = <1>;
151 ranges = <0x0 0x0 0x0 0xc0000000>;
152 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
153 ti,hwmods = "l3_main_1", "l3_main_2";
154 reg = <0x0 0x44000000 0x0 0x1000000>,
155 <0x0 0x45000000 0x0 0x1000>;
156 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
157 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
159 l4_cfg: interconnect@4a000000 {
161 l4_wkup: interconnect@4ae00000 {
163 l4_per1: interconnect@48000000 {
165 l4_per2: interconnect@48400000 {
167 l4_per3: interconnect@48800000 {
171 compatible = "simple-bus";
173 #address-cells = <1>;
174 ranges = <0x51000000 0x51000000 0x3000
175 0x0 0x20000000 0x10000000>;
178 * To enable PCI endpoint mode, disable the pcie1_rc
179 * node and enable pcie1_ep mode.
181 pcie1_rc: pcie@51000000 {
182 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
183 reg-names = "rc_dbics", "ti_conf", "config";
184 interrupts = <0 232 0x4>, <0 233 0x4>;
185 #address-cells = <3>;
188 ranges = <0x81000000 0 0 0x03000 0 0x00010000
189 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
190 bus-range = <0x00 0xff>;
191 #interrupt-cells = <1>;
193 linux,pci-domain = <0>;
196 phy-names = "pcie-phy0";
197 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
198 interrupt-map-mask = <0 0 0 7>;
199 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
200 <0 0 0 2 &pcie1_intc 2>,
201 <0 0 0 3 &pcie1_intc 3>,
202 <0 0 0 4 &pcie1_intc 4>;
203 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
205 pcie1_intc: interrupt-controller {
206 interrupt-controller;
207 #address-cells = <0>;
208 #interrupt-cells = <1>;
212 pcie1_ep: pcie_ep@51000000 {
213 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
214 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
215 interrupts = <0 232 0x4>;
217 num-ib-windows = <4>;
218 num-ob-windows = <16>;
221 phy-names = "pcie-phy0";
222 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
223 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
229 compatible = "simple-bus";
231 #address-cells = <1>;
232 ranges = <0x51800000 0x51800000 0x3000
233 0x0 0x30000000 0x10000000>;
236 pcie2_rc: pcie@51800000 {
237 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
238 reg-names = "rc_dbics", "ti_conf", "config";
239 interrupts = <0 355 0x4>, <0 356 0x4>;
240 #address-cells = <3>;
243 ranges = <0x81000000 0 0 0x03000 0 0x00010000
244 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
245 bus-range = <0x00 0xff>;
246 #interrupt-cells = <1>;
248 linux,pci-domain = <1>;
251 phy-names = "pcie-phy0";
252 interrupt-map-mask = <0 0 0 7>;
253 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
254 <0 0 0 2 &pcie2_intc 2>,
255 <0 0 0 3 &pcie2_intc 3>,
256 <0 0 0 4 &pcie2_intc 4>;
257 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
258 pcie2_intc: interrupt-controller {
259 interrupt-controller;
260 #address-cells = <0>;
261 #interrupt-cells = <1>;
266 ocmcram1: ocmcram@40300000 {
267 compatible = "mmio-sram";
268 reg = <0x40300000 0x80000>;
269 ranges = <0x0 0x40300000 0x80000>;
270 #address-cells = <1>;
273 * This is a placeholder for an optional reserved
274 * region for use by secure software. The size
275 * of this region is not known until runtime so it
276 * is set as zero to either be updated to reserve
277 * space or left unchanged to leave all SRAM for use.
278 * On HS parts that that require the reserved region
279 * either the bootloader can update the size to
280 * the required amount or the node can be overridden
281 * from the board dts file for the secure platform.
284 compatible = "ti,secure-ram";
290 * NOTE: ocmcram2 and ocmcram3 are not available on all
291 * DRA7xx and AM57xx variants. Confirm availability in
292 * the data manual for the exact part number in use
293 * before enabling these nodes in the board dts file.
295 ocmcram2: ocmcram@40400000 {
297 compatible = "mmio-sram";
298 reg = <0x40400000 0x100000>;
299 ranges = <0x0 0x40400000 0x100000>;
300 #address-cells = <1>;
304 ocmcram3: ocmcram@40500000 {
306 compatible = "mmio-sram";
307 reg = <0x40500000 0x100000>;
308 ranges = <0x0 0x40500000 0x100000>;
309 #address-cells = <1>;
313 bandgap: bandgap@4a0021e0 {
314 reg = <0x4a0021e0 0xc
320 compatible = "ti,dra752-bandgap";
321 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
322 #thermal-sensor-cells = <1>;
325 dsp1_system: dsp_system@40d00000 {
326 compatible = "syscon";
327 reg = <0x40d00000 0x100>;
330 dra7_iodelay_core: padconf@4844a000 {
331 compatible = "ti,dra7-iodelay";
332 reg = <0x4844a000 0x0d1c>;
333 #address-cells = <1>;
335 #pinctrl-cells = <2>;
338 edma: edma@43300000 {
339 compatible = "ti,edma3-tpcc";
341 reg = <0x43300000 0x100000>;
342 reg-names = "edma3_cc";
343 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "edma3_ccint", "edma3_mperr",
351 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
354 * memcpy is disabled, can be enabled with:
355 * ti,edma-memcpy-channels = <20 21>;
356 * for example. Note that these channels need to be
357 * masked in the xbar as well.
361 edma_tptc0: tptc@43400000 {
362 compatible = "ti,edma3-tptc";
364 reg = <0x43400000 0x100000>;
365 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-names = "edma3_tcerrint";
369 edma_tptc1: tptc@43500000 {
370 compatible = "ti,edma3-tptc";
372 reg = <0x43500000 0x100000>;
373 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
374 interrupt-names = "edma3_tcerrint";
378 compatible = "ti,omap5-dmm";
379 reg = <0x4e000000 0x800>;
380 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
384 mmu0_dsp1: mmu@40d01000 {
385 compatible = "ti,dra7-dsp-iommu";
386 reg = <0x40d01000 0x100>;
387 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
388 ti,hwmods = "mmu0_dsp1";
390 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
394 mmu1_dsp1: mmu@40d02000 {
395 compatible = "ti,dra7-dsp-iommu";
396 reg = <0x40d02000 0x100>;
397 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
398 ti,hwmods = "mmu1_dsp1";
400 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
404 mmu_ipu1: mmu@58882000 {
405 compatible = "ti,dra7-iommu";
406 reg = <0x58882000 0x100>;
407 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
408 ti,hwmods = "mmu_ipu1";
410 ti,iommu-bus-err-back;
414 mmu_ipu2: mmu@55082000 {
415 compatible = "ti,dra7-iommu";
416 reg = <0x55082000 0x100>;
417 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
418 ti,hwmods = "mmu_ipu2";
420 ti,iommu-bus-err-back;
424 abb_mpu: regulator-abb-mpu {
425 compatible = "ti,abb-v3";
426 regulator-name = "abb_mpu";
427 #address-cells = <0>;
429 clocks = <&sys_clkin1>;
430 ti,settling-time = <50>;
431 ti,clock-cycles = <16>;
433 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
434 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
436 reg-names = "setup-address", "control-address",
437 "int-address", "efuse-address",
439 ti,tranxdone-status-mask = <0x80>;
440 /* LDOVBBMPU_FBB_MUX_CTRL */
441 ti,ldovbb-override-mask = <0x400>;
442 /* LDOVBBMPU_FBB_VSET_OUT */
443 ti,ldovbb-vset-mask = <0x1F>;
446 * NOTE: only FBB mode used but actual vset will
447 * determine final biasing
450 /*uV ABB efuse rbb_m fbb_m vset_m*/
451 1060000 0 0x0 0 0x02000000 0x01F00000
452 1160000 0 0x4 0 0x02000000 0x01F00000
453 1210000 0 0x8 0 0x02000000 0x01F00000
457 abb_ivahd: regulator-abb-ivahd {
458 compatible = "ti,abb-v3";
459 regulator-name = "abb_ivahd";
460 #address-cells = <0>;
462 clocks = <&sys_clkin1>;
463 ti,settling-time = <50>;
464 ti,clock-cycles = <16>;
466 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
467 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
469 reg-names = "setup-address", "control-address",
470 "int-address", "efuse-address",
472 ti,tranxdone-status-mask = <0x40000000>;
473 /* LDOVBBIVA_FBB_MUX_CTRL */
474 ti,ldovbb-override-mask = <0x400>;
475 /* LDOVBBIVA_FBB_VSET_OUT */
476 ti,ldovbb-vset-mask = <0x1F>;
479 * NOTE: only FBB mode used but actual vset will
480 * determine final biasing
483 /*uV ABB efuse rbb_m fbb_m vset_m*/
484 1055000 0 0x0 0 0x02000000 0x01F00000
485 1150000 0 0x4 0 0x02000000 0x01F00000
486 1250000 0 0x8 0 0x02000000 0x01F00000
490 abb_dspeve: regulator-abb-dspeve {
491 compatible = "ti,abb-v3";
492 regulator-name = "abb_dspeve";
493 #address-cells = <0>;
495 clocks = <&sys_clkin1>;
496 ti,settling-time = <50>;
497 ti,clock-cycles = <16>;
499 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
500 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
502 reg-names = "setup-address", "control-address",
503 "int-address", "efuse-address",
505 ti,tranxdone-status-mask = <0x20000000>;
506 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
507 ti,ldovbb-override-mask = <0x400>;
508 /* LDOVBBDSPEVE_FBB_VSET_OUT */
509 ti,ldovbb-vset-mask = <0x1F>;
512 * NOTE: only FBB mode used but actual vset will
513 * determine final biasing
516 /*uV ABB efuse rbb_m fbb_m vset_m*/
517 1055000 0 0x0 0 0x02000000 0x01F00000
518 1150000 0 0x4 0 0x02000000 0x01F00000
519 1250000 0 0x8 0 0x02000000 0x01F00000
523 abb_gpu: regulator-abb-gpu {
524 compatible = "ti,abb-v3";
525 regulator-name = "abb_gpu";
526 #address-cells = <0>;
528 clocks = <&sys_clkin1>;
529 ti,settling-time = <50>;
530 ti,clock-cycles = <16>;
532 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
533 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
535 reg-names = "setup-address", "control-address",
536 "int-address", "efuse-address",
538 ti,tranxdone-status-mask = <0x10000000>;
539 /* LDOVBBGPU_FBB_MUX_CTRL */
540 ti,ldovbb-override-mask = <0x400>;
541 /* LDOVBBGPU_FBB_VSET_OUT */
542 ti,ldovbb-vset-mask = <0x1F>;
545 * NOTE: only FBB mode used but actual vset will
546 * determine final biasing
549 /*uV ABB efuse rbb_m fbb_m vset_m*/
550 1090000 0 0x0 0 0x02000000 0x01F00000
551 1210000 0 0x4 0 0x02000000 0x01F00000
552 1280000 0 0x8 0 0x02000000 0x01F00000
557 compatible = "ti,dra7xxx-qspi";
558 reg = <0x4b300000 0x100>,
559 <0x5c000000 0x4000000>;
560 reg-names = "qspi_base", "qspi_mmap";
561 syscon-chipselects = <&scm_conf 0x558>;
562 #address-cells = <1>;
565 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
568 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
573 sata: sata@4a141100 {
574 compatible = "snps,dwc-ahci";
575 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
576 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
578 phy-names = "sata-phy";
579 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
581 ports-implemented = <0x1>;
585 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
586 gpmc: gpmc@50000000 {
587 compatible = "ti,am3352-gpmc";
589 reg = <0x50000000 0x37c>; /* device IO registers */
590 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
591 dmas = <&edma_xbar 4 0>;
594 gpmc,num-waitpins = <2>;
595 #address-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
604 crossbar_mpu: crossbar@4a002a48 {
605 compatible = "ti,irq-crossbar";
606 reg = <0x4a002a48 0x130>;
607 interrupt-controller;
608 interrupt-parent = <&wakeupgen>;
609 #interrupt-cells = <3>;
611 ti,max-crossbar-sources = <MAX_SOURCES>;
613 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
614 ti,irqs-skip = <10 133 139 140>;
615 ti,irqs-safe-map = <0>;
619 compatible = "ti,dra7-dss";
620 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
621 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
623 ti,hwmods = "dss_core";
624 /* CTRL_CORE_DSS_PLL_CONTROL */
625 syscon-pll-ctrl = <&scm_conf 0x538>;
626 #address-cells = <1>;
631 compatible = "ti,dra7-dispc";
632 reg = <0x58001000 0x1000>;
633 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
634 ti,hwmods = "dss_dispc";
635 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
637 /* CTRL_CORE_SMA_SW_1 */
638 syscon-pol = <&scm_conf 0x534>;
641 hdmi: encoder@58060000 {
642 compatible = "ti,dra7-hdmi";
643 reg = <0x58040000 0x200>,
646 <0x58060000 0x19000>;
647 reg-names = "wp", "pll", "phy", "core";
648 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
650 ti,hwmods = "dss_hdmi";
651 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
652 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
653 clock-names = "fck", "sys_clk";
654 dmas = <&sdma_xbar 76>;
655 dma-names = "audio_tx";
660 compatible = "ti,omap4-aes";
662 reg = <0x4b500000 0xa0>;
663 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
664 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
665 dma-names = "tx", "rx";
666 clocks = <&l3_iclk_div>;
671 compatible = "ti,omap4-aes";
673 reg = <0x4b700000 0xa0>;
674 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
675 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
676 dma-names = "tx", "rx";
677 clocks = <&l3_iclk_div>;
682 compatible = "ti,omap4-des";
684 reg = <0x480a5000 0xa0>;
685 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
686 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
687 dma-names = "tx", "rx";
688 clocks = <&l3_iclk_div>;
692 sham: sham@53100000 {
693 compatible = "ti,omap5-sham";
695 reg = <0x4b101000 0x300>;
696 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
697 dmas = <&edma_xbar 119 0>;
699 clocks = <&l3_iclk_div>;
703 opp_supply_mpu: opp-supply@4a003b20 {
704 compatible = "ti,omap5-opp-supply";
705 reg = <0x4a003b20 0xc>;
706 ti,efuse-settings = <
712 ti,absolute-max-voltage-uv = <1500000>;
717 thermal_zones: thermal-zones {
718 #include "omap4-cpu-thermal.dtsi"
719 #include "omap5-gpu-thermal.dtsi"
720 #include "omap5-core-thermal.dtsi"
721 #include "dra7-dspeve-thermal.dtsi"
722 #include "dra7-iva-thermal.dtsi"
728 polling-delay = <500>; /* milliseconds */
729 coefficients = <0 2000>;
733 coefficients = <0 2000>;
737 coefficients = <0 2000>;
741 coefficients = <0 2000>;
745 coefficients = <0 2000>;
749 temperature = <120000>; /* milli Celsius */
753 temperature = <120000>; /* milli Celsius */
757 temperature = <120000>; /* milli Celsius */
761 temperature = <120000>; /* milli Celsius */
765 temperature = <120000>; /* milli Celsius */
768 #include "dra7-l4.dtsi"
769 #include "dra7xx-clocks.dtsi"
771 /* Local timers, see ARM architected timer wrap erratum i940 */
776 assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
777 assigned-clock-parents = <&timer_sys_clk_div>;
785 assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
786 assigned-clock-parents = <&timer_sys_clk_div>;