2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/bus/ti-sysc.h>
11 #include <dt-bindings/clock/dra7.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/dra.h>
14 #include <dt-bindings/clock/dra7.h>
16 #define MAX_SOURCES 400
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&crossbar_mpu>;
42 ethernet0 = &cpsw_emac0;
43 ethernet1 = &cpsw_emac1;
50 compatible = "arm,armv7-timer";
51 status = "disabled"; /* See ARM architected timer wrap erratum i940 */
52 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
55 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
56 interrupt-parent = <&gic>;
59 gic: interrupt-controller@48211000 {
60 compatible = "arm,cortex-a15-gic";
62 #interrupt-cells = <3>;
63 reg = <0x0 0x48211000 0x0 0x1000>,
64 <0x0 0x48212000 0x0 0x2000>,
65 <0x0 0x48214000 0x0 0x2000>,
66 <0x0 0x48216000 0x0 0x2000>;
67 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
68 interrupt-parent = <&gic>;
71 wakeupgen: interrupt-controller@48281000 {
72 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
74 #interrupt-cells = <3>;
75 reg = <0x0 0x48281000 0x0 0x1000>;
76 interrupt-parent = <&gic>;
85 compatible = "arm,cortex-a15";
88 operating-points-v2 = <&cpu0_opp_table>;
90 clocks = <&dpll_mpu_ck>;
93 clock-latency = <300000>; /* From omap-cpufreq driver */
96 #cooling-cells = <2>; /* min followed by max */
98 vbb-supply = <&abb_mpu>;
102 cpu0_opp_table: opp-table {
103 compatible = "operating-points-v2-ti-cpu";
104 syscon = <&scm_wkup>;
107 opp-hz = /bits/ 64 <1000000000>;
108 opp-microvolt = <1060000 850000 1150000>,
109 <1060000 850000 1150000>;
110 opp-supported-hw = <0xFF 0x01>;
115 opp-hz = /bits/ 64 <1176000000>;
116 opp-microvolt = <1160000 885000 1160000>,
117 <1160000 885000 1160000>;
119 opp-supported-hw = <0xFF 0x02>;
122 opp_high@1500000000 {
123 opp-hz = /bits/ 64 <1500000000>;
124 opp-microvolt = <1210000 950000 1250000>,
125 <1210000 950000 1250000>;
126 opp-supported-hw = <0xFF 0x04>;
131 * The soc node represents the soc top level view. It is used for IPs
132 * that are not memory mapped in the MPU view or for the MPU itself.
135 compatible = "ti,omap-infra";
137 compatible = "ti,omap5-mpu";
143 * XXX: Use a flat representation of the SOC interconnect.
144 * The real OMAP interconnect network is quite complex.
145 * Since it will not bring real advantage to represent that in DT for
146 * the moment, just use a fake OCP bus entry to represent the whole bus
150 compatible = "ti,dra7-l3-noc", "simple-bus";
151 #address-cells = <1>;
153 ranges = <0x0 0x0 0x0 0xc0000000>;
154 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
155 ti,hwmods = "l3_main_1", "l3_main_2";
156 reg = <0x0 0x44000000 0x0 0x1000000>,
157 <0x0 0x45000000 0x0 0x1000>;
158 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
159 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
161 l4_cfg: l4@4a000000 {
162 compatible = "ti,dra7-l4-cfg", "simple-bus";
163 #address-cells = <1>;
165 ranges = <0 0x4a000000 0x22c000>;
168 compatible = "ti,dra7-scm-core", "simple-bus";
169 reg = <0x2000 0x2000>;
170 #address-cells = <1>;
172 ranges = <0 0x2000 0x2000>;
174 scm_conf: scm_conf@0 {
175 compatible = "syscon", "simple-bus";
177 #address-cells = <1>;
179 ranges = <0 0x0 0x1400>;
181 pbias_regulator: pbias_regulator@e00 {
182 compatible = "ti,pbias-dra7", "ti,pbias-omap";
184 syscon = <&scm_conf>;
185 pbias_mmc_reg: pbias_mmc_omap5 {
186 regulator-name = "pbias_mmc_omap5";
187 regulator-min-microvolt = <1800000>;
188 regulator-max-microvolt = <3300000>;
192 scm_conf_clocks: clocks {
193 #address-cells = <1>;
198 dra7_pmx_core: pinmux@1400 {
199 compatible = "ti,dra7-padconf",
201 reg = <0x1400 0x0468>;
202 #address-cells = <1>;
204 #pinctrl-cells = <1>;
205 #interrupt-cells = <1>;
206 interrupt-controller;
207 pinctrl-single,register-width = <32>;
208 pinctrl-single,function-mask = <0x3fffffff>;
211 scm_conf1: scm_conf@1c04 {
212 compatible = "syscon";
213 reg = <0x1c04 0x0020>;
217 scm_conf_pcie: scm_conf@1c24 {
218 compatible = "syscon";
219 reg = <0x1c24 0x0024>;
222 sdma_xbar: dma-router@b78 {
223 compatible = "ti,dra7-dma-crossbar";
226 dma-requests = <205>;
227 ti,dma-safe-map = <0>;
228 dma-masters = <&sdma>;
231 edma_xbar: dma-router@c78 {
232 compatible = "ti,dra7-dma-crossbar";
235 dma-requests = <204>;
236 ti,dma-safe-map = <0>;
237 dma-masters = <&edma>;
241 cm_core_aon: cm_core_aon@5000 {
242 compatible = "ti,dra7-cm-core-aon",
244 #address-cells = <1>;
246 reg = <0x5000 0x2000>;
247 ranges = <0 0x5000 0x2000>;
249 cm_core_aon_clocks: clocks {
250 #address-cells = <1>;
254 cm_core_aon_clockdomains: clockdomains {
258 cm_core: cm_core@8000 {
259 compatible = "ti,dra7-cm-core", "simple-bus";
260 #address-cells = <1>;
262 reg = <0x8000 0x3000>;
263 ranges = <0 0x8000 0x3000>;
265 cm_core_clocks: clocks {
266 #address-cells = <1>;
270 cm_core_clockdomains: clockdomains {
275 l4_wkup: l4@4ae00000 {
276 compatible = "ti,dra7-l4-wkup", "simple-bus";
277 #address-cells = <1>;
279 ranges = <0 0x4ae00000 0x3f000>;
281 counter32k: counter@4000 {
282 compatible = "ti,omap-counter32k";
284 ti,hwmods = "counter_32k";
288 compatible = "ti,dra7-prm", "simple-bus";
289 reg = <0x6000 0x3000>;
290 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
293 ranges = <0 0x6000 0x3000>;
296 #address-cells = <1>;
300 prm_clockdomains: clockdomains {
304 scm_wkup: scm_conf@c000 {
305 compatible = "syscon";
306 reg = <0xc000 0x1000>;
311 compatible = "simple-bus";
313 #address-cells = <1>;
314 ranges = <0x51000000 0x51000000 0x3000
315 0x0 0x20000000 0x10000000>;
318 * To enable PCI endpoint mode, disable the pcie1_rc
319 * node and enable pcie1_ep mode.
321 pcie1_rc: pcie@51000000 {
322 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
323 reg-names = "rc_dbics", "ti_conf", "config";
324 interrupts = <0 232 0x4>, <0 233 0x4>;
325 #address-cells = <3>;
328 ranges = <0x81000000 0 0 0x03000 0 0x00010000
329 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
330 bus-range = <0x00 0xff>;
331 #interrupt-cells = <1>;
333 linux,pci-domain = <0>;
336 phy-names = "pcie-phy0";
337 interrupt-map-mask = <0 0 0 7>;
338 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
339 <0 0 0 2 &pcie1_intc 2>,
340 <0 0 0 3 &pcie1_intc 3>,
341 <0 0 0 4 &pcie1_intc 4>;
342 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
344 pcie1_intc: interrupt-controller {
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <1>;
351 pcie1_ep: pcie_ep@51000000 {
352 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
353 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
354 interrupts = <0 232 0x4>;
356 num-ib-windows = <4>;
357 num-ob-windows = <16>;
360 phy-names = "pcie-phy0";
361 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
367 compatible = "simple-bus";
369 #address-cells = <1>;
370 ranges = <0x51800000 0x51800000 0x3000
371 0x0 0x30000000 0x10000000>;
374 pcie2_rc: pcie@51800000 {
375 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
376 reg-names = "rc_dbics", "ti_conf", "config";
377 interrupts = <0 355 0x4>, <0 356 0x4>;
378 #address-cells = <3>;
381 ranges = <0x81000000 0 0 0x03000 0 0x00010000
382 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
383 bus-range = <0x00 0xff>;
384 #interrupt-cells = <1>;
386 linux,pci-domain = <1>;
389 phy-names = "pcie-phy0";
390 interrupt-map-mask = <0 0 0 7>;
391 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
392 <0 0 0 2 &pcie2_intc 2>,
393 <0 0 0 3 &pcie2_intc 3>,
394 <0 0 0 4 &pcie2_intc 4>;
395 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
396 pcie2_intc: interrupt-controller {
397 interrupt-controller;
398 #address-cells = <0>;
399 #interrupt-cells = <1>;
404 ocmcram1: ocmcram@40300000 {
405 compatible = "mmio-sram";
406 reg = <0x40300000 0x80000>;
407 ranges = <0x0 0x40300000 0x80000>;
408 #address-cells = <1>;
411 * This is a placeholder for an optional reserved
412 * region for use by secure software. The size
413 * of this region is not known until runtime so it
414 * is set as zero to either be updated to reserve
415 * space or left unchanged to leave all SRAM for use.
416 * On HS parts that that require the reserved region
417 * either the bootloader can update the size to
418 * the required amount or the node can be overridden
419 * from the board dts file for the secure platform.
422 compatible = "ti,secure-ram";
428 * NOTE: ocmcram2 and ocmcram3 are not available on all
429 * DRA7xx and AM57xx variants. Confirm availability in
430 * the data manual for the exact part number in use
431 * before enabling these nodes in the board dts file.
433 ocmcram2: ocmcram@40400000 {
435 compatible = "mmio-sram";
436 reg = <0x40400000 0x100000>;
437 ranges = <0x0 0x40400000 0x100000>;
438 #address-cells = <1>;
442 ocmcram3: ocmcram@40500000 {
444 compatible = "mmio-sram";
445 reg = <0x40500000 0x100000>;
446 ranges = <0x0 0x40500000 0x100000>;
447 #address-cells = <1>;
451 bandgap: bandgap@4a0021e0 {
452 reg = <0x4a0021e0 0xc
458 compatible = "ti,dra752-bandgap";
459 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
460 #thermal-sensor-cells = <1>;
463 dsp1_system: dsp_system@40d00000 {
464 compatible = "syscon";
465 reg = <0x40d00000 0x100>;
468 dra7_iodelay_core: padconf@4844a000 {
469 compatible = "ti,dra7-iodelay";
470 reg = <0x4844a000 0x0d1c>;
471 #address-cells = <1>;
473 #pinctrl-cells = <2>;
476 sdma: dma-controller@4a056000 {
477 compatible = "ti,omap4430-sdma";
478 reg = <0x4a056000 0x1000>;
479 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
485 dma-requests = <127>;
486 ti,hwmods = "dma_system";
489 edma: edma@43300000 {
490 compatible = "ti,edma3-tpcc";
492 reg = <0x43300000 0x100000>;
493 reg-names = "edma3_cc";
494 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "edma3_ccint", "edma3_mperr",
502 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
505 * memcpy is disabled, can be enabled with:
506 * ti,edma-memcpy-channels = <20 21>;
507 * for example. Note that these channels need to be
508 * masked in the xbar as well.
512 edma_tptc0: tptc@43400000 {
513 compatible = "ti,edma3-tptc";
515 reg = <0x43400000 0x100000>;
516 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
517 interrupt-names = "edma3_tcerrint";
520 edma_tptc1: tptc@43500000 {
521 compatible = "ti,edma3-tptc";
523 reg = <0x43500000 0x100000>;
524 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
525 interrupt-names = "edma3_tcerrint";
528 gpio1: gpio@4ae10000 {
529 compatible = "ti,omap4-gpio";
530 reg = <0x4ae10000 0x200>;
531 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
539 gpio2: gpio@48055000 {
540 compatible = "ti,omap4-gpio";
541 reg = <0x48055000 0x200>;
542 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
550 gpio3: gpio@48057000 {
551 compatible = "ti,omap4-gpio";
552 reg = <0x48057000 0x200>;
553 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
561 gpio4: gpio@48059000 {
562 compatible = "ti,omap4-gpio";
563 reg = <0x48059000 0x200>;
564 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-controller;
569 #interrupt-cells = <2>;
572 gpio5: gpio@4805b000 {
573 compatible = "ti,omap4-gpio";
574 reg = <0x4805b000 0x200>;
575 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
583 gpio6: gpio@4805d000 {
584 compatible = "ti,omap4-gpio";
585 reg = <0x4805d000 0x200>;
586 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
590 interrupt-controller;
591 #interrupt-cells = <2>;
594 gpio7: gpio@48051000 {
595 compatible = "ti,omap4-gpio";
596 reg = <0x48051000 0x200>;
597 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
601 interrupt-controller;
602 #interrupt-cells = <2>;
605 gpio8: gpio@48053000 {
606 compatible = "ti,omap4-gpio";
607 reg = <0x48053000 0x200>;
608 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
616 uart1: serial@4806a000 {
617 compatible = "ti,dra742-uart", "ti,omap4-uart";
618 reg = <0x4806a000 0x100>;
619 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
621 clock-frequency = <48000000>;
623 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
624 dma-names = "tx", "rx";
627 uart2: serial@4806c000 {
628 compatible = "ti,dra742-uart", "ti,omap4-uart";
629 reg = <0x4806c000 0x100>;
630 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
632 clock-frequency = <48000000>;
634 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
635 dma-names = "tx", "rx";
638 uart3: serial@48020000 {
639 compatible = "ti,dra742-uart", "ti,omap4-uart";
640 reg = <0x48020000 0x100>;
641 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
643 clock-frequency = <48000000>;
645 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
646 dma-names = "tx", "rx";
649 uart4: serial@4806e000 {
650 compatible = "ti,dra742-uart", "ti,omap4-uart";
651 reg = <0x4806e000 0x100>;
652 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
654 clock-frequency = <48000000>;
656 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
657 dma-names = "tx", "rx";
660 uart5: serial@48066000 {
661 compatible = "ti,dra742-uart", "ti,omap4-uart";
662 reg = <0x48066000 0x100>;
663 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
665 clock-frequency = <48000000>;
667 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
668 dma-names = "tx", "rx";
671 uart6: serial@48068000 {
672 compatible = "ti,dra742-uart", "ti,omap4-uart";
673 reg = <0x48068000 0x100>;
674 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
676 clock-frequency = <48000000>;
678 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
679 dma-names = "tx", "rx";
682 uart7: serial@48420000 {
683 compatible = "ti,dra742-uart", "ti,omap4-uart";
684 reg = <0x48420000 0x100>;
685 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
687 clock-frequency = <48000000>;
691 uart8: serial@48422000 {
692 compatible = "ti,dra742-uart", "ti,omap4-uart";
693 reg = <0x48422000 0x100>;
694 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
696 clock-frequency = <48000000>;
700 uart9: serial@48424000 {
701 compatible = "ti,dra742-uart", "ti,omap4-uart";
702 reg = <0x48424000 0x100>;
703 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
705 clock-frequency = <48000000>;
709 uart10: serial@4ae2b000 {
710 compatible = "ti,dra742-uart", "ti,omap4-uart";
711 reg = <0x4ae2b000 0x100>;
712 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
713 ti,hwmods = "uart10";
714 clock-frequency = <48000000>;
718 mailbox1: mailbox@4a0f4000 {
719 compatible = "ti,omap4-mailbox";
720 reg = <0x4a0f4000 0x200>;
721 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
724 ti,hwmods = "mailbox1";
726 ti,mbox-num-users = <3>;
727 ti,mbox-num-fifos = <8>;
731 mailbox2: mailbox@4883a000 {
732 compatible = "ti,omap4-mailbox";
733 reg = <0x4883a000 0x200>;
734 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
738 ti,hwmods = "mailbox2";
740 ti,mbox-num-users = <4>;
741 ti,mbox-num-fifos = <12>;
745 mailbox3: mailbox@4883c000 {
746 compatible = "ti,omap4-mailbox";
747 reg = <0x4883c000 0x200>;
748 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "mailbox3";
754 ti,mbox-num-users = <4>;
755 ti,mbox-num-fifos = <12>;
759 mailbox4: mailbox@4883e000 {
760 compatible = "ti,omap4-mailbox";
761 reg = <0x4883e000 0x200>;
762 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
766 ti,hwmods = "mailbox4";
768 ti,mbox-num-users = <4>;
769 ti,mbox-num-fifos = <12>;
773 mailbox5: mailbox@48840000 {
774 compatible = "ti,omap4-mailbox";
775 reg = <0x48840000 0x200>;
776 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
780 ti,hwmods = "mailbox5";
782 ti,mbox-num-users = <4>;
783 ti,mbox-num-fifos = <12>;
787 mailbox6: mailbox@48842000 {
788 compatible = "ti,omap4-mailbox";
789 reg = <0x48842000 0x200>;
790 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
794 ti,hwmods = "mailbox6";
796 ti,mbox-num-users = <4>;
797 ti,mbox-num-fifos = <12>;
801 mailbox7: mailbox@48844000 {
802 compatible = "ti,omap4-mailbox";
803 reg = <0x48844000 0x200>;
804 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
808 ti,hwmods = "mailbox7";
810 ti,mbox-num-users = <4>;
811 ti,mbox-num-fifos = <12>;
815 mailbox8: mailbox@48846000 {
816 compatible = "ti,omap4-mailbox";
817 reg = <0x48846000 0x200>;
818 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
822 ti,hwmods = "mailbox8";
824 ti,mbox-num-users = <4>;
825 ti,mbox-num-fifos = <12>;
829 mailbox9: mailbox@4885e000 {
830 compatible = "ti,omap4-mailbox";
831 reg = <0x4885e000 0x200>;
832 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
836 ti,hwmods = "mailbox9";
838 ti,mbox-num-users = <4>;
839 ti,mbox-num-fifos = <12>;
843 mailbox10: mailbox@48860000 {
844 compatible = "ti,omap4-mailbox";
845 reg = <0x48860000 0x200>;
846 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
850 ti,hwmods = "mailbox10";
852 ti,mbox-num-users = <4>;
853 ti,mbox-num-fifos = <12>;
857 mailbox11: mailbox@48862000 {
858 compatible = "ti,omap4-mailbox";
859 reg = <0x48862000 0x200>;
860 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
861 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
862 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
864 ti,hwmods = "mailbox11";
866 ti,mbox-num-users = <4>;
867 ti,mbox-num-fifos = <12>;
871 mailbox12: mailbox@48864000 {
872 compatible = "ti,omap4-mailbox";
873 reg = <0x48864000 0x200>;
874 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
878 ti,hwmods = "mailbox12";
880 ti,mbox-num-users = <4>;
881 ti,mbox-num-fifos = <12>;
885 mailbox13: mailbox@48802000 {
886 compatible = "ti,omap4-mailbox";
887 reg = <0x48802000 0x200>;
888 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
892 ti,hwmods = "mailbox13";
894 ti,mbox-num-users = <4>;
895 ti,mbox-num-fifos = <12>;
899 timer1: timer@4ae18000 {
900 compatible = "ti,omap5430-timer";
901 reg = <0x4ae18000 0x80>;
902 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
903 ti,hwmods = "timer1";
906 clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
909 timer2: timer@48032000 {
910 compatible = "ti,omap5430-timer";
911 reg = <0x48032000 0x80>;
912 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
913 ti,hwmods = "timer2";
915 clocks = <&l4per_clkctrl DRA7_TIMER2_CLKCTRL 24>;
918 timer3: timer@48034000 {
919 compatible = "ti,omap5430-timer";
920 reg = <0x48034000 0x80>;
921 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
922 ti,hwmods = "timer3";
924 clocks = <&l4per_clkctrl DRA7_TIMER3_CLKCTRL 24>;
925 assigned-clocks = <&l4per_clkctrl DRA7_TIMER3_CLKCTRL 24>;
926 assigned-clock-parents = <&timer_sys_clk_div>;
929 timer4: timer@48036000 {
930 compatible = "ti,omap5430-timer";
931 reg = <0x48036000 0x80>;
932 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
933 ti,hwmods = "timer4";
935 clocks = <&l4per_clkctrl DRA7_TIMER4_CLKCTRL 24>;
936 assigned-clocks = <&l4per_clkctrl DRA7_TIMER4_CLKCTRL 24>;
937 assigned-clock-parents = <&timer_sys_clk_div>;
940 timer5: timer@48820000 {
941 compatible = "ti,omap5430-timer";
942 reg = <0x48820000 0x80>;
943 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
944 ti,hwmods = "timer5";
947 timer6: timer@48822000 {
948 compatible = "ti,omap5430-timer";
949 reg = <0x48822000 0x80>;
950 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
951 ti,hwmods = "timer6";
954 timer7: timer@48824000 {
955 compatible = "ti,omap5430-timer";
956 reg = <0x48824000 0x80>;
957 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
958 ti,hwmods = "timer7";
961 timer8: timer@48826000 {
962 compatible = "ti,omap5430-timer";
963 reg = <0x48826000 0x80>;
964 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
965 ti,hwmods = "timer8";
968 timer9: timer@4803e000 {
969 compatible = "ti,omap5430-timer";
970 reg = <0x4803e000 0x80>;
971 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
972 ti,hwmods = "timer9";
975 timer10: timer@48086000 {
976 compatible = "ti,omap5430-timer";
977 reg = <0x48086000 0x80>;
978 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
979 ti,hwmods = "timer10";
982 timer11: timer@48088000 {
983 compatible = "ti,omap5430-timer";
984 reg = <0x48088000 0x80>;
985 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
986 ti,hwmods = "timer11";
989 timer12: timer@4ae20000 {
990 compatible = "ti,omap5430-timer";
991 reg = <0x4ae20000 0x80>;
992 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
993 ti,hwmods = "timer12";
998 timer13: timer@48828000 {
999 compatible = "ti,omap5430-timer";
1000 reg = <0x48828000 0x80>;
1001 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
1002 ti,hwmods = "timer13";
1005 timer14: timer@4882a000 {
1006 compatible = "ti,omap5430-timer";
1007 reg = <0x4882a000 0x80>;
1008 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
1009 ti,hwmods = "timer14";
1012 timer15: timer@4882c000 {
1013 compatible = "ti,omap5430-timer";
1014 reg = <0x4882c000 0x80>;
1015 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1016 ti,hwmods = "timer15";
1019 timer16: timer@4882e000 {
1020 compatible = "ti,omap5430-timer";
1021 reg = <0x4882e000 0x80>;
1022 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
1023 ti,hwmods = "timer16";
1026 wdt2: wdt@4ae14000 {
1027 compatible = "ti,omap3-wdt";
1028 reg = <0x4ae14000 0x80>;
1029 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1030 ti,hwmods = "wd_timer2";
1033 hwspinlock: spinlock@4a0f6000 {
1034 compatible = "ti,omap4-hwspinlock";
1035 reg = <0x4a0f6000 0x1000>;
1036 ti,hwmods = "spinlock";
1037 #hwlock-cells = <1>;
1041 compatible = "ti,omap5-dmm";
1042 reg = <0x4e000000 0x800>;
1043 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1047 i2c1: i2c@48070000 {
1048 compatible = "ti,omap4-i2c";
1049 reg = <0x48070000 0x100>;
1050 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1051 #address-cells = <1>;
1054 status = "disabled";
1057 i2c2: i2c@48072000 {
1058 compatible = "ti,omap4-i2c";
1059 reg = <0x48072000 0x100>;
1060 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1061 #address-cells = <1>;
1064 status = "disabled";
1067 i2c3: i2c@48060000 {
1068 compatible = "ti,omap4-i2c";
1069 reg = <0x48060000 0x100>;
1070 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1071 #address-cells = <1>;
1074 status = "disabled";
1077 i2c4: i2c@4807a000 {
1078 compatible = "ti,omap4-i2c";
1079 reg = <0x4807a000 0x100>;
1080 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1081 #address-cells = <1>;
1084 status = "disabled";
1087 i2c5: i2c@4807c000 {
1088 compatible = "ti,omap4-i2c";
1089 reg = <0x4807c000 0x100>;
1090 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1091 #address-cells = <1>;
1094 status = "disabled";
1097 mmc1: mmc@4809c000 {
1098 compatible = "ti,dra7-sdhci";
1099 reg = <0x4809c000 0x400>;
1100 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1102 status = "disabled";
1103 pbias-supply = <&pbias_mmc_reg>;
1104 max-frequency = <192000000>;
1109 hdqw1w: 1w@480b2000 {
1110 compatible = "ti,omap3-1w";
1111 reg = <0x480b2000 0x1000>;
1112 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1113 ti,hwmods = "hdq1w";
1116 mmc2: mmc@480b4000 {
1117 compatible = "ti,dra7-sdhci";
1118 reg = <0x480b4000 0x400>;
1119 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1121 status = "disabled";
1122 max-frequency = <192000000>;
1123 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
1124 sdhci-caps-mask = <0x7 0x0>;
1130 mmc3: mmc@480ad000 {
1131 compatible = "ti,dra7-sdhci";
1132 reg = <0x480ad000 0x400>;
1133 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1135 status = "disabled";
1136 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1137 max-frequency = <64000000>;
1138 /* SDMA is not supported */
1139 sdhci-caps-mask = <0x0 0x400000>;
1142 mmc4: mmc@480d1000 {
1143 compatible = "ti,dra7-sdhci";
1144 reg = <0x480d1000 0x400>;
1145 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1147 status = "disabled";
1148 max-frequency = <192000000>;
1149 /* SDMA is not supported */
1150 sdhci-caps-mask = <0x0 0x400000>;
1153 mmu0_dsp1: mmu@40d01000 {
1154 compatible = "ti,dra7-dsp-iommu";
1155 reg = <0x40d01000 0x100>;
1156 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1157 ti,hwmods = "mmu0_dsp1";
1159 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1160 status = "disabled";
1163 mmu1_dsp1: mmu@40d02000 {
1164 compatible = "ti,dra7-dsp-iommu";
1165 reg = <0x40d02000 0x100>;
1166 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1167 ti,hwmods = "mmu1_dsp1";
1169 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1170 status = "disabled";
1173 mmu_ipu1: mmu@58882000 {
1174 compatible = "ti,dra7-iommu";
1175 reg = <0x58882000 0x100>;
1176 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1177 ti,hwmods = "mmu_ipu1";
1179 ti,iommu-bus-err-back;
1180 status = "disabled";
1183 mmu_ipu2: mmu@55082000 {
1184 compatible = "ti,dra7-iommu";
1185 reg = <0x55082000 0x100>;
1186 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1187 ti,hwmods = "mmu_ipu2";
1189 ti,iommu-bus-err-back;
1190 status = "disabled";
1193 abb_mpu: regulator-abb-mpu {
1194 compatible = "ti,abb-v3";
1195 regulator-name = "abb_mpu";
1196 #address-cells = <0>;
1198 clocks = <&sys_clkin1>;
1199 ti,settling-time = <50>;
1200 ti,clock-cycles = <16>;
1202 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1203 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1205 reg-names = "setup-address", "control-address",
1206 "int-address", "efuse-address",
1208 ti,tranxdone-status-mask = <0x80>;
1209 /* LDOVBBMPU_FBB_MUX_CTRL */
1210 ti,ldovbb-override-mask = <0x400>;
1211 /* LDOVBBMPU_FBB_VSET_OUT */
1212 ti,ldovbb-vset-mask = <0x1F>;
1215 * NOTE: only FBB mode used but actual vset will
1216 * determine final biasing
1219 /*uV ABB efuse rbb_m fbb_m vset_m*/
1220 1060000 0 0x0 0 0x02000000 0x01F00000
1221 1160000 0 0x4 0 0x02000000 0x01F00000
1222 1210000 0 0x8 0 0x02000000 0x01F00000
1226 abb_ivahd: regulator-abb-ivahd {
1227 compatible = "ti,abb-v3";
1228 regulator-name = "abb_ivahd";
1229 #address-cells = <0>;
1231 clocks = <&sys_clkin1>;
1232 ti,settling-time = <50>;
1233 ti,clock-cycles = <16>;
1235 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1236 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1238 reg-names = "setup-address", "control-address",
1239 "int-address", "efuse-address",
1241 ti,tranxdone-status-mask = <0x40000000>;
1242 /* LDOVBBIVA_FBB_MUX_CTRL */
1243 ti,ldovbb-override-mask = <0x400>;
1244 /* LDOVBBIVA_FBB_VSET_OUT */
1245 ti,ldovbb-vset-mask = <0x1F>;
1248 * NOTE: only FBB mode used but actual vset will
1249 * determine final biasing
1252 /*uV ABB efuse rbb_m fbb_m vset_m*/
1253 1055000 0 0x0 0 0x02000000 0x01F00000
1254 1150000 0 0x4 0 0x02000000 0x01F00000
1255 1250000 0 0x8 0 0x02000000 0x01F00000
1259 abb_dspeve: regulator-abb-dspeve {
1260 compatible = "ti,abb-v3";
1261 regulator-name = "abb_dspeve";
1262 #address-cells = <0>;
1264 clocks = <&sys_clkin1>;
1265 ti,settling-time = <50>;
1266 ti,clock-cycles = <16>;
1268 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1269 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1271 reg-names = "setup-address", "control-address",
1272 "int-address", "efuse-address",
1274 ti,tranxdone-status-mask = <0x20000000>;
1275 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1276 ti,ldovbb-override-mask = <0x400>;
1277 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1278 ti,ldovbb-vset-mask = <0x1F>;
1281 * NOTE: only FBB mode used but actual vset will
1282 * determine final biasing
1285 /*uV ABB efuse rbb_m fbb_m vset_m*/
1286 1055000 0 0x0 0 0x02000000 0x01F00000
1287 1150000 0 0x4 0 0x02000000 0x01F00000
1288 1250000 0 0x8 0 0x02000000 0x01F00000
1292 abb_gpu: regulator-abb-gpu {
1293 compatible = "ti,abb-v3";
1294 regulator-name = "abb_gpu";
1295 #address-cells = <0>;
1297 clocks = <&sys_clkin1>;
1298 ti,settling-time = <50>;
1299 ti,clock-cycles = <16>;
1301 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1302 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1304 reg-names = "setup-address", "control-address",
1305 "int-address", "efuse-address",
1307 ti,tranxdone-status-mask = <0x10000000>;
1308 /* LDOVBBGPU_FBB_MUX_CTRL */
1309 ti,ldovbb-override-mask = <0x400>;
1310 /* LDOVBBGPU_FBB_VSET_OUT */
1311 ti,ldovbb-vset-mask = <0x1F>;
1314 * NOTE: only FBB mode used but actual vset will
1315 * determine final biasing
1318 /*uV ABB efuse rbb_m fbb_m vset_m*/
1319 1090000 0 0x0 0 0x02000000 0x01F00000
1320 1210000 0 0x4 0 0x02000000 0x01F00000
1321 1280000 0 0x8 0 0x02000000 0x01F00000
1325 mcspi1: spi@48098000 {
1326 compatible = "ti,omap4-mcspi";
1327 reg = <0x48098000 0x200>;
1328 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1329 #address-cells = <1>;
1331 ti,hwmods = "mcspi1";
1332 ti,spi-num-cs = <4>;
1333 dmas = <&sdma_xbar 35>,
1341 dma-names = "tx0", "rx0", "tx1", "rx1",
1342 "tx2", "rx2", "tx3", "rx3";
1343 status = "disabled";
1346 mcspi2: spi@4809a000 {
1347 compatible = "ti,omap4-mcspi";
1348 reg = <0x4809a000 0x200>;
1349 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1350 #address-cells = <1>;
1352 ti,hwmods = "mcspi2";
1353 ti,spi-num-cs = <2>;
1354 dmas = <&sdma_xbar 43>,
1358 dma-names = "tx0", "rx0", "tx1", "rx1";
1359 status = "disabled";
1362 mcspi3: spi@480b8000 {
1363 compatible = "ti,omap4-mcspi";
1364 reg = <0x480b8000 0x200>;
1365 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1366 #address-cells = <1>;
1368 ti,hwmods = "mcspi3";
1369 ti,spi-num-cs = <2>;
1370 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1371 dma-names = "tx0", "rx0";
1372 status = "disabled";
1375 mcspi4: spi@480ba000 {
1376 compatible = "ti,omap4-mcspi";
1377 reg = <0x480ba000 0x200>;
1378 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1379 #address-cells = <1>;
1381 ti,hwmods = "mcspi4";
1382 ti,spi-num-cs = <1>;
1383 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1384 dma-names = "tx0", "rx0";
1385 status = "disabled";
1388 qspi: spi@4b300000 {
1389 compatible = "ti,dra7xxx-qspi";
1390 reg = <0x4b300000 0x100>,
1391 <0x5c000000 0x4000000>;
1392 reg-names = "qspi_base", "qspi_mmap";
1393 syscon-chipselects = <&scm_conf 0x558>;
1394 #address-cells = <1>;
1397 clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
1398 clock-names = "fck";
1400 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1401 status = "disabled";
1406 compatible = "ti,omap-ocp2scp";
1407 #address-cells = <1>;
1410 reg = <0x4a090000 0x20>;
1411 ti,hwmods = "ocp2scp3";
1412 sata_phy: phy@4a096000 {
1413 compatible = "ti,phy-pipe3-sata";
1414 reg = <0x4A096000 0x80>, /* phy_rx */
1415 <0x4A096400 0x64>, /* phy_tx */
1416 <0x4A096800 0x40>; /* pll_ctrl */
1417 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1418 syscon-phy-power = <&scm_conf 0x374>;
1419 clocks = <&sys_clkin1>,
1420 <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1421 clock-names = "sysclk", "refclk";
1422 syscon-pllreset = <&scm_conf 0x3fc>;
1426 pcie1_phy: pciephy@4a094000 {
1427 compatible = "ti,phy-pipe3-pcie";
1428 reg = <0x4a094000 0x80>, /* phy_rx */
1429 <0x4a094400 0x64>; /* phy_tx */
1430 reg-names = "phy_rx", "phy_tx";
1431 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1432 syscon-pcs = <&scm_conf_pcie 0x10>;
1433 clocks = <&dpll_pcie_ref_ck>,
1434 <&dpll_pcie_ref_m2ldo_ck>,
1435 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
1436 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
1437 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
1438 <&optfclk_pciephy_div>,
1440 clock-names = "dpll_ref", "dpll_ref_m2",
1441 "wkupclk", "refclk",
1442 "div-clk", "phy-div", "sysclk";
1446 pcie2_phy: pciephy@4a095000 {
1447 compatible = "ti,phy-pipe3-pcie";
1448 reg = <0x4a095000 0x80>, /* phy_rx */
1449 <0x4a095400 0x64>; /* phy_tx */
1450 reg-names = "phy_rx", "phy_tx";
1451 syscon-phy-power = <&scm_conf_pcie 0x20>;
1452 syscon-pcs = <&scm_conf_pcie 0x10>;
1453 clocks = <&dpll_pcie_ref_ck>,
1454 <&dpll_pcie_ref_m2ldo_ck>,
1455 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
1456 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
1457 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
1458 <&optfclk_pciephy_div>,
1460 clock-names = "dpll_ref", "dpll_ref_m2",
1461 "wkupclk", "refclk",
1462 "div-clk", "phy-div", "sysclk";
1464 status = "disabled";
1468 sata: sata@4a141100 {
1469 compatible = "snps,dwc-ahci";
1470 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1471 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1473 phy-names = "sata-phy";
1474 clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1476 ports-implemented = <0x1>;
1480 compatible = "ti,am3352-rtc";
1481 reg = <0x48838000 0x100>;
1482 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1484 ti,hwmods = "rtcss";
1485 clocks = <&sys_32k_ck>;
1490 compatible = "ti,omap-ocp2scp";
1491 #address-cells = <1>;
1494 reg = <0x4a080000 0x20>;
1495 ti,hwmods = "ocp2scp1";
1497 usb2_phy1: phy@4a084000 {
1498 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1499 reg = <0x4a084000 0x400>;
1500 syscon-phy-power = <&scm_conf 0x300>;
1501 clocks = <&usb_phy1_always_on_clk32k>,
1502 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1503 clock-names = "wkupclk",
1508 usb2_phy2: phy@4a085000 {
1509 compatible = "ti,dra7x-usb2-phy2",
1511 reg = <0x4a085000 0x400>;
1512 syscon-phy-power = <&scm_conf 0xe74>;
1513 clocks = <&usb_phy2_always_on_clk32k>,
1514 <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
1515 clock-names = "wkupclk",
1520 usb3_phy1: phy@4a084400 {
1521 compatible = "ti,omap-usb3";
1522 reg = <0x4a084400 0x80>,
1525 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1526 syscon-phy-power = <&scm_conf 0x370>;
1527 clocks = <&usb_phy3_always_on_clk32k>,
1529 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1530 clock-names = "wkupclk",
1537 target-module@4a0dd000 {
1538 compatible = "ti,sysc-omap4-sr", "ti,sysc";
1539 ti,hwmods = "smartreflex_core";
1540 reg = <0x4a0dd038 0x4>;
1542 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1543 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1546 <SYSC_IDLE_SMART_WKUP>;
1547 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
1548 clock-names = "fck";
1549 #address-cells = <1>;
1551 ranges = <0 0x4a0dd000 0x001000>;
1553 /* SmartReflex child device marked reserved in TRM */
1556 target-module@4a0d9000 {
1557 compatible = "ti,sysc-omap4-sr", "ti,sysc";
1558 ti,hwmods = "smartreflex_mpu";
1559 reg = <0x4a0d9038 0x4>;
1561 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1562 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1565 <SYSC_IDLE_SMART_WKUP>;
1566 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
1567 clock-names = "fck";
1568 #address-cells = <1>;
1570 ranges = <0 0x4a0d9000 0x001000>;
1572 /* SmartReflex child device marked reserved in TRM */
1575 omap_dwc3_1: omap_dwc3_1@48880000 {
1576 compatible = "ti,dwc3";
1577 ti,hwmods = "usb_otg_ss1";
1578 reg = <0x48880000 0x10000>;
1579 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1580 #address-cells = <1>;
1584 usb1: usb@48890000 {
1585 compatible = "snps,dwc3";
1586 reg = <0x48890000 0x17000>;
1587 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1590 interrupt-names = "peripheral",
1593 phys = <&usb2_phy1>, <&usb3_phy1>;
1594 phy-names = "usb2-phy", "usb3-phy";
1595 maximum-speed = "super-speed";
1597 snps,dis_u3_susphy_quirk;
1598 snps,dis_u2_susphy_quirk;
1602 omap_dwc3_2: omap_dwc3_2@488c0000 {
1603 compatible = "ti,dwc3";
1604 ti,hwmods = "usb_otg_ss2";
1605 reg = <0x488c0000 0x10000>;
1606 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1607 #address-cells = <1>;
1611 usb2: usb@488d0000 {
1612 compatible = "snps,dwc3";
1613 reg = <0x488d0000 0x17000>;
1614 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1616 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1617 interrupt-names = "peripheral",
1620 phys = <&usb2_phy2>;
1621 phy-names = "usb2-phy";
1622 maximum-speed = "high-speed";
1624 snps,dis_u3_susphy_quirk;
1625 snps,dis_u2_susphy_quirk;
1626 snps,dis_metastability_quirk;
1630 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1631 omap_dwc3_3: omap_dwc3_3@48900000 {
1632 compatible = "ti,dwc3";
1633 ti,hwmods = "usb_otg_ss3";
1634 reg = <0x48900000 0x10000>;
1635 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1636 #address-cells = <1>;
1640 status = "disabled";
1641 usb3: usb@48910000 {
1642 compatible = "snps,dwc3";
1643 reg = <0x48910000 0x17000>;
1644 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1647 interrupt-names = "peripheral",
1650 maximum-speed = "high-speed";
1652 snps,dis_u3_susphy_quirk;
1653 snps,dis_u2_susphy_quirk;
1658 compatible = "ti,am3352-elm";
1659 reg = <0x48078000 0xfc0>; /* device IO registers */
1660 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1662 status = "disabled";
1665 gpmc: gpmc@50000000 {
1666 compatible = "ti,am3352-gpmc";
1668 reg = <0x50000000 0x37c>; /* device IO registers */
1669 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1670 dmas = <&edma_xbar 4 0>;
1673 gpmc,num-waitpins = <2>;
1674 #address-cells = <2>;
1676 interrupt-controller;
1677 #interrupt-cells = <2>;
1680 status = "disabled";
1684 compatible = "ti,dra7-atl";
1685 reg = <0x4843c000 0x3ff>;
1687 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1688 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1689 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
1690 clock-names = "fck";
1691 status = "disabled";
1694 mcasp1: mcasp@48460000 {
1695 compatible = "ti,dra7-mcasp-audio";
1696 ti,hwmods = "mcasp1";
1697 reg = <0x48460000 0x2000>,
1698 <0x45800000 0x1000>;
1699 reg-names = "mpu","dat";
1700 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1702 interrupt-names = "tx", "rx";
1703 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1704 dma-names = "tx", "rx";
1705 clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
1706 <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
1707 clock-names = "fck", "ahclkx", "ahclkr";
1708 status = "disabled";
1711 mcasp2: mcasp@48464000 {
1712 compatible = "ti,dra7-mcasp-audio";
1713 ti,hwmods = "mcasp2";
1714 reg = <0x48464000 0x2000>,
1715 <0x45c00000 0x1000>;
1716 reg-names = "mpu","dat";
1717 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1718 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1719 interrupt-names = "tx", "rx";
1720 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1721 dma-names = "tx", "rx";
1722 clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
1723 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
1724 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
1725 clock-names = "fck", "ahclkx", "ahclkr";
1726 status = "disabled";
1729 mcasp3: mcasp@48468000 {
1730 compatible = "ti,dra7-mcasp-audio";
1731 ti,hwmods = "mcasp3";
1732 reg = <0x48468000 0x2000>,
1733 <0x46000000 0x1000>;
1734 reg-names = "mpu","dat";
1735 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1737 interrupt-names = "tx", "rx";
1738 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1739 dma-names = "tx", "rx";
1740 clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
1741 <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1742 clock-names = "fck", "ahclkx";
1743 status = "disabled";
1746 mcasp4: mcasp@4846c000 {
1747 compatible = "ti,dra7-mcasp-audio";
1748 ti,hwmods = "mcasp4";
1749 reg = <0x4846c000 0x2000>,
1750 <0x48436000 0x1000>;
1751 reg-names = "mpu","dat";
1752 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1754 interrupt-names = "tx", "rx";
1755 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1756 dma-names = "tx", "rx";
1757 clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
1758 <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
1759 clock-names = "fck", "ahclkx";
1760 status = "disabled";
1763 mcasp5: mcasp@48470000 {
1764 compatible = "ti,dra7-mcasp-audio";
1765 ti,hwmods = "mcasp5";
1766 reg = <0x48470000 0x2000>,
1767 <0x4843a000 0x1000>;
1768 reg-names = "mpu","dat";
1769 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1771 interrupt-names = "tx", "rx";
1772 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1773 dma-names = "tx", "rx";
1774 clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
1775 <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
1776 clock-names = "fck", "ahclkx";
1777 status = "disabled";
1780 mcasp6: mcasp@48474000 {
1781 compatible = "ti,dra7-mcasp-audio";
1782 ti,hwmods = "mcasp6";
1783 reg = <0x48474000 0x2000>,
1784 <0x4844c000 0x1000>;
1785 reg-names = "mpu","dat";
1786 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1788 interrupt-names = "tx", "rx";
1789 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1790 dma-names = "tx", "rx";
1791 clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
1792 <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
1793 clock-names = "fck", "ahclkx";
1794 status = "disabled";
1797 mcasp7: mcasp@48478000 {
1798 compatible = "ti,dra7-mcasp-audio";
1799 ti,hwmods = "mcasp7";
1800 reg = <0x48478000 0x2000>,
1801 <0x48450000 0x1000>;
1802 reg-names = "mpu","dat";
1803 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1805 interrupt-names = "tx", "rx";
1806 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1807 dma-names = "tx", "rx";
1808 clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
1809 <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
1810 clock-names = "fck", "ahclkx";
1811 status = "disabled";
1814 mcasp8: mcasp@4847c000 {
1815 compatible = "ti,dra7-mcasp-audio";
1816 ti,hwmods = "mcasp8";
1817 reg = <0x4847c000 0x2000>,
1818 <0x48454000 0x1000>;
1819 reg-names = "mpu","dat";
1820 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1822 interrupt-names = "tx", "rx";
1823 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1824 dma-names = "tx", "rx";
1825 clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
1826 <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
1827 clock-names = "fck", "ahclkx";
1828 status = "disabled";
1831 crossbar_mpu: crossbar@4a002a48 {
1832 compatible = "ti,irq-crossbar";
1833 reg = <0x4a002a48 0x130>;
1834 interrupt-controller;
1835 interrupt-parent = <&wakeupgen>;
1836 #interrupt-cells = <3>;
1837 ti,max-irqs = <160>;
1838 ti,max-crossbar-sources = <MAX_SOURCES>;
1840 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1841 ti,irqs-skip = <10 133 139 140>;
1842 ti,irqs-safe-map = <0>;
1845 mac: ethernet@48484000 {
1846 compatible = "ti,dra7-cpsw","ti,cpsw";
1848 clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
1849 clock-names = "fck", "cpts";
1850 cpdma_channels = <8>;
1851 ale_entries = <1024>;
1852 bd_ram_size = <0x2000>;
1853 mac_control = <0x20>;
1856 cpts_clock_mult = <0x784CFE14>;
1857 cpts_clock_shift = <29>;
1858 reg = <0x48484000 0x1000
1860 #address-cells = <1>;
1864 * Do not allow gating of cpsw clock as workaround
1865 * for errata i877. Keeping internal clock disabled
1866 * causes the device switching characteristics
1867 * to degrade over time and eventually fail to meet
1868 * the data manual delay time/skew specs.
1878 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1883 syscon = <&scm_conf>;
1884 status = "disabled";
1886 davinci_mdio: mdio@48485000 {
1887 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1888 #address-cells = <1>;
1890 ti,hwmods = "davinci_mdio";
1891 bus_freq = <1000000>;
1892 reg = <0x48485000 0x100>;
1895 cpsw_emac0: slave@48480200 {
1896 /* Filled in by U-Boot */
1897 mac-address = [ 00 00 00 00 00 00 ];
1900 cpsw_emac1: slave@48480300 {
1901 /* Filled in by U-Boot */
1902 mac-address = [ 00 00 00 00 00 00 ];
1905 phy_sel: cpsw-phy-sel@4a002554 {
1906 compatible = "ti,dra7xx-cpsw-phy-sel";
1907 reg= <0x4a002554 0x4>;
1908 reg-names = "gmii-sel";
1912 dcan1: can@4ae3c000 {
1913 compatible = "ti,dra7-d_can";
1914 ti,hwmods = "dcan1";
1915 reg = <0x4ae3c000 0x2000>;
1916 syscon-raminit = <&scm_conf 0x558 0>;
1917 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1918 clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
1919 status = "disabled";
1922 dcan2: can@48480000 {
1923 compatible = "ti,dra7-d_can";
1924 ti,hwmods = "dcan2";
1925 reg = <0x48480000 0x2000>;
1926 syscon-raminit = <&scm_conf 0x558 1>;
1927 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1928 clocks = <&sys_clkin1>;
1929 status = "disabled";
1933 compatible = "ti,dra7-dss";
1934 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1935 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1936 status = "disabled";
1937 ti,hwmods = "dss_core";
1938 /* CTRL_CORE_DSS_PLL_CONTROL */
1939 syscon-pll-ctrl = <&scm_conf 0x538>;
1940 #address-cells = <1>;
1945 compatible = "ti,dra7-dispc";
1946 reg = <0x58001000 0x1000>;
1947 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1948 ti,hwmods = "dss_dispc";
1949 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
1950 clock-names = "fck";
1951 /* CTRL_CORE_SMA_SW_1 */
1952 syscon-pol = <&scm_conf 0x534>;
1955 hdmi: encoder@58060000 {
1956 compatible = "ti,dra7-hdmi";
1957 reg = <0x58040000 0x200>,
1960 <0x58060000 0x19000>;
1961 reg-names = "wp", "pll", "phy", "core";
1962 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1963 status = "disabled";
1964 ti,hwmods = "dss_hdmi";
1965 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
1966 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
1967 clock-names = "fck", "sys_clk";
1968 dmas = <&sdma_xbar 76>;
1969 dma-names = "audio_tx";
1973 epwmss0: epwmss@4843e000 {
1974 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1975 reg = <0x4843e000 0x30>;
1976 ti,hwmods = "epwmss0";
1977 #address-cells = <1>;
1979 status = "disabled";
1982 ehrpwm0: pwm@4843e200 {
1983 compatible = "ti,dra746-ehrpwm",
1986 reg = <0x4843e200 0x80>;
1987 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1988 clock-names = "tbclk", "fck";
1989 status = "disabled";
1992 ecap0: ecap@4843e100 {
1993 compatible = "ti,dra746-ecap",
1996 reg = <0x4843e100 0x80>;
1997 clocks = <&l4_root_clk_div>;
1998 clock-names = "fck";
1999 status = "disabled";
2003 epwmss1: epwmss@48440000 {
2004 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2005 reg = <0x48440000 0x30>;
2006 ti,hwmods = "epwmss1";
2007 #address-cells = <1>;
2009 status = "disabled";
2012 ehrpwm1: pwm@48440200 {
2013 compatible = "ti,dra746-ehrpwm",
2016 reg = <0x48440200 0x80>;
2017 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2018 clock-names = "tbclk", "fck";
2019 status = "disabled";
2022 ecap1: ecap@48440100 {
2023 compatible = "ti,dra746-ecap",
2026 reg = <0x48440100 0x80>;
2027 clocks = <&l4_root_clk_div>;
2028 clock-names = "fck";
2029 status = "disabled";
2033 epwmss2: epwmss@48442000 {
2034 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2035 reg = <0x48442000 0x30>;
2036 ti,hwmods = "epwmss2";
2037 #address-cells = <1>;
2039 status = "disabled";
2042 ehrpwm2: pwm@48442200 {
2043 compatible = "ti,dra746-ehrpwm",
2046 reg = <0x48442200 0x80>;
2047 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2048 clock-names = "tbclk", "fck";
2049 status = "disabled";
2052 ecap2: ecap@48442100 {
2053 compatible = "ti,dra746-ecap",
2056 reg = <0x48442100 0x80>;
2057 clocks = <&l4_root_clk_div>;
2058 clock-names = "fck";
2059 status = "disabled";
2063 aes1: aes@4b500000 {
2064 compatible = "ti,omap4-aes";
2066 reg = <0x4b500000 0xa0>;
2067 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2068 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2069 dma-names = "tx", "rx";
2070 clocks = <&l3_iclk_div>;
2071 clock-names = "fck";
2074 aes2: aes@4b700000 {
2075 compatible = "ti,omap4-aes";
2077 reg = <0x4b700000 0xa0>;
2078 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2079 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2080 dma-names = "tx", "rx";
2081 clocks = <&l3_iclk_div>;
2082 clock-names = "fck";
2086 compatible = "ti,omap4-des";
2088 reg = <0x480a5000 0xa0>;
2089 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2090 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2091 dma-names = "tx", "rx";
2092 clocks = <&l3_iclk_div>;
2093 clock-names = "fck";
2096 sham: sham@53100000 {
2097 compatible = "ti,omap5-sham";
2099 reg = <0x4b101000 0x300>;
2100 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2101 dmas = <&edma_xbar 119 0>;
2103 clocks = <&l3_iclk_div>;
2104 clock-names = "fck";
2108 compatible = "ti,omap4-rng";
2110 reg = <0x48090000 0x2000>;
2111 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2112 clocks = <&l3_iclk_div>;
2113 clock-names = "fck";
2116 opp_supply_mpu: opp-supply@4a003b20 {
2117 compatible = "ti,omap5-opp-supply";
2118 reg = <0x4a003b20 0xc>;
2119 ti,efuse-settings = <
2125 ti,absolute-max-voltage-uv = <1500000>;
2130 thermal_zones: thermal-zones {
2131 #include "omap4-cpu-thermal.dtsi"
2132 #include "omap5-gpu-thermal.dtsi"
2133 #include "omap5-core-thermal.dtsi"
2134 #include "dra7-dspeve-thermal.dtsi"
2135 #include "dra7-iva-thermal.dtsi"
2141 polling-delay = <500>; /* milliseconds */
2142 coefficients = <0 2000>;
2146 coefficients = <0 2000>;
2150 coefficients = <0 2000>;
2154 coefficients = <0 2000>;
2158 coefficients = <0 2000>;
2162 temperature = <120000>; /* milli Celsius */
2165 #include "dra7xx-clocks.dtsi"
2168 temperature = <120000>; /* milli Celsius */
2172 temperature = <120000>; /* milli Celsius */
2176 temperature = <120000>; /* milli Celsius */
2180 temperature = <120000>; /* milli Celsius */