2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #define MAX_SOURCES 400
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x0 0x48211000 0x0 0x1000>,
60 <0x0 0x48212000 0x0 0x1000>,
61 <0x0 0x48214000 0x0 0x2000>,
62 <0x0 0x48216000 0x0 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 #interrupt-cells = <3>;
71 reg = <0x0 0x48281000 0x0 0x1000>;
72 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a15";
90 clocks = <&dpll_mpu_ck>;
93 clock-latency = <300000>; /* From omap-cpufreq driver */
96 cooling-min-level = <0>;
97 cooling-max-level = <2>;
98 #cooling-cells = <2>; /* min followed by max */
103 * The soc node represents the soc top level view. It is used for IPs
104 * that are not memory mapped in the MPU view or for the MPU itself.
107 compatible = "ti,omap-infra";
109 compatible = "ti,omap5-mpu";
115 * XXX: Use a flat representation of the SOC interconnect.
116 * The real OMAP interconnect network is quite complex.
117 * Since it will not bring real advantage to represent that in DT for
118 * the moment, just use a fake OCP bus entry to represent the whole bus
122 compatible = "ti,dra7-l3-noc", "simple-bus";
123 #address-cells = <1>;
125 ranges = <0x0 0x0 0x0 0xc0000000>;
126 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
127 ti,hwmods = "l3_main_1", "l3_main_2";
128 reg = <0x0 0x44000000 0x0 0x1000000>,
129 <0x0 0x45000000 0x0 0x1000>;
130 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
131 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
133 l4_cfg: l4@4a000000 {
134 compatible = "ti,dra7-l4-cfg", "simple-bus";
135 #address-cells = <1>;
137 ranges = <0 0x4a000000 0x22c000>;
140 compatible = "ti,dra7-scm-core", "simple-bus";
141 reg = <0x2000 0x2000>;
142 #address-cells = <1>;
144 ranges = <0 0x2000 0x2000>;
146 scm_conf: scm_conf@0 {
147 compatible = "syscon", "simple-bus";
149 #address-cells = <1>;
151 ranges = <0 0x0 0x1400>;
153 pbias_regulator: pbias_regulator@e00 {
154 compatible = "ti,pbias-dra7", "ti,pbias-omap";
156 syscon = <&scm_conf>;
157 pbias_mmc_reg: pbias_mmc_omap5 {
158 regulator-name = "pbias_mmc_omap5";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <3000000>;
164 scm_conf_clocks: clocks {
165 #address-cells = <1>;
170 dra7_pmx_core: pinmux@1400 {
171 compatible = "ti,dra7-padconf",
173 reg = <0x1400 0x0468>;
174 #address-cells = <1>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <32>;
179 pinctrl-single,function-mask = <0x3fffffff>;
182 scm_conf1: scm_conf@1c04 {
183 compatible = "syscon";
184 reg = <0x1c04 0x0020>;
187 scm_conf_pcie: scm_conf@1c24 {
188 compatible = "syscon";
189 reg = <0x1c24 0x0024>;
192 sdma_xbar: dma-router@b78 {
193 compatible = "ti,dra7-dma-crossbar";
196 dma-requests = <205>;
197 ti,dma-safe-map = <0>;
198 dma-masters = <&sdma>;
201 edma_xbar: dma-router@c78 {
202 compatible = "ti,dra7-dma-crossbar";
205 dma-requests = <204>;
206 ti,dma-safe-map = <0>;
207 dma-masters = <&edma>;
211 cm_core_aon: cm_core_aon@5000 {
212 compatible = "ti,dra7-cm-core-aon";
213 reg = <0x5000 0x2000>;
215 cm_core_aon_clocks: clocks {
216 #address-cells = <1>;
220 cm_core_aon_clockdomains: clockdomains {
224 cm_core: cm_core@8000 {
225 compatible = "ti,dra7-cm-core";
226 reg = <0x8000 0x3000>;
228 cm_core_clocks: clocks {
229 #address-cells = <1>;
233 cm_core_clockdomains: clockdomains {
238 l4_wkup: l4@4ae00000 {
239 compatible = "ti,dra7-l4-wkup", "simple-bus";
240 #address-cells = <1>;
242 ranges = <0 0x4ae00000 0x3f000>;
244 counter32k: counter@4000 {
245 compatible = "ti,omap-counter32k";
247 ti,hwmods = "counter_32k";
251 compatible = "ti,dra7-prm";
252 reg = <0x6000 0x3000>;
253 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
256 #address-cells = <1>;
260 prm_clockdomains: clockdomains {
264 scm_wkup: scm_conf@c000 {
265 compatible = "syscon";
266 reg = <0xc000 0x1000>;
271 compatible = "simple-bus";
273 #address-cells = <1>;
274 ranges = <0x51000000 0x51000000 0x3000
275 0x0 0x20000000 0x10000000>;
276 pcie1: pcie@51000000 {
277 compatible = "ti,dra7-pcie";
278 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
279 reg-names = "rc_dbics", "ti_conf", "config";
280 interrupts = <0 232 0x4>, <0 233 0x4>;
281 #address-cells = <3>;
284 ranges = <0x81000000 0 0 0x03000 0 0x00010000
285 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
286 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
287 bus-range = <0x00 0xff>;
288 #interrupt-cells = <1>;
290 linux,pci-domain = <0>;
293 phy-names = "pcie-phy0";
294 interrupt-map-mask = <0 0 0 7>;
295 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
296 <0 0 0 2 &pcie1_intc 2>,
297 <0 0 0 3 &pcie1_intc 3>,
298 <0 0 0 4 &pcie1_intc 4>;
299 pcie1_intc: interrupt-controller {
300 interrupt-controller;
301 #address-cells = <0>;
302 #interrupt-cells = <1>;
308 compatible = "simple-bus";
310 #address-cells = <1>;
311 ranges = <0x51800000 0x51800000 0x3000
312 0x0 0x30000000 0x10000000>;
315 compatible = "ti,dra7-pcie";
316 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
317 reg-names = "rc_dbics", "ti_conf", "config";
318 interrupts = <0 355 0x4>, <0 356 0x4>;
319 #address-cells = <3>;
322 ranges = <0x81000000 0 0 0x03000 0 0x00010000
323 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
324 dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
325 bus-range = <0x00 0xff>;
326 #interrupt-cells = <1>;
328 linux,pci-domain = <1>;
331 phy-names = "pcie-phy0";
332 interrupt-map-mask = <0 0 0 7>;
333 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
334 <0 0 0 2 &pcie2_intc 2>,
335 <0 0 0 3 &pcie2_intc 3>,
336 <0 0 0 4 &pcie2_intc 4>;
337 pcie2_intc: interrupt-controller {
338 interrupt-controller;
339 #address-cells = <0>;
340 #interrupt-cells = <1>;
345 ocmcram1: ocmcram@40300000 {
346 compatible = "mmio-sram";
347 reg = <0x40300000 0x80000>;
348 ranges = <0x0 0x40300000 0x80000>;
349 #address-cells = <1>;
352 * This is a placeholder for an optional reserved
353 * region for use by secure software. The size
354 * of this region is not known until runtime so it
355 * is set as zero to either be updated to reserve
356 * space or left unchanged to leave all SRAM for use.
357 * On HS parts that that require the reserved region
358 * either the bootloader can update the size to
359 * the required amount or the node can be overridden
360 * from the board dts file for the secure platform.
363 compatible = "ti,secure-ram";
369 * NOTE: ocmcram2 and ocmcram3 are not available on all
370 * DRA7xx and AM57xx variants. Confirm availability in
371 * the data manual for the exact part number in use
372 * before enabling these nodes in the board dts file.
374 ocmcram2: ocmcram@40400000 {
376 compatible = "mmio-sram";
377 reg = <0x40400000 0x100000>;
378 ranges = <0x0 0x40400000 0x100000>;
379 #address-cells = <1>;
383 ocmcram3: ocmcram@40500000 {
385 compatible = "mmio-sram";
386 reg = <0x40500000 0x100000>;
387 ranges = <0x0 0x40500000 0x100000>;
388 #address-cells = <1>;
392 bandgap: bandgap@4a0021e0 {
393 reg = <0x4a0021e0 0xc
399 compatible = "ti,dra752-bandgap";
400 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
401 #thermal-sensor-cells = <1>;
404 dsp1_system: dsp_system@40d00000 {
405 compatible = "syscon";
406 reg = <0x40d00000 0x100>;
409 sdma: dma-controller@4a056000 {
410 compatible = "ti,omap4430-sdma";
411 reg = <0x4a056000 0x1000>;
412 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
418 dma-requests = <127>;
421 edma: edma@43300000 {
422 compatible = "ti,edma3-tpcc";
424 reg = <0x43300000 0x100000>;
425 reg-names = "edma3_cc";
426 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "edma3_ccint", "edma3_mperr",
434 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
437 * memcpy is disabled, can be enabled with:
438 * ti,edma-memcpy-channels = <20 21>;
439 * for example. Note that these channels need to be
440 * masked in the xbar as well.
444 edma_tptc0: tptc@43400000 {
445 compatible = "ti,edma3-tptc";
447 reg = <0x43400000 0x100000>;
448 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
449 interrupt-names = "edma3_tcerrint";
452 edma_tptc1: tptc@43500000 {
453 compatible = "ti,edma3-tptc";
455 reg = <0x43500000 0x100000>;
456 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
457 interrupt-names = "edma3_tcerrint";
460 gpio1: gpio@4ae10000 {
461 compatible = "ti,omap4-gpio";
462 reg = <0x4ae10000 0x200>;
463 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
471 gpio2: gpio@48055000 {
472 compatible = "ti,omap4-gpio";
473 reg = <0x48055000 0x200>;
474 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
482 gpio3: gpio@48057000 {
483 compatible = "ti,omap4-gpio";
484 reg = <0x48057000 0x200>;
485 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
489 interrupt-controller;
490 #interrupt-cells = <2>;
493 gpio4: gpio@48059000 {
494 compatible = "ti,omap4-gpio";
495 reg = <0x48059000 0x200>;
496 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
504 gpio5: gpio@4805b000 {
505 compatible = "ti,omap4-gpio";
506 reg = <0x4805b000 0x200>;
507 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-controller;
512 #interrupt-cells = <2>;
515 gpio6: gpio@4805d000 {
516 compatible = "ti,omap4-gpio";
517 reg = <0x4805d000 0x200>;
518 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
526 gpio7: gpio@48051000 {
527 compatible = "ti,omap4-gpio";
528 reg = <0x48051000 0x200>;
529 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
537 gpio8: gpio@48053000 {
538 compatible = "ti,omap4-gpio";
539 reg = <0x48053000 0x200>;
540 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
548 uart1: serial@4806a000 {
549 compatible = "ti,dra742-uart", "ti,omap4-uart";
550 reg = <0x4806a000 0x100>;
551 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
553 clock-frequency = <48000000>;
555 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
556 dma-names = "tx", "rx";
559 uart2: serial@4806c000 {
560 compatible = "ti,dra742-uart", "ti,omap4-uart";
561 reg = <0x4806c000 0x100>;
562 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
564 clock-frequency = <48000000>;
566 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
567 dma-names = "tx", "rx";
570 uart3: serial@48020000 {
571 compatible = "ti,dra742-uart", "ti,omap4-uart";
572 reg = <0x48020000 0x100>;
573 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
575 clock-frequency = <48000000>;
577 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
578 dma-names = "tx", "rx";
581 uart4: serial@4806e000 {
582 compatible = "ti,dra742-uart", "ti,omap4-uart";
583 reg = <0x4806e000 0x100>;
584 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
586 clock-frequency = <48000000>;
588 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
589 dma-names = "tx", "rx";
592 uart5: serial@48066000 {
593 compatible = "ti,dra742-uart", "ti,omap4-uart";
594 reg = <0x48066000 0x100>;
595 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
597 clock-frequency = <48000000>;
599 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
600 dma-names = "tx", "rx";
603 uart6: serial@48068000 {
604 compatible = "ti,dra742-uart", "ti,omap4-uart";
605 reg = <0x48068000 0x100>;
606 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
608 clock-frequency = <48000000>;
610 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
611 dma-names = "tx", "rx";
614 uart7: serial@48420000 {
615 compatible = "ti,dra742-uart", "ti,omap4-uart";
616 reg = <0x48420000 0x100>;
617 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
619 clock-frequency = <48000000>;
623 uart8: serial@48422000 {
624 compatible = "ti,dra742-uart", "ti,omap4-uart";
625 reg = <0x48422000 0x100>;
626 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
628 clock-frequency = <48000000>;
632 uart9: serial@48424000 {
633 compatible = "ti,dra742-uart", "ti,omap4-uart";
634 reg = <0x48424000 0x100>;
635 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
637 clock-frequency = <48000000>;
641 uart10: serial@4ae2b000 {
642 compatible = "ti,dra742-uart", "ti,omap4-uart";
643 reg = <0x4ae2b000 0x100>;
644 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
645 ti,hwmods = "uart10";
646 clock-frequency = <48000000>;
650 mailbox1: mailbox@4a0f4000 {
651 compatible = "ti,omap4-mailbox";
652 reg = <0x4a0f4000 0x200>;
653 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
656 ti,hwmods = "mailbox1";
658 ti,mbox-num-users = <3>;
659 ti,mbox-num-fifos = <8>;
663 mailbox2: mailbox@4883a000 {
664 compatible = "ti,omap4-mailbox";
665 reg = <0x4883a000 0x200>;
666 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
670 ti,hwmods = "mailbox2";
672 ti,mbox-num-users = <4>;
673 ti,mbox-num-fifos = <12>;
677 mailbox3: mailbox@4883c000 {
678 compatible = "ti,omap4-mailbox";
679 reg = <0x4883c000 0x200>;
680 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
684 ti,hwmods = "mailbox3";
686 ti,mbox-num-users = <4>;
687 ti,mbox-num-fifos = <12>;
691 mailbox4: mailbox@4883e000 {
692 compatible = "ti,omap4-mailbox";
693 reg = <0x4883e000 0x200>;
694 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
698 ti,hwmods = "mailbox4";
700 ti,mbox-num-users = <4>;
701 ti,mbox-num-fifos = <12>;
705 mailbox5: mailbox@48840000 {
706 compatible = "ti,omap4-mailbox";
707 reg = <0x48840000 0x200>;
708 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
712 ti,hwmods = "mailbox5";
714 ti,mbox-num-users = <4>;
715 ti,mbox-num-fifos = <12>;
719 mailbox6: mailbox@48842000 {
720 compatible = "ti,omap4-mailbox";
721 reg = <0x48842000 0x200>;
722 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "mailbox6";
728 ti,mbox-num-users = <4>;
729 ti,mbox-num-fifos = <12>;
733 mailbox7: mailbox@48844000 {
734 compatible = "ti,omap4-mailbox";
735 reg = <0x48844000 0x200>;
736 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
740 ti,hwmods = "mailbox7";
742 ti,mbox-num-users = <4>;
743 ti,mbox-num-fifos = <12>;
747 mailbox8: mailbox@48846000 {
748 compatible = "ti,omap4-mailbox";
749 reg = <0x48846000 0x200>;
750 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
754 ti,hwmods = "mailbox8";
756 ti,mbox-num-users = <4>;
757 ti,mbox-num-fifos = <12>;
761 mailbox9: mailbox@4885e000 {
762 compatible = "ti,omap4-mailbox";
763 reg = <0x4885e000 0x200>;
764 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
768 ti,hwmods = "mailbox9";
770 ti,mbox-num-users = <4>;
771 ti,mbox-num-fifos = <12>;
775 mailbox10: mailbox@48860000 {
776 compatible = "ti,omap4-mailbox";
777 reg = <0x48860000 0x200>;
778 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
782 ti,hwmods = "mailbox10";
784 ti,mbox-num-users = <4>;
785 ti,mbox-num-fifos = <12>;
789 mailbox11: mailbox@48862000 {
790 compatible = "ti,omap4-mailbox";
791 reg = <0x48862000 0x200>;
792 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
796 ti,hwmods = "mailbox11";
798 ti,mbox-num-users = <4>;
799 ti,mbox-num-fifos = <12>;
803 mailbox12: mailbox@48864000 {
804 compatible = "ti,omap4-mailbox";
805 reg = <0x48864000 0x200>;
806 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
810 ti,hwmods = "mailbox12";
812 ti,mbox-num-users = <4>;
813 ti,mbox-num-fifos = <12>;
817 mailbox13: mailbox@48802000 {
818 compatible = "ti,omap4-mailbox";
819 reg = <0x48802000 0x200>;
820 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
824 ti,hwmods = "mailbox13";
826 ti,mbox-num-users = <4>;
827 ti,mbox-num-fifos = <12>;
831 timer1: timer@4ae18000 {
832 compatible = "ti,omap5430-timer";
833 reg = <0x4ae18000 0x80>;
834 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
835 ti,hwmods = "timer1";
839 timer2: timer@48032000 {
840 compatible = "ti,omap5430-timer";
841 reg = <0x48032000 0x80>;
842 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
843 ti,hwmods = "timer2";
846 timer3: timer@48034000 {
847 compatible = "ti,omap5430-timer";
848 reg = <0x48034000 0x80>;
849 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
850 ti,hwmods = "timer3";
853 timer4: timer@48036000 {
854 compatible = "ti,omap5430-timer";
855 reg = <0x48036000 0x80>;
856 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
857 ti,hwmods = "timer4";
860 timer5: timer@48820000 {
861 compatible = "ti,omap5430-timer";
862 reg = <0x48820000 0x80>;
863 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
864 ti,hwmods = "timer5";
867 timer6: timer@48822000 {
868 compatible = "ti,omap5430-timer";
869 reg = <0x48822000 0x80>;
870 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
871 ti,hwmods = "timer6";
874 timer7: timer@48824000 {
875 compatible = "ti,omap5430-timer";
876 reg = <0x48824000 0x80>;
877 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
878 ti,hwmods = "timer7";
881 timer8: timer@48826000 {
882 compatible = "ti,omap5430-timer";
883 reg = <0x48826000 0x80>;
884 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
885 ti,hwmods = "timer8";
888 timer9: timer@4803e000 {
889 compatible = "ti,omap5430-timer";
890 reg = <0x4803e000 0x80>;
891 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
892 ti,hwmods = "timer9";
895 timer10: timer@48086000 {
896 compatible = "ti,omap5430-timer";
897 reg = <0x48086000 0x80>;
898 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
899 ti,hwmods = "timer10";
902 timer11: timer@48088000 {
903 compatible = "ti,omap5430-timer";
904 reg = <0x48088000 0x80>;
905 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
906 ti,hwmods = "timer11";
909 timer12: timer@4ae20000 {
910 compatible = "ti,omap5430-timer";
911 reg = <0x4ae20000 0x80>;
912 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
913 ti,hwmods = "timer12";
918 timer13: timer@48828000 {
919 compatible = "ti,omap5430-timer";
920 reg = <0x48828000 0x80>;
921 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
922 ti,hwmods = "timer13";
925 timer14: timer@4882a000 {
926 compatible = "ti,omap5430-timer";
927 reg = <0x4882a000 0x80>;
928 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
929 ti,hwmods = "timer14";
932 timer15: timer@4882c000 {
933 compatible = "ti,omap5430-timer";
934 reg = <0x4882c000 0x80>;
935 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
936 ti,hwmods = "timer15";
939 timer16: timer@4882e000 {
940 compatible = "ti,omap5430-timer";
941 reg = <0x4882e000 0x80>;
942 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
943 ti,hwmods = "timer16";
947 compatible = "ti,omap3-wdt";
948 reg = <0x4ae14000 0x80>;
949 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
950 ti,hwmods = "wd_timer2";
953 hwspinlock: spinlock@4a0f6000 {
954 compatible = "ti,omap4-hwspinlock";
955 reg = <0x4a0f6000 0x1000>;
956 ti,hwmods = "spinlock";
961 compatible = "ti,omap5-dmm";
962 reg = <0x4e000000 0x800>;
963 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
968 compatible = "ti,omap4-i2c";
969 reg = <0x48070000 0x100>;
970 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
971 #address-cells = <1>;
978 compatible = "ti,omap4-i2c";
979 reg = <0x48072000 0x100>;
980 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
981 #address-cells = <1>;
988 compatible = "ti,omap4-i2c";
989 reg = <0x48060000 0x100>;
990 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
991 #address-cells = <1>;
998 compatible = "ti,omap4-i2c";
999 reg = <0x4807a000 0x100>;
1000 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cells = <1>;
1004 status = "disabled";
1007 i2c5: i2c@4807c000 {
1008 compatible = "ti,omap4-i2c";
1009 reg = <0x4807c000 0x100>;
1010 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cells = <1>;
1014 status = "disabled";
1017 mmc1: mmc@4809c000 {
1018 compatible = "ti,omap4-hsmmc";
1019 reg = <0x4809c000 0x400>;
1020 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1023 ti,needs-special-reset;
1024 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1025 dma-names = "tx", "rx";
1026 status = "disabled";
1027 pbias-supply = <&pbias_mmc_reg>;
1030 mmc2: mmc@480b4000 {
1031 compatible = "ti,omap4-hsmmc";
1032 reg = <0x480b4000 0x400>;
1033 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1035 ti,needs-special-reset;
1036 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1037 dma-names = "tx", "rx";
1038 status = "disabled";
1041 mmc3: mmc@480ad000 {
1042 compatible = "ti,omap4-hsmmc";
1043 reg = <0x480ad000 0x400>;
1044 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1046 ti,needs-special-reset;
1047 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1048 dma-names = "tx", "rx";
1049 status = "disabled";
1052 mmc4: mmc@480d1000 {
1053 compatible = "ti,omap4-hsmmc";
1054 reg = <0x480d1000 0x400>;
1055 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1057 ti,needs-special-reset;
1058 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1059 dma-names = "tx", "rx";
1060 status = "disabled";
1063 mmu0_dsp1: mmu@40d01000 {
1064 compatible = "ti,dra7-dsp-iommu";
1065 reg = <0x40d01000 0x100>;
1066 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1067 ti,hwmods = "mmu0_dsp1";
1069 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1070 status = "disabled";
1073 mmu1_dsp1: mmu@40d02000 {
1074 compatible = "ti,dra7-dsp-iommu";
1075 reg = <0x40d02000 0x100>;
1076 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1077 ti,hwmods = "mmu1_dsp1";
1079 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1080 status = "disabled";
1083 mmu_ipu1: mmu@58882000 {
1084 compatible = "ti,dra7-iommu";
1085 reg = <0x58882000 0x100>;
1086 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1087 ti,hwmods = "mmu_ipu1";
1089 ti,iommu-bus-err-back;
1090 status = "disabled";
1093 mmu_ipu2: mmu@55082000 {
1094 compatible = "ti,dra7-iommu";
1095 reg = <0x55082000 0x100>;
1096 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1097 ti,hwmods = "mmu_ipu2";
1099 ti,iommu-bus-err-back;
1100 status = "disabled";
1103 abb_mpu: regulator-abb-mpu {
1104 compatible = "ti,abb-v3";
1105 regulator-name = "abb_mpu";
1106 #address-cells = <0>;
1108 clocks = <&sys_clkin1>;
1109 ti,settling-time = <50>;
1110 ti,clock-cycles = <16>;
1112 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1113 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1115 reg-names = "setup-address", "control-address",
1116 "int-address", "efuse-address",
1118 ti,tranxdone-status-mask = <0x80>;
1119 /* LDOVBBMPU_FBB_MUX_CTRL */
1120 ti,ldovbb-override-mask = <0x400>;
1121 /* LDOVBBMPU_FBB_VSET_OUT */
1122 ti,ldovbb-vset-mask = <0x1F>;
1125 * NOTE: only FBB mode used but actual vset will
1126 * determine final biasing
1129 /*uV ABB efuse rbb_m fbb_m vset_m*/
1130 1060000 0 0x0 0 0x02000000 0x01F00000
1131 1160000 0 0x4 0 0x02000000 0x01F00000
1132 1210000 0 0x8 0 0x02000000 0x01F00000
1136 abb_ivahd: regulator-abb-ivahd {
1137 compatible = "ti,abb-v3";
1138 regulator-name = "abb_ivahd";
1139 #address-cells = <0>;
1141 clocks = <&sys_clkin1>;
1142 ti,settling-time = <50>;
1143 ti,clock-cycles = <16>;
1145 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1146 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1148 reg-names = "setup-address", "control-address",
1149 "int-address", "efuse-address",
1151 ti,tranxdone-status-mask = <0x40000000>;
1152 /* LDOVBBIVA_FBB_MUX_CTRL */
1153 ti,ldovbb-override-mask = <0x400>;
1154 /* LDOVBBIVA_FBB_VSET_OUT */
1155 ti,ldovbb-vset-mask = <0x1F>;
1158 * NOTE: only FBB mode used but actual vset will
1159 * determine final biasing
1162 /*uV ABB efuse rbb_m fbb_m vset_m*/
1163 1055000 0 0x0 0 0x02000000 0x01F00000
1164 1150000 0 0x4 0 0x02000000 0x01F00000
1165 1250000 0 0x8 0 0x02000000 0x01F00000
1169 abb_dspeve: regulator-abb-dspeve {
1170 compatible = "ti,abb-v3";
1171 regulator-name = "abb_dspeve";
1172 #address-cells = <0>;
1174 clocks = <&sys_clkin1>;
1175 ti,settling-time = <50>;
1176 ti,clock-cycles = <16>;
1178 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1179 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1181 reg-names = "setup-address", "control-address",
1182 "int-address", "efuse-address",
1184 ti,tranxdone-status-mask = <0x20000000>;
1185 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1186 ti,ldovbb-override-mask = <0x400>;
1187 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1188 ti,ldovbb-vset-mask = <0x1F>;
1191 * NOTE: only FBB mode used but actual vset will
1192 * determine final biasing
1195 /*uV ABB efuse rbb_m fbb_m vset_m*/
1196 1055000 0 0x0 0 0x02000000 0x01F00000
1197 1150000 0 0x4 0 0x02000000 0x01F00000
1198 1250000 0 0x8 0 0x02000000 0x01F00000
1202 abb_gpu: regulator-abb-gpu {
1203 compatible = "ti,abb-v3";
1204 regulator-name = "abb_gpu";
1205 #address-cells = <0>;
1207 clocks = <&sys_clkin1>;
1208 ti,settling-time = <50>;
1209 ti,clock-cycles = <16>;
1211 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1212 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1214 reg-names = "setup-address", "control-address",
1215 "int-address", "efuse-address",
1217 ti,tranxdone-status-mask = <0x10000000>;
1218 /* LDOVBBGPU_FBB_MUX_CTRL */
1219 ti,ldovbb-override-mask = <0x400>;
1220 /* LDOVBBGPU_FBB_VSET_OUT */
1221 ti,ldovbb-vset-mask = <0x1F>;
1224 * NOTE: only FBB mode used but actual vset will
1225 * determine final biasing
1228 /*uV ABB efuse rbb_m fbb_m vset_m*/
1229 1090000 0 0x0 0 0x02000000 0x01F00000
1230 1210000 0 0x4 0 0x02000000 0x01F00000
1231 1280000 0 0x8 0 0x02000000 0x01F00000
1235 mcspi1: spi@48098000 {
1236 compatible = "ti,omap4-mcspi";
1237 reg = <0x48098000 0x200>;
1238 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cells = <1>;
1241 ti,hwmods = "mcspi1";
1242 ti,spi-num-cs = <4>;
1243 dmas = <&sdma_xbar 35>,
1251 dma-names = "tx0", "rx0", "tx1", "rx1",
1252 "tx2", "rx2", "tx3", "rx3";
1253 status = "disabled";
1256 mcspi2: spi@4809a000 {
1257 compatible = "ti,omap4-mcspi";
1258 reg = <0x4809a000 0x200>;
1259 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1260 #address-cells = <1>;
1262 ti,hwmods = "mcspi2";
1263 ti,spi-num-cs = <2>;
1264 dmas = <&sdma_xbar 43>,
1268 dma-names = "tx0", "rx0", "tx1", "rx1";
1269 status = "disabled";
1272 mcspi3: spi@480b8000 {
1273 compatible = "ti,omap4-mcspi";
1274 reg = <0x480b8000 0x200>;
1275 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1276 #address-cells = <1>;
1278 ti,hwmods = "mcspi3";
1279 ti,spi-num-cs = <2>;
1280 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1281 dma-names = "tx0", "rx0";
1282 status = "disabled";
1285 mcspi4: spi@480ba000 {
1286 compatible = "ti,omap4-mcspi";
1287 reg = <0x480ba000 0x200>;
1288 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1289 #address-cells = <1>;
1291 ti,hwmods = "mcspi4";
1292 ti,spi-num-cs = <1>;
1293 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1294 dma-names = "tx0", "rx0";
1295 status = "disabled";
1298 qspi: qspi@4b300000 {
1299 compatible = "ti,dra7xxx-qspi";
1300 reg = <0x4b300000 0x100>,
1301 <0x5c000000 0x4000000>;
1302 reg-names = "qspi_base", "qspi_mmap";
1303 syscon-chipselects = <&scm_conf 0x558>;
1304 #address-cells = <1>;
1307 clocks = <&qspi_gfclk_div>;
1308 clock-names = "fck";
1310 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1311 status = "disabled";
1316 compatible = "ti,omap-ocp2scp";
1317 #address-cells = <1>;
1320 reg = <0x4a090000 0x20>;
1321 ti,hwmods = "ocp2scp3";
1322 sata_phy: phy@4A096000 {
1323 compatible = "ti,phy-pipe3-sata";
1324 reg = <0x4A096000 0x80>, /* phy_rx */
1325 <0x4A096400 0x64>, /* phy_tx */
1326 <0x4A096800 0x40>; /* pll_ctrl */
1327 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1328 syscon-phy-power = <&scm_conf 0x374>;
1329 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1330 clock-names = "sysclk", "refclk";
1331 syscon-pllreset = <&scm_conf 0x3fc>;
1335 pcie1_phy: pciephy@4a094000 {
1336 compatible = "ti,phy-pipe3-pcie";
1337 reg = <0x4a094000 0x80>, /* phy_rx */
1338 <0x4a094400 0x64>; /* phy_tx */
1339 reg-names = "phy_rx", "phy_tx";
1340 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1341 syscon-pcs = <&scm_conf_pcie 0x10>;
1342 clocks = <&dpll_pcie_ref_ck>,
1343 <&dpll_pcie_ref_m2ldo_ck>,
1344 <&optfclk_pciephy1_32khz>,
1345 <&optfclk_pciephy1_clk>,
1346 <&optfclk_pciephy1_div_clk>,
1347 <&optfclk_pciephy_div>,
1349 clock-names = "dpll_ref", "dpll_ref_m2",
1350 "wkupclk", "refclk",
1351 "div-clk", "phy-div", "sysclk";
1355 pcie2_phy: pciephy@4a095000 {
1356 compatible = "ti,phy-pipe3-pcie";
1357 reg = <0x4a095000 0x80>, /* phy_rx */
1358 <0x4a095400 0x64>; /* phy_tx */
1359 reg-names = "phy_rx", "phy_tx";
1360 syscon-phy-power = <&scm_conf_pcie 0x20>;
1361 syscon-pcs = <&scm_conf_pcie 0x10>;
1362 clocks = <&dpll_pcie_ref_ck>,
1363 <&dpll_pcie_ref_m2ldo_ck>,
1364 <&optfclk_pciephy2_32khz>,
1365 <&optfclk_pciephy2_clk>,
1366 <&optfclk_pciephy2_div_clk>,
1367 <&optfclk_pciephy_div>,
1369 clock-names = "dpll_ref", "dpll_ref_m2",
1370 "wkupclk", "refclk",
1371 "div-clk", "phy-div", "sysclk";
1373 status = "disabled";
1377 sata: sata@4a141100 {
1378 compatible = "snps,dwc-ahci";
1379 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1380 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1382 phy-names = "sata-phy";
1383 clocks = <&sata_ref_clk>;
1385 ports-implemented = <0x1>;
1389 compatible = "ti,am3352-rtc";
1390 reg = <0x48838000 0x100>;
1391 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1393 ti,hwmods = "rtcss";
1394 clocks = <&sys_32k_ck>;
1399 compatible = "ti,omap-ocp2scp";
1400 #address-cells = <1>;
1403 reg = <0x4a080000 0x20>;
1404 ti,hwmods = "ocp2scp1";
1406 usb2_phy1: phy@4a084000 {
1407 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1408 reg = <0x4a084000 0x400>;
1409 syscon-phy-power = <&scm_conf 0x300>;
1410 clocks = <&usb_phy1_always_on_clk32k>,
1411 <&usb_otg_ss1_refclk960m>;
1412 clock-names = "wkupclk",
1417 usb2_phy2: phy@4a085000 {
1418 compatible = "ti,dra7x-usb2-phy2",
1420 reg = <0x4a085000 0x400>;
1421 syscon-phy-power = <&scm_conf 0xe74>;
1422 clocks = <&usb_phy2_always_on_clk32k>,
1423 <&usb_otg_ss2_refclk960m>;
1424 clock-names = "wkupclk",
1429 usb3_phy1: phy@4a084400 {
1430 compatible = "ti,omap-usb3";
1431 reg = <0x4a084400 0x80>,
1434 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1435 syscon-phy-power = <&scm_conf 0x370>;
1436 clocks = <&usb_phy3_always_on_clk32k>,
1438 <&usb_otg_ss1_refclk960m>;
1439 clock-names = "wkupclk",
1446 omap_dwc3_1: omap_dwc3_1@48880000 {
1447 compatible = "ti,dwc3";
1448 ti,hwmods = "usb_otg_ss1";
1449 reg = <0x48880000 0x10000>;
1450 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1451 #address-cells = <1>;
1455 usb1: usb@48890000 {
1456 compatible = "snps,dwc3";
1457 reg = <0x48890000 0x17000>;
1458 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1461 interrupt-names = "peripheral",
1464 phys = <&usb2_phy1>, <&usb3_phy1>;
1465 phy-names = "usb2-phy", "usb3-phy";
1466 maximum-speed = "super-speed";
1468 snps,dis_u3_susphy_quirk;
1469 snps,dis_u2_susphy_quirk;
1473 omap_dwc3_2: omap_dwc3_2@488c0000 {
1474 compatible = "ti,dwc3";
1475 ti,hwmods = "usb_otg_ss2";
1476 reg = <0x488c0000 0x10000>;
1477 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1478 #address-cells = <1>;
1482 usb2: usb@488d0000 {
1483 compatible = "snps,dwc3";
1484 reg = <0x488d0000 0x17000>;
1485 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1488 interrupt-names = "peripheral",
1491 phys = <&usb2_phy2>;
1492 phy-names = "usb2-phy";
1493 maximum-speed = "high-speed";
1495 snps,dis_u3_susphy_quirk;
1496 snps,dis_u2_susphy_quirk;
1500 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1501 omap_dwc3_3: omap_dwc3_3@48900000 {
1502 compatible = "ti,dwc3";
1503 ti,hwmods = "usb_otg_ss3";
1504 reg = <0x48900000 0x10000>;
1505 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1506 #address-cells = <1>;
1510 status = "disabled";
1511 usb3: usb@48910000 {
1512 compatible = "snps,dwc3";
1513 reg = <0x48910000 0x17000>;
1514 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1517 interrupt-names = "peripheral",
1520 maximum-speed = "high-speed";
1522 snps,dis_u3_susphy_quirk;
1523 snps,dis_u2_susphy_quirk;
1528 compatible = "ti,am3352-elm";
1529 reg = <0x48078000 0xfc0>; /* device IO registers */
1530 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1532 status = "disabled";
1535 gpmc: gpmc@50000000 {
1536 compatible = "ti,am3352-gpmc";
1538 reg = <0x50000000 0x37c>; /* device IO registers */
1539 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1540 dmas = <&edma_xbar 4 0>;
1543 gpmc,num-waitpins = <2>;
1544 #address-cells = <2>;
1546 interrupt-controller;
1547 #interrupt-cells = <2>;
1550 status = "disabled";
1554 compatible = "ti,dra7-atl";
1555 reg = <0x4843c000 0x3ff>;
1557 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1558 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1559 clocks = <&atl_gfclk_mux>;
1560 clock-names = "fck";
1561 status = "disabled";
1564 mcasp1: mcasp@48460000 {
1565 compatible = "ti,dra7-mcasp-audio";
1566 ti,hwmods = "mcasp1";
1567 reg = <0x48460000 0x2000>,
1568 <0x45800000 0x1000>;
1569 reg-names = "mpu","dat";
1570 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1572 interrupt-names = "tx", "rx";
1573 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1574 dma-names = "tx", "rx";
1575 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1576 <&mcasp1_ahclkr_mux>;
1577 clock-names = "fck", "ahclkx", "ahclkr";
1578 status = "disabled";
1581 mcasp2: mcasp@48464000 {
1582 compatible = "ti,dra7-mcasp-audio";
1583 ti,hwmods = "mcasp2";
1584 reg = <0x48464000 0x2000>,
1585 <0x45c00000 0x1000>;
1586 reg-names = "mpu","dat";
1587 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1589 interrupt-names = "tx", "rx";
1590 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1591 dma-names = "tx", "rx";
1592 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1593 <&mcasp2_ahclkr_mux>;
1594 clock-names = "fck", "ahclkx", "ahclkr";
1595 status = "disabled";
1598 mcasp3: mcasp@48468000 {
1599 compatible = "ti,dra7-mcasp-audio";
1600 ti,hwmods = "mcasp3";
1601 reg = <0x48468000 0x2000>,
1602 <0x46000000 0x1000>;
1603 reg-names = "mpu","dat";
1604 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1606 interrupt-names = "tx", "rx";
1607 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1608 dma-names = "tx", "rx";
1609 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1610 clock-names = "fck", "ahclkx";
1611 status = "disabled";
1614 mcasp4: mcasp@4846c000 {
1615 compatible = "ti,dra7-mcasp-audio";
1616 ti,hwmods = "mcasp4";
1617 reg = <0x4846c000 0x2000>,
1618 <0x48436000 0x1000>;
1619 reg-names = "mpu","dat";
1620 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1621 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1622 interrupt-names = "tx", "rx";
1623 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1624 dma-names = "tx", "rx";
1625 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1626 clock-names = "fck", "ahclkx";
1627 status = "disabled";
1630 mcasp5: mcasp@48470000 {
1631 compatible = "ti,dra7-mcasp-audio";
1632 ti,hwmods = "mcasp5";
1633 reg = <0x48470000 0x2000>,
1634 <0x4843a000 0x1000>;
1635 reg-names = "mpu","dat";
1636 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1638 interrupt-names = "tx", "rx";
1639 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1640 dma-names = "tx", "rx";
1641 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1642 clock-names = "fck", "ahclkx";
1643 status = "disabled";
1646 mcasp6: mcasp@48474000 {
1647 compatible = "ti,dra7-mcasp-audio";
1648 ti,hwmods = "mcasp6";
1649 reg = <0x48474000 0x2000>,
1650 <0x4844c000 0x1000>;
1651 reg-names = "mpu","dat";
1652 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1654 interrupt-names = "tx", "rx";
1655 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1656 dma-names = "tx", "rx";
1657 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1658 clock-names = "fck", "ahclkx";
1659 status = "disabled";
1662 mcasp7: mcasp@48478000 {
1663 compatible = "ti,dra7-mcasp-audio";
1664 ti,hwmods = "mcasp7";
1665 reg = <0x48478000 0x2000>,
1666 <0x48450000 0x1000>;
1667 reg-names = "mpu","dat";
1668 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1669 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1670 interrupt-names = "tx", "rx";
1671 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1672 dma-names = "tx", "rx";
1673 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1674 clock-names = "fck", "ahclkx";
1675 status = "disabled";
1678 mcasp8: mcasp@4847c000 {
1679 compatible = "ti,dra7-mcasp-audio";
1680 ti,hwmods = "mcasp8";
1681 reg = <0x4847c000 0x2000>,
1682 <0x48454000 0x1000>;
1683 reg-names = "mpu","dat";
1684 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1686 interrupt-names = "tx", "rx";
1687 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1688 dma-names = "tx", "rx";
1689 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1690 clock-names = "fck", "ahclkx";
1691 status = "disabled";
1694 crossbar_mpu: crossbar@4a002a48 {
1695 compatible = "ti,irq-crossbar";
1696 reg = <0x4a002a48 0x130>;
1697 interrupt-controller;
1698 interrupt-parent = <&wakeupgen>;
1699 #interrupt-cells = <3>;
1700 ti,max-irqs = <160>;
1701 ti,max-crossbar-sources = <MAX_SOURCES>;
1703 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1704 ti,irqs-skip = <10 133 139 140>;
1705 ti,irqs-safe-map = <0>;
1708 mac: ethernet@48484000 {
1709 compatible = "ti,dra7-cpsw","ti,cpsw";
1711 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1712 clock-names = "fck", "cpts";
1713 cpdma_channels = <8>;
1714 ale_entries = <1024>;
1715 bd_ram_size = <0x2000>;
1717 mac_control = <0x20>;
1720 cpts_clock_mult = <0x784CFE14>;
1721 cpts_clock_shift = <29>;
1722 reg = <0x48484000 0x1000
1724 #address-cells = <1>;
1728 * Do not allow gating of cpsw clock as workaround
1729 * for errata i877. Keeping internal clock disabled
1730 * causes the device switching characteristics
1731 * to degrade over time and eventually fail to meet
1732 * the data manual delay time/skew specs.
1742 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1747 syscon = <&scm_conf>;
1748 status = "disabled";
1750 davinci_mdio: mdio@48485000 {
1751 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1752 #address-cells = <1>;
1754 ti,hwmods = "davinci_mdio";
1755 bus_freq = <1000000>;
1756 reg = <0x48485000 0x100>;
1759 cpsw_emac0: slave@48480200 {
1760 /* Filled in by U-Boot */
1761 mac-address = [ 00 00 00 00 00 00 ];
1764 cpsw_emac1: slave@48480300 {
1765 /* Filled in by U-Boot */
1766 mac-address = [ 00 00 00 00 00 00 ];
1769 phy_sel: cpsw-phy-sel@4a002554 {
1770 compatible = "ti,dra7xx-cpsw-phy-sel";
1771 reg= <0x4a002554 0x4>;
1772 reg-names = "gmii-sel";
1776 dcan1: can@4ae3c000 {
1777 compatible = "ti,dra7-d_can";
1778 ti,hwmods = "dcan1";
1779 reg = <0x4ae3c000 0x2000>;
1780 syscon-raminit = <&scm_conf 0x558 0>;
1781 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1782 clocks = <&dcan1_sys_clk_mux>;
1783 status = "disabled";
1786 dcan2: can@48480000 {
1787 compatible = "ti,dra7-d_can";
1788 ti,hwmods = "dcan2";
1789 reg = <0x48480000 0x2000>;
1790 syscon-raminit = <&scm_conf 0x558 1>;
1791 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1792 clocks = <&sys_clkin1>;
1793 status = "disabled";
1797 compatible = "ti,dra7-dss";
1798 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1799 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1800 status = "disabled";
1801 ti,hwmods = "dss_core";
1802 /* CTRL_CORE_DSS_PLL_CONTROL */
1803 syscon-pll-ctrl = <&scm_conf 0x538>;
1804 #address-cells = <1>;
1809 compatible = "ti,dra7-dispc";
1810 reg = <0x58001000 0x1000>;
1811 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1812 ti,hwmods = "dss_dispc";
1813 clocks = <&dss_dss_clk>;
1814 clock-names = "fck";
1815 /* CTRL_CORE_SMA_SW_1 */
1816 syscon-pol = <&scm_conf 0x534>;
1819 hdmi: encoder@58060000 {
1820 compatible = "ti,dra7-hdmi";
1821 reg = <0x58040000 0x200>,
1824 <0x58060000 0x19000>;
1825 reg-names = "wp", "pll", "phy", "core";
1826 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1827 status = "disabled";
1828 ti,hwmods = "dss_hdmi";
1829 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1830 clock-names = "fck", "sys_clk";
1834 epwmss0: epwmss@4843e000 {
1835 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1836 reg = <0x4843e000 0x30>;
1837 ti,hwmods = "epwmss0";
1838 #address-cells = <1>;
1840 status = "disabled";
1843 ehrpwm0: pwm@4843e200 {
1844 compatible = "ti,dra746-ehrpwm",
1847 reg = <0x4843e200 0x80>;
1848 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1849 clock-names = "tbclk", "fck";
1850 status = "disabled";
1853 ecap0: ecap@4843e100 {
1854 compatible = "ti,dra746-ecap",
1857 reg = <0x4843e100 0x80>;
1858 clocks = <&l4_root_clk_div>;
1859 clock-names = "fck";
1860 status = "disabled";
1864 epwmss1: epwmss@48440000 {
1865 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1866 reg = <0x48440000 0x30>;
1867 ti,hwmods = "epwmss1";
1868 #address-cells = <1>;
1870 status = "disabled";
1873 ehrpwm1: pwm@48440200 {
1874 compatible = "ti,dra746-ehrpwm",
1877 reg = <0x48440200 0x80>;
1878 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1879 clock-names = "tbclk", "fck";
1880 status = "disabled";
1883 ecap1: ecap@48440100 {
1884 compatible = "ti,dra746-ecap",
1887 reg = <0x48440100 0x80>;
1888 clocks = <&l4_root_clk_div>;
1889 clock-names = "fck";
1890 status = "disabled";
1894 epwmss2: epwmss@48442000 {
1895 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1896 reg = <0x48442000 0x30>;
1897 ti,hwmods = "epwmss2";
1898 #address-cells = <1>;
1900 status = "disabled";
1903 ehrpwm2: pwm@48442200 {
1904 compatible = "ti,dra746-ehrpwm",
1907 reg = <0x48442200 0x80>;
1908 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1909 clock-names = "tbclk", "fck";
1910 status = "disabled";
1913 ecap2: ecap@48442100 {
1914 compatible = "ti,dra746-ecap",
1917 reg = <0x48442100 0x80>;
1918 clocks = <&l4_root_clk_div>;
1919 clock-names = "fck";
1920 status = "disabled";
1924 aes1: aes@4b500000 {
1925 compatible = "ti,omap4-aes";
1927 reg = <0x4b500000 0xa0>;
1928 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1929 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1930 dma-names = "tx", "rx";
1931 clocks = <&l3_iclk_div>;
1932 clock-names = "fck";
1935 aes2: aes@4b700000 {
1936 compatible = "ti,omap4-aes";
1938 reg = <0x4b700000 0xa0>;
1939 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1940 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1941 dma-names = "tx", "rx";
1942 clocks = <&l3_iclk_div>;
1943 clock-names = "fck";
1947 compatible = "ti,omap4-des";
1949 reg = <0x480a5000 0xa0>;
1950 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1951 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1952 dma-names = "tx", "rx";
1953 clocks = <&l3_iclk_div>;
1954 clock-names = "fck";
1957 sham: sham@53100000 {
1958 compatible = "ti,omap5-sham";
1960 reg = <0x4b101000 0x300>;
1961 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1962 dmas = <&edma_xbar 119 0>;
1964 clocks = <&l3_iclk_div>;
1965 clock-names = "fck";
1969 compatible = "ti,omap4-rng";
1971 reg = <0x48090000 0x2000>;
1972 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1973 clocks = <&l3_iclk_div>;
1974 clock-names = "fck";
1978 thermal_zones: thermal-zones {
1979 #include "omap4-cpu-thermal.dtsi"
1980 #include "omap5-gpu-thermal.dtsi"
1981 #include "omap5-core-thermal.dtsi"
1982 #include "dra7-dspeve-thermal.dtsi"
1983 #include "dra7-iva-thermal.dtsi"
1989 polling-delay = <500>; /* milliseconds */
1992 /include/ "dra7xx-clocks.dtsi"