1 &l4_cfg { /* 0x4a000000 */
2 compatible = "ti,dra7-l4-cfg", "simple-bus";
3 reg = <0x4a000000 0x800>,
6 reg-names = "ap", "la", "ia0";
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
14 compatible = "simple-bus";
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
19 <0x00001000 0x00001000 0x001000>, /* ap 2 */
20 <0x00002000 0x00002000 0x002000>, /* ap 3 */
21 <0x00004000 0x00004000 0x001000>, /* ap 4 */
22 <0x00005000 0x00005000 0x001000>, /* ap 5 */
23 <0x00006000 0x00006000 0x001000>, /* ap 6 */
24 <0x00008000 0x00008000 0x002000>, /* ap 7 */
25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
26 <0x00056000 0x00056000 0x001000>, /* ap 9 */
27 <0x00057000 0x00057000 0x001000>, /* ap 10 */
28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
29 <0x00060000 0x00060000 0x001000>, /* ap 12 */
30 <0x00080000 0x00080000 0x008000>, /* ap 13 */
31 <0x00088000 0x00088000 0x001000>, /* ap 14 */
32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
35 <0x000da000 0x000da000 0x001000>, /* ap 18 */
36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
37 <0x000de000 0x000de000 0x001000>, /* ap 20 */
38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
44 <0x00090000 0x00090000 0x008000>, /* ap 59 */
45 <0x00098000 0x00098000 0x001000>; /* ap 60 */
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
48 compatible = "ti,sysc-omap4", "ti,sysc";
53 ranges = <0x0 0x2000 0x2000>;
56 compatible = "ti,dra7-scm-core", "simple-bus";
60 ranges = <0 0 0x2000>;
62 scm_conf: scm_conf@0 {
63 compatible = "syscon", "simple-bus";
67 ranges = <0 0x0 0x1400>;
69 pbias_regulator: pbias_regulator@e00 {
70 compatible = "ti,pbias-dra7", "ti,pbias-omap";
73 pbias_mmc_reg: pbias_mmc_omap5 {
74 regulator-name = "pbias_mmc_omap5";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
80 phy_gmii_sel: phy-gmii-sel {
81 compatible = "ti,dra7xx-phy-gmii-sel";
86 scm_conf_clocks: clocks {
92 dra7_pmx_core: pinmux@1400 {
93 compatible = "ti,dra7-padconf",
95 reg = <0x1400 0x0468>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x3fffffff>;
105 scm_conf1: scm_conf@1c04 {
106 compatible = "syscon";
107 reg = <0x1c04 0x0020>;
111 scm_conf_pcie: scm_conf@1c24 {
112 compatible = "syscon";
113 reg = <0x1c24 0x0024>;
116 sdma_xbar: dma-router@b78 {
117 compatible = "ti,dra7-dma-crossbar";
120 dma-requests = <205>;
121 ti,dma-safe-map = <0>;
122 dma-masters = <&sdma>;
125 edma_xbar: dma-router@c78 {
126 compatible = "ti,dra7-dma-crossbar";
129 dma-requests = <204>;
130 ti,dma-safe-map = <0>;
131 dma-masters = <&edma>;
136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
137 compatible = "ti,sysc-omap4", "ti,sysc";
140 #address-cells = <1>;
142 ranges = <0x0 0x5000 0x1000>;
144 cm_core_aon: cm_core_aon@0 {
145 compatible = "ti,dra7-cm-core-aon",
147 #address-cells = <1>;
150 ranges = <0 0 0x2000>;
152 cm_core_aon_clocks: clocks {
153 #address-cells = <1>;
157 cm_core_aon_clockdomains: clockdomains {
162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
163 compatible = "ti,sysc-omap4", "ti,sysc";
166 #address-cells = <1>;
168 ranges = <0x0 0x8000 0x2000>;
171 compatible = "ti,dra7-cm-core", "simple-bus";
172 #address-cells = <1>;
175 ranges = <0 0 0x3000>;
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
182 cm_core_clockdomains: clockdomains {
187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
188 compatible = "ti,sysc-omap2", "ti,sysc";
189 ti,hwmods = "dma_system";
193 reg-names = "rev", "sysc", "syss";
194 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
196 SYSC_OMAP2_SOFTRESET |
197 SYSC_OMAP2_AUTOIDLE)>;
198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
201 <SYSC_IDLE_SMART_WKUP>;
202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205 <SYSC_IDLE_SMART_WKUP>;
207 /* Domains (P, C): core_pwrdm, dma_clkdm */
208 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
210 #address-cells = <1>;
212 ranges = <0x0 0x56000 0x1000>;
214 sdma: dma-controller@0 {
215 compatible = "ti,omap4430-sdma";
217 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223 dma-requests = <127>;
227 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
228 compatible = "ti,sysc";
230 #address-cells = <1>;
232 ranges = <0x0 0x5e000 0x2000>;
235 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
236 compatible = "ti,sysc-omap2", "ti,sysc";
237 ti,hwmods = "ocp2scp1";
241 reg-names = "rev", "sysc", "syss";
242 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
243 SYSC_OMAP2_AUTOIDLE)>;
244 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
248 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
249 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
251 #address-cells = <1>;
253 ranges = <0x0 0x80000 0x8000>;
256 compatible = "ti,omap-ocp2scp";
257 #address-cells = <1>;
259 ranges = <0 0 0x8000>;
262 usb2_phy1: phy@4000 {
263 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
264 reg = <0x4000 0x400>;
265 syscon-phy-power = <&scm_conf 0x300>;
266 clocks = <&usb_phy1_always_on_clk32k>,
267 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
268 clock-names = "wkupclk",
273 usb2_phy2: phy@5000 {
274 compatible = "ti,dra7x-usb2-phy2",
276 reg = <0x5000 0x400>;
277 syscon-phy-power = <&scm_conf 0xe74>;
278 clocks = <&usb_phy2_always_on_clk32k>,
279 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
280 clock-names = "wkupclk",
285 usb3_phy1: phy@4400 {
286 compatible = "ti,omap-usb3";
290 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
291 syscon-phy-power = <&scm_conf 0x370>;
292 clocks = <&usb_phy3_always_on_clk32k>,
294 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
295 clock-names = "wkupclk",
303 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
304 compatible = "ti,sysc-omap2", "ti,sysc";
305 ti,hwmods = "ocp2scp3";
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311 SYSC_OMAP2_AUTOIDLE)>;
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
319 #address-cells = <1>;
321 ranges = <0x0 0x90000 0x8000>;
324 compatible = "ti,omap-ocp2scp";
325 #address-cells = <1>;
327 ranges = <0 0 0x8000>;
330 pcie1_phy: pciephy@4000 {
331 compatible = "ti,phy-pipe3-pcie";
332 reg = <0x4000 0x80>, /* phy_rx */
333 <0x4400 0x64>; /* phy_tx */
334 reg-names = "phy_rx", "phy_tx";
335 syscon-phy-power = <&scm_conf_pcie 0x1c>;
336 syscon-pcs = <&scm_conf_pcie 0x10>;
337 clocks = <&dpll_pcie_ref_ck>,
338 <&dpll_pcie_ref_m2ldo_ck>,
339 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
342 <&optfclk_pciephy_div>,
344 clock-names = "dpll_ref", "dpll_ref_m2",
346 "div-clk", "phy-div", "sysclk";
350 pcie2_phy: pciephy@5000 {
351 compatible = "ti,phy-pipe3-pcie";
352 reg = <0x5000 0x80>, /* phy_rx */
353 <0x5400 0x64>; /* phy_tx */
354 reg-names = "phy_rx", "phy_tx";
355 syscon-phy-power = <&scm_conf_pcie 0x20>;
356 syscon-pcs = <&scm_conf_pcie 0x10>;
357 clocks = <&dpll_pcie_ref_ck>,
358 <&dpll_pcie_ref_m2ldo_ck>,
359 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
362 <&optfclk_pciephy_div>,
364 clock-names = "dpll_ref", "dpll_ref_m2",
366 "div-clk", "phy-div", "sysclk";
372 compatible = "ti,phy-pipe3-sata";
373 reg = <0x6000 0x80>, /* phy_rx */
374 <0x6400 0x64>, /* phy_tx */
375 <0x6800 0x40>; /* pll_ctrl */
376 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
377 syscon-phy-power = <&scm_conf 0x374>;
378 clocks = <&sys_clkin1>,
379 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
380 clock-names = "sysclk", "refclk";
381 syscon-pllreset = <&scm_conf 0x3fc>;
387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
388 compatible = "ti,sysc";
390 #address-cells = <1>;
392 ranges = <0x0 0xa0000 0x8000>;
395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
396 compatible = "ti,sysc-omap4-sr", "ti,sysc";
397 ti,hwmods = "smartreflex_mpu";
400 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
401 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
404 <SYSC_IDLE_SMART_WKUP>;
405 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
406 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
408 #address-cells = <1>;
410 ranges = <0x0 0xd9000 0x1000>;
412 /* SmartReflex child device marked reserved in TRM */
415 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
416 compatible = "ti,sysc-omap4-sr", "ti,sysc";
417 ti,hwmods = "smartreflex_core";
420 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
421 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
424 <SYSC_IDLE_SMART_WKUP>;
425 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
426 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
428 #address-cells = <1>;
430 ranges = <0x0 0xdd000 0x1000>;
432 /* SmartReflex child device marked reserved in TRM */
435 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
436 compatible = "ti,sysc";
438 #address-cells = <1>;
440 ranges = <0x0 0xe0000 0x1000>;
443 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
444 compatible = "ti,sysc-omap4", "ti,sysc";
445 ti,hwmods = "mailbox1";
448 reg-names = "rev", "sysc";
449 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
450 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
453 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
454 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
456 #address-cells = <1>;
458 ranges = <0x0 0xf4000 0x1000>;
460 mailbox1: mailbox@0 {
461 compatible = "ti,omap4-mailbox";
463 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
467 ti,mbox-num-users = <3>;
468 ti,mbox-num-fifos = <8>;
473 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
474 compatible = "ti,sysc-omap2", "ti,sysc";
475 ti,hwmods = "spinlock";
479 reg-names = "rev", "sysc", "syss";
480 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
481 SYSC_OMAP2_SOFTRESET |
482 SYSC_OMAP2_AUTOIDLE)>;
483 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
487 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
488 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
490 #address-cells = <1>;
492 ranges = <0x0 0xf6000 0x1000>;
494 hwspinlock: spinlock@0 {
495 compatible = "ti,omap4-hwspinlock";
502 segment@100000 { /* 0x4a100000 */
503 compatible = "simple-bus";
504 #address-cells = <1>;
506 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
507 <0x00003000 0x00103000 0x001000>, /* ap 28 */
508 <0x00008000 0x00108000 0x001000>, /* ap 29 */
509 <0x00009000 0x00109000 0x001000>, /* ap 30 */
510 <0x00040000 0x00140000 0x010000>, /* ap 31 */
511 <0x00050000 0x00150000 0x001000>, /* ap 32 */
512 <0x00051000 0x00151000 0x001000>, /* ap 33 */
513 <0x00052000 0x00152000 0x001000>, /* ap 34 */
514 <0x00053000 0x00153000 0x001000>, /* ap 35 */
515 <0x00054000 0x00154000 0x001000>, /* ap 36 */
516 <0x00055000 0x00155000 0x001000>, /* ap 37 */
517 <0x00056000 0x00156000 0x001000>, /* ap 38 */
518 <0x00057000 0x00157000 0x001000>, /* ap 39 */
519 <0x00058000 0x00158000 0x001000>, /* ap 40 */
520 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
521 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
522 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
523 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
524 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
525 <0x00060000 0x00160000 0x001000>, /* ap 48 */
526 <0x00061000 0x00161000 0x001000>, /* ap 49 */
527 <0x00062000 0x00162000 0x001000>, /* ap 50 */
528 <0x00063000 0x00163000 0x001000>, /* ap 51 */
529 <0x00064000 0x00164000 0x001000>, /* ap 52 */
530 <0x00065000 0x00165000 0x001000>, /* ap 53 */
531 <0x00066000 0x00166000 0x001000>, /* ap 54 */
532 <0x00067000 0x00167000 0x001000>, /* ap 55 */
533 <0x00068000 0x00168000 0x001000>, /* ap 56 */
534 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
535 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
536 <0x00071000 0x00171000 0x001000>, /* ap 61 */
537 <0x00072000 0x00172000 0x001000>, /* ap 62 */
538 <0x00073000 0x00173000 0x001000>, /* ap 63 */
539 <0x00074000 0x00174000 0x001000>, /* ap 64 */
540 <0x00075000 0x00175000 0x001000>, /* ap 65 */
541 <0x00076000 0x00176000 0x001000>, /* ap 66 */
542 <0x00077000 0x00177000 0x001000>, /* ap 67 */
543 <0x00078000 0x00178000 0x001000>, /* ap 68 */
544 <0x00081000 0x00181000 0x001000>, /* ap 69 */
545 <0x00082000 0x00182000 0x001000>, /* ap 70 */
546 <0x00083000 0x00183000 0x001000>, /* ap 71 */
547 <0x00084000 0x00184000 0x001000>, /* ap 72 */
548 <0x00085000 0x00185000 0x001000>, /* ap 73 */
549 <0x00086000 0x00186000 0x001000>, /* ap 74 */
550 <0x00087000 0x00187000 0x001000>, /* ap 75 */
551 <0x00088000 0x00188000 0x001000>, /* ap 76 */
552 <0x00069000 0x00169000 0x001000>, /* ap 103 */
553 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
554 <0x00079000 0x00179000 0x001000>, /* ap 105 */
555 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
556 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
557 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
558 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
559 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
560 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
561 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
562 <0x00059000 0x00159000 0x001000>, /* ap 125 */
563 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
565 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
566 compatible = "ti,sysc";
568 #address-cells = <1>;
570 ranges = <0x0 0x2000 0x1000>;
573 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
574 compatible = "ti,sysc";
576 #address-cells = <1>;
578 ranges = <0x0 0x8000 0x1000>;
581 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
582 compatible = "ti,sysc";
584 #address-cells = <1>;
586 ranges = <0x0 0x40000 0x10000>;
589 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
590 compatible = "ti,sysc";
592 #address-cells = <1>;
594 ranges = <0x0 0x51000 0x1000>;
597 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
598 compatible = "ti,sysc";
600 #address-cells = <1>;
602 ranges = <0x0 0x53000 0x1000>;
605 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
606 compatible = "ti,sysc";
608 #address-cells = <1>;
610 ranges = <0x0 0x55000 0x1000>;
613 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
614 compatible = "ti,sysc";
616 #address-cells = <1>;
618 ranges = <0x0 0x57000 0x1000>;
621 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
622 compatible = "ti,sysc";
624 #address-cells = <1>;
626 ranges = <0x0 0x59000 0x1000>;
629 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
630 compatible = "ti,sysc";
632 #address-cells = <1>;
634 ranges = <0x0 0x5b000 0x1000>;
637 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
638 compatible = "ti,sysc";
640 #address-cells = <1>;
642 ranges = <0x0 0x5d000 0x1000>;
645 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
646 compatible = "ti,sysc";
648 #address-cells = <1>;
650 ranges = <0x0 0x5f000 0x1000>;
653 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
654 compatible = "ti,sysc";
656 #address-cells = <1>;
658 ranges = <0x0 0x61000 0x1000>;
661 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
662 compatible = "ti,sysc";
664 #address-cells = <1>;
666 ranges = <0x0 0x63000 0x1000>;
669 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
670 compatible = "ti,sysc";
672 #address-cells = <1>;
674 ranges = <0x0 0x65000 0x1000>;
677 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
678 compatible = "ti,sysc";
680 #address-cells = <1>;
682 ranges = <0x0 0x67000 0x1000>;
685 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
686 compatible = "ti,sysc";
688 #address-cells = <1>;
690 ranges = <0x0 0x69000 0x1000>;
693 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
694 compatible = "ti,sysc";
696 #address-cells = <1>;
698 ranges = <0x0 0x6b000 0x1000>;
701 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
702 compatible = "ti,sysc";
704 #address-cells = <1>;
706 ranges = <0x0 0x6d000 0x1000>;
709 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
710 compatible = "ti,sysc";
712 #address-cells = <1>;
714 ranges = <0x0 0x71000 0x1000>;
717 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
718 compatible = "ti,sysc";
720 #address-cells = <1>;
722 ranges = <0x0 0x73000 0x1000>;
725 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
726 compatible = "ti,sysc";
728 #address-cells = <1>;
730 ranges = <0x0 0x75000 0x1000>;
733 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
734 compatible = "ti,sysc";
736 #address-cells = <1>;
738 ranges = <0x0 0x77000 0x1000>;
741 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
742 compatible = "ti,sysc";
744 #address-cells = <1>;
746 ranges = <0x0 0x79000 0x1000>;
749 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
750 compatible = "ti,sysc";
752 #address-cells = <1>;
754 ranges = <0x0 0x7b000 0x1000>;
757 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
758 compatible = "ti,sysc";
760 #address-cells = <1>;
762 ranges = <0x0 0x7d000 0x1000>;
765 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
766 compatible = "ti,sysc";
768 #address-cells = <1>;
770 ranges = <0x0 0x81000 0x1000>;
773 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
774 compatible = "ti,sysc";
776 #address-cells = <1>;
778 ranges = <0x0 0x83000 0x1000>;
781 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
782 compatible = "ti,sysc";
784 #address-cells = <1>;
786 ranges = <0x0 0x85000 0x1000>;
789 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
790 compatible = "ti,sysc";
792 #address-cells = <1>;
794 ranges = <0x0 0x87000 0x1000>;
798 segment@200000 { /* 0x4a200000 */
799 compatible = "simple-bus";
800 #address-cells = <1>;
802 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
803 <0x00019000 0x00219000 0x001000>, /* ap 44 */
804 <0x00000000 0x00200000 0x001000>, /* ap 77 */
805 <0x00001000 0x00201000 0x001000>, /* ap 78 */
806 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
807 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
808 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
809 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
810 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
811 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
812 <0x00010000 0x00210000 0x001000>, /* ap 85 */
813 <0x00011000 0x00211000 0x001000>, /* ap 86 */
814 <0x00012000 0x00212000 0x001000>, /* ap 87 */
815 <0x00013000 0x00213000 0x001000>, /* ap 88 */
816 <0x00014000 0x00214000 0x001000>, /* ap 89 */
817 <0x00015000 0x00215000 0x001000>, /* ap 90 */
818 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
819 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
820 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
821 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
822 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
823 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
824 <0x00020000 0x00220000 0x001000>, /* ap 97 */
825 <0x00021000 0x00221000 0x001000>, /* ap 98 */
826 <0x00024000 0x00224000 0x001000>, /* ap 99 */
827 <0x00025000 0x00225000 0x001000>, /* ap 100 */
828 <0x00026000 0x00226000 0x001000>, /* ap 101 */
829 <0x00027000 0x00227000 0x001000>, /* ap 102 */
830 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
831 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
832 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
833 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
834 <0x00030000 0x00230000 0x001000>, /* ap 113 */
835 <0x00031000 0x00231000 0x001000>, /* ap 114 */
836 <0x00032000 0x00232000 0x001000>, /* ap 115 */
837 <0x00033000 0x00233000 0x001000>, /* ap 116 */
838 <0x00034000 0x00234000 0x001000>, /* ap 117 */
839 <0x00035000 0x00235000 0x001000>, /* ap 118 */
840 <0x00036000 0x00236000 0x001000>, /* ap 119 */
841 <0x00037000 0x00237000 0x001000>, /* ap 120 */
842 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
843 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
845 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
846 compatible = "ti,sysc";
848 #address-cells = <1>;
850 ranges = <0x0 0x0 0x1000>;
853 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
854 compatible = "ti,sysc";
856 #address-cells = <1>;
858 ranges = <0x0 0xa000 0x1000>;
861 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
862 compatible = "ti,sysc";
864 #address-cells = <1>;
866 ranges = <0x0 0xc000 0x1000>;
869 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
870 compatible = "ti,sysc";
872 #address-cells = <1>;
874 ranges = <0x0 0xe000 0x1000>;
877 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
878 compatible = "ti,sysc";
880 #address-cells = <1>;
882 ranges = <0x0 0x10000 0x1000>;
885 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
886 compatible = "ti,sysc";
888 #address-cells = <1>;
890 ranges = <0x0 0x12000 0x1000>;
893 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
894 compatible = "ti,sysc";
896 #address-cells = <1>;
898 ranges = <0x0 0x14000 0x1000>;
901 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
902 compatible = "ti,sysc";
904 #address-cells = <1>;
906 ranges = <0x0 0x18000 0x1000>;
909 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
910 compatible = "ti,sysc";
912 #address-cells = <1>;
914 ranges = <0x0 0x1a000 0x1000>;
917 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
918 compatible = "ti,sysc";
920 #address-cells = <1>;
922 ranges = <0x0 0x1c000 0x1000>;
925 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
926 compatible = "ti,sysc";
928 #address-cells = <1>;
930 ranges = <0x0 0x1e000 0x1000>;
933 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
934 compatible = "ti,sysc";
936 #address-cells = <1>;
938 ranges = <0x0 0x20000 0x1000>;
941 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
942 compatible = "ti,sysc";
944 #address-cells = <1>;
946 ranges = <0x0 0x24000 0x1000>;
949 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
950 compatible = "ti,sysc";
952 #address-cells = <1>;
954 ranges = <0x0 0x26000 0x1000>;
957 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
958 compatible = "ti,sysc";
960 #address-cells = <1>;
962 ranges = <0x0 0x2a000 0x1000>;
965 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
966 compatible = "ti,sysc";
968 #address-cells = <1>;
970 ranges = <0x0 0x2c000 0x1000>;
973 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
974 compatible = "ti,sysc";
976 #address-cells = <1>;
978 ranges = <0x0 0x2e000 0x1000>;
981 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
982 compatible = "ti,sysc";
984 #address-cells = <1>;
986 ranges = <0x0 0x30000 0x1000>;
989 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
990 compatible = "ti,sysc";
992 #address-cells = <1>;
994 ranges = <0x0 0x32000 0x1000>;
997 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
998 compatible = "ti,sysc";
1000 #address-cells = <1>;
1002 ranges = <0x0 0x34000 0x1000>;
1005 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1006 compatible = "ti,sysc";
1007 status = "disabled";
1008 #address-cells = <1>;
1010 ranges = <0x0 0x36000 0x1000>;
1015 &l4_per1 { /* 0x48000000 */
1016 compatible = "ti,dra7-l4-per1", "simple-bus";
1017 reg = <0x48000000 0x800>,
1023 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1024 #address-cells = <1>;
1026 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1027 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1029 segment@0 { /* 0x48000000 */
1030 compatible = "simple-bus";
1031 #address-cells = <1>;
1033 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1034 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1035 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1036 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1037 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1038 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1039 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1040 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1041 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1042 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1043 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1044 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1045 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1046 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1047 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1048 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1049 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1050 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1051 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1052 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1053 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1054 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1055 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1056 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1057 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1058 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1059 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1060 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1061 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1062 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1063 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1064 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1065 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1066 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1067 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1068 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1069 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1070 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1071 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1072 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1073 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1074 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1075 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1076 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1077 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1078 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1079 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1080 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1081 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1082 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1083 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1084 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1085 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1086 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1087 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1088 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1089 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1090 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1091 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1092 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1093 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1094 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1095 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1096 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1097 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1098 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1099 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1100 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1101 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1102 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1103 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1104 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1105 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1106 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1107 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1108 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1109 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1110 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1111 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1112 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1113 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1114 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1115 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1116 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1117 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1119 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1120 compatible = "ti,sysc-omap2", "ti,sysc";
1121 reg = <0x20050 0x4>,
1124 reg-names = "rev", "sysc", "syss";
1125 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1126 SYSC_OMAP2_SOFTRESET |
1127 SYSC_OMAP2_AUTOIDLE)>;
1128 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1131 <SYSC_IDLE_SMART_WKUP>;
1133 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1134 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1135 clock-names = "fck";
1136 #address-cells = <1>;
1138 ranges = <0x0 0x20000 0x1000>;
1141 compatible = "ti,dra742-uart", "ti,omap4-uart";
1143 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1144 clock-frequency = <48000000>;
1145 status = "disabled";
1146 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1147 dma-names = "tx", "rx";
1151 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1152 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1153 ti,hwmods = "timer2";
1154 reg = <0x32000 0x4>,
1156 reg-names = "rev", "sysc";
1157 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1158 SYSC_OMAP4_SOFTRESET)>;
1159 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1162 <SYSC_IDLE_SMART_WKUP>;
1163 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1164 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1165 clock-names = "fck";
1166 #address-cells = <1>;
1168 ranges = <0x0 0x32000 0x1000>;
1171 compatible = "ti,omap5430-timer";
1173 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1174 clock-names = "fck";
1175 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1179 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */
1180 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1181 ti,hwmods = "timer3";
1182 reg = <0x34000 0x4>,
1184 reg-names = "rev", "sysc";
1185 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1186 SYSC_OMAP4_SOFTRESET)>;
1187 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1190 <SYSC_IDLE_SMART_WKUP>;
1191 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1192 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1193 clock-names = "fck";
1194 #address-cells = <1>;
1196 ranges = <0x0 0x34000 0x1000>;
1199 compatible = "ti,omap5430-timer";
1201 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1202 clock-names = "fck";
1203 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1207 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1208 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1209 ti,hwmods = "timer4";
1210 reg = <0x36000 0x4>,
1212 reg-names = "rev", "sysc";
1213 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1214 SYSC_OMAP4_SOFTRESET)>;
1215 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1218 <SYSC_IDLE_SMART_WKUP>;
1219 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1220 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1221 clock-names = "fck";
1222 #address-cells = <1>;
1224 ranges = <0x0 0x36000 0x1000>;
1227 compatible = "ti,omap5430-timer";
1229 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1230 clock-names = "fck";
1231 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1235 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1236 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1237 ti,hwmods = "timer9";
1238 reg = <0x3e000 0x4>,
1240 reg-names = "rev", "sysc";
1241 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1242 SYSC_OMAP4_SOFTRESET)>;
1243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1246 <SYSC_IDLE_SMART_WKUP>;
1247 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1248 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1249 clock-names = "fck";
1250 #address-cells = <1>;
1252 ranges = <0x0 0x3e000 0x1000>;
1255 compatible = "ti,omap5430-timer";
1257 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1258 clock-names = "fck";
1259 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1263 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1264 compatible = "ti,sysc-omap2", "ti,sysc";
1265 reg = <0x51000 0x4>,
1268 reg-names = "rev", "sysc", "syss";
1269 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1270 SYSC_OMAP2_SOFTRESET |
1271 SYSC_OMAP2_AUTOIDLE)>;
1272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1275 <SYSC_IDLE_SMART_WKUP>;
1277 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1278 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1279 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1280 clock-names = "fck", "dbclk";
1281 #address-cells = <1>;
1283 ranges = <0x0 0x51000 0x1000>;
1286 compatible = "ti,omap4-gpio";
1288 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1291 interrupt-controller;
1292 #interrupt-cells = <2>;
1296 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1297 compatible = "ti,sysc-omap2", "ti,sysc";
1298 reg = <0x53000 0x4>,
1301 reg-names = "rev", "sysc", "syss";
1302 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1303 SYSC_OMAP2_SOFTRESET |
1304 SYSC_OMAP2_AUTOIDLE)>;
1305 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1308 <SYSC_IDLE_SMART_WKUP>;
1310 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1311 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1312 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1313 clock-names = "fck", "dbclk";
1314 #address-cells = <1>;
1316 ranges = <0x0 0x53000 0x1000>;
1319 compatible = "ti,omap4-gpio";
1321 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1324 interrupt-controller;
1325 #interrupt-cells = <2>;
1329 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1330 compatible = "ti,sysc-omap2", "ti,sysc";
1331 reg = <0x55000 0x4>,
1334 reg-names = "rev", "sysc", "syss";
1335 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1336 SYSC_OMAP2_SOFTRESET |
1337 SYSC_OMAP2_AUTOIDLE)>;
1338 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1341 <SYSC_IDLE_SMART_WKUP>;
1343 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1344 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1345 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1346 clock-names = "fck", "dbclk";
1347 #address-cells = <1>;
1349 ranges = <0x0 0x55000 0x1000>;
1352 compatible = "ti,omap4-gpio";
1354 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1357 interrupt-controller;
1358 #interrupt-cells = <2>;
1362 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
1363 compatible = "ti,sysc-omap2", "ti,sysc";
1364 reg = <0x57000 0x4>,
1367 reg-names = "rev", "sysc", "syss";
1368 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1369 SYSC_OMAP2_SOFTRESET |
1370 SYSC_OMAP2_AUTOIDLE)>;
1371 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1374 <SYSC_IDLE_SMART_WKUP>;
1376 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1377 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1378 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1379 clock-names = "fck", "dbclk";
1380 #address-cells = <1>;
1382 ranges = <0x0 0x57000 0x1000>;
1385 compatible = "ti,omap4-gpio";
1387 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1390 interrupt-controller;
1391 #interrupt-cells = <2>;
1395 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1396 compatible = "ti,sysc-omap2", "ti,sysc";
1397 reg = <0x59000 0x4>,
1400 reg-names = "rev", "sysc", "syss";
1401 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1402 SYSC_OMAP2_SOFTRESET |
1403 SYSC_OMAP2_AUTOIDLE)>;
1404 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1407 <SYSC_IDLE_SMART_WKUP>;
1409 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1410 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1411 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1412 clock-names = "fck", "dbclk";
1413 #address-cells = <1>;
1415 ranges = <0x0 0x59000 0x1000>;
1418 compatible = "ti,omap4-gpio";
1420 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1428 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1429 compatible = "ti,sysc-omap2", "ti,sysc";
1430 reg = <0x5b000 0x4>,
1433 reg-names = "rev", "sysc", "syss";
1434 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1435 SYSC_OMAP2_SOFTRESET |
1436 SYSC_OMAP2_AUTOIDLE)>;
1437 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1440 <SYSC_IDLE_SMART_WKUP>;
1442 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1443 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1444 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1445 clock-names = "fck", "dbclk";
1446 #address-cells = <1>;
1448 ranges = <0x0 0x5b000 0x1000>;
1451 compatible = "ti,omap4-gpio";
1453 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1456 interrupt-controller;
1457 #interrupt-cells = <2>;
1461 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1462 compatible = "ti,sysc-omap2", "ti,sysc";
1463 reg = <0x5d000 0x4>,
1466 reg-names = "rev", "sysc", "syss";
1467 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1468 SYSC_OMAP2_SOFTRESET |
1469 SYSC_OMAP2_AUTOIDLE)>;
1470 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1473 <SYSC_IDLE_SMART_WKUP>;
1475 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1476 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1477 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1478 clock-names = "fck", "dbclk";
1479 #address-cells = <1>;
1481 ranges = <0x0 0x5d000 0x1000>;
1484 compatible = "ti,omap4-gpio";
1486 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1494 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1495 compatible = "ti,sysc-omap2", "ti,sysc";
1496 reg = <0x60000 0x8>,
1499 reg-names = "rev", "sysc", "syss";
1500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1501 SYSC_OMAP2_ENAWAKEUP |
1502 SYSC_OMAP2_SOFTRESET |
1503 SYSC_OMAP2_AUTOIDLE)>;
1504 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1507 <SYSC_IDLE_SMART_WKUP>;
1509 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1510 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1511 clock-names = "fck";
1512 #address-cells = <1>;
1514 ranges = <0x0 0x60000 0x1000>;
1517 compatible = "ti,omap4-i2c";
1519 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1520 #address-cells = <1>;
1522 status = "disabled";
1526 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1527 compatible = "ti,sysc-omap2", "ti,sysc";
1528 reg = <0x66050 0x4>,
1531 reg-names = "rev", "sysc", "syss";
1532 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1533 SYSC_OMAP2_SOFTRESET |
1534 SYSC_OMAP2_AUTOIDLE)>;
1535 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1538 <SYSC_IDLE_SMART_WKUP>;
1540 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1541 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1542 clock-names = "fck";
1543 #address-cells = <1>;
1545 ranges = <0x0 0x66000 0x1000>;
1548 compatible = "ti,dra742-uart", "ti,omap4-uart";
1550 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1551 clock-frequency = <48000000>;
1552 status = "disabled";
1553 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1554 dma-names = "tx", "rx";
1558 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1559 compatible = "ti,sysc-omap2", "ti,sysc";
1560 reg = <0x68050 0x4>,
1563 reg-names = "rev", "sysc", "syss";
1564 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1565 SYSC_OMAP2_SOFTRESET |
1566 SYSC_OMAP2_AUTOIDLE)>;
1567 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1570 <SYSC_IDLE_SMART_WKUP>;
1572 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1573 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1574 clock-names = "fck";
1575 #address-cells = <1>;
1577 ranges = <0x0 0x68000 0x1000>;
1580 compatible = "ti,dra742-uart", "ti,omap4-uart";
1582 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1583 clock-frequency = <48000000>;
1584 status = "disabled";
1585 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1586 dma-names = "tx", "rx";
1590 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1591 compatible = "ti,sysc-omap2", "ti,sysc";
1592 reg = <0x6a050 0x4>,
1595 reg-names = "rev", "sysc", "syss";
1596 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1597 SYSC_OMAP2_SOFTRESET |
1598 SYSC_OMAP2_AUTOIDLE)>;
1599 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1602 <SYSC_IDLE_SMART_WKUP>;
1604 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1605 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1606 clock-names = "fck";
1607 #address-cells = <1>;
1609 ranges = <0x0 0x6a000 0x1000>;
1612 compatible = "ti,dra742-uart", "ti,omap4-uart";
1614 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1615 clock-frequency = <48000000>;
1616 status = "disabled";
1617 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1618 dma-names = "tx", "rx";
1622 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1623 compatible = "ti,sysc-omap2", "ti,sysc";
1624 reg = <0x6c050 0x4>,
1627 reg-names = "rev", "sysc", "syss";
1628 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1629 SYSC_OMAP2_SOFTRESET |
1630 SYSC_OMAP2_AUTOIDLE)>;
1631 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1634 <SYSC_IDLE_SMART_WKUP>;
1636 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1637 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1638 clock-names = "fck";
1639 #address-cells = <1>;
1641 ranges = <0x0 0x6c000 0x1000>;
1644 compatible = "ti,dra742-uart", "ti,omap4-uart";
1646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1647 clock-frequency = <48000000>;
1648 status = "disabled";
1649 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1650 dma-names = "tx", "rx";
1654 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1655 compatible = "ti,sysc-omap2", "ti,sysc";
1656 reg = <0x6e050 0x4>,
1659 reg-names = "rev", "sysc", "syss";
1660 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1661 SYSC_OMAP2_SOFTRESET |
1662 SYSC_OMAP2_AUTOIDLE)>;
1663 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1666 <SYSC_IDLE_SMART_WKUP>;
1668 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1669 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1670 clock-names = "fck";
1671 #address-cells = <1>;
1673 ranges = <0x0 0x6e000 0x1000>;
1676 compatible = "ti,dra742-uart", "ti,omap4-uart";
1678 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1679 clock-frequency = <48000000>;
1680 status = "disabled";
1681 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1682 dma-names = "tx", "rx";
1686 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1687 compatible = "ti,sysc-omap2", "ti,sysc";
1688 reg = <0x70000 0x8>,
1691 reg-names = "rev", "sysc", "syss";
1692 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1693 SYSC_OMAP2_ENAWAKEUP |
1694 SYSC_OMAP2_SOFTRESET |
1695 SYSC_OMAP2_AUTOIDLE)>;
1696 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1699 <SYSC_IDLE_SMART_WKUP>;
1701 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1702 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1703 clock-names = "fck";
1704 #address-cells = <1>;
1706 ranges = <0x0 0x70000 0x1000>;
1709 compatible = "ti,omap4-i2c";
1711 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1712 #address-cells = <1>;
1714 status = "disabled";
1718 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1719 compatible = "ti,sysc-omap2", "ti,sysc";
1720 reg = <0x72000 0x8>,
1723 reg-names = "rev", "sysc", "syss";
1724 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1725 SYSC_OMAP2_ENAWAKEUP |
1726 SYSC_OMAP2_SOFTRESET |
1727 SYSC_OMAP2_AUTOIDLE)>;
1728 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1731 <SYSC_IDLE_SMART_WKUP>;
1733 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1734 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1735 clock-names = "fck";
1736 #address-cells = <1>;
1738 ranges = <0x0 0x72000 0x1000>;
1741 compatible = "ti,omap4-i2c";
1743 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1744 #address-cells = <1>;
1746 status = "disabled";
1750 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1751 compatible = "ti,sysc-omap2", "ti,sysc";
1753 reg = <0x78000 0x4>,
1756 reg-names = "rev", "sysc", "syss";
1757 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1758 SYSC_OMAP2_SOFTRESET |
1759 SYSC_OMAP2_AUTOIDLE)>;
1760 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1763 <SYSC_IDLE_SMART_WKUP>;
1765 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1766 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1767 clock-names = "fck";
1768 #address-cells = <1>;
1770 ranges = <0x0 0x78000 0x1000>;
1773 compatible = "ti,am3352-elm";
1774 reg = <0x0 0xfc0>; /* device IO registers */
1775 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1776 status = "disabled";
1780 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1781 compatible = "ti,sysc-omap2", "ti,sysc";
1782 reg = <0x7a000 0x8>,
1785 reg-names = "rev", "sysc", "syss";
1786 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1787 SYSC_OMAP2_ENAWAKEUP |
1788 SYSC_OMAP2_SOFTRESET |
1789 SYSC_OMAP2_AUTOIDLE)>;
1790 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1793 <SYSC_IDLE_SMART_WKUP>;
1795 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1796 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1797 clock-names = "fck";
1798 #address-cells = <1>;
1800 ranges = <0x0 0x7a000 0x1000>;
1803 compatible = "ti,omap4-i2c";
1805 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1806 #address-cells = <1>;
1808 status = "disabled";
1812 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1813 compatible = "ti,sysc-omap2", "ti,sysc";
1814 reg = <0x7c000 0x8>,
1817 reg-names = "rev", "sysc", "syss";
1818 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1819 SYSC_OMAP2_ENAWAKEUP |
1820 SYSC_OMAP2_SOFTRESET |
1821 SYSC_OMAP2_AUTOIDLE)>;
1822 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1825 <SYSC_IDLE_SMART_WKUP>;
1827 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1828 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1829 clock-names = "fck";
1830 #address-cells = <1>;
1832 ranges = <0x0 0x7c000 0x1000>;
1835 compatible = "ti,omap4-i2c";
1837 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1838 #address-cells = <1>;
1840 status = "disabled";
1844 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1845 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1846 ti,hwmods = "timer10";
1847 reg = <0x86000 0x4>,
1849 reg-names = "rev", "sysc";
1850 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1851 SYSC_OMAP4_SOFTRESET)>;
1852 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1855 <SYSC_IDLE_SMART_WKUP>;
1856 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1857 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1858 clock-names = "fck";
1859 #address-cells = <1>;
1861 ranges = <0x0 0x86000 0x1000>;
1864 compatible = "ti,omap5430-timer";
1866 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1867 clock-names = "fck";
1868 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1872 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1873 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1874 ti,hwmods = "timer11";
1875 reg = <0x88000 0x4>,
1877 reg-names = "rev", "sysc";
1878 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1879 SYSC_OMAP4_SOFTRESET)>;
1880 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1883 <SYSC_IDLE_SMART_WKUP>;
1884 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1885 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1886 clock-names = "fck";
1887 #address-cells = <1>;
1889 ranges = <0x0 0x88000 0x1000>;
1892 compatible = "ti,omap5430-timer";
1894 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1895 clock-names = "fck";
1896 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1900 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1901 compatible = "ti,sysc-omap2", "ti,sysc";
1903 reg = <0x91fe0 0x4>,
1905 reg-names = "rev", "sysc";
1906 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1907 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1909 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1910 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1911 clock-names = "fck";
1912 #address-cells = <1>;
1914 ranges = <0x0 0x90000 0x2000>;
1917 compatible = "ti,omap4-rng";
1919 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&l3_iclk_div>;
1921 clock-names = "fck";
1925 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1926 compatible = "ti,sysc-omap4", "ti,sysc";
1927 reg = <0x98000 0x4>,
1929 reg-names = "rev", "sysc";
1930 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1931 SYSC_OMAP4_SOFTRESET)>;
1932 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1935 <SYSC_IDLE_SMART_WKUP>;
1936 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1937 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1938 clock-names = "fck";
1939 #address-cells = <1>;
1941 ranges = <0x0 0x98000 0x1000>;
1944 compatible = "ti,omap4-mcspi";
1946 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1947 #address-cells = <1>;
1949 ti,spi-num-cs = <4>;
1950 dmas = <&sdma_xbar 35>,
1958 dma-names = "tx0", "rx0", "tx1", "rx1",
1959 "tx2", "rx2", "tx3", "rx3";
1960 status = "disabled";
1964 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1965 compatible = "ti,sysc-omap4", "ti,sysc";
1966 reg = <0x9a000 0x4>,
1968 reg-names = "rev", "sysc";
1969 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1970 SYSC_OMAP4_SOFTRESET)>;
1971 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1974 <SYSC_IDLE_SMART_WKUP>;
1975 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1976 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1977 clock-names = "fck";
1978 #address-cells = <1>;
1980 ranges = <0x0 0x9a000 0x1000>;
1983 compatible = "ti,omap4-mcspi";
1985 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1986 #address-cells = <1>;
1988 ti,spi-num-cs = <2>;
1989 dmas = <&sdma_xbar 43>,
1993 dma-names = "tx0", "rx0", "tx1", "rx1";
1994 status = "disabled";
1998 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
1999 compatible = "ti,sysc-omap4", "ti,sysc";
2000 reg = <0x9c000 0x4>,
2002 reg-names = "rev", "sysc";
2003 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2004 SYSC_OMAP4_SOFTRESET)>;
2005 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2008 <SYSC_IDLE_SMART_WKUP>;
2009 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2012 <SYSC_IDLE_SMART_WKUP>;
2013 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2014 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2015 clock-names = "fck";
2016 #address-cells = <1>;
2018 ranges = <0x0 0x9c000 0x1000>;
2021 compatible = "ti,dra7-sdhci";
2023 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2024 status = "disabled";
2025 pbias-supply = <&pbias_mmc_reg>;
2026 max-frequency = <192000000>;
2032 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2033 compatible = "ti,sysc";
2034 status = "disabled";
2035 #address-cells = <1>;
2037 ranges = <0x0 0xa2000 0x1000>;
2040 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2041 compatible = "ti,sysc";
2042 status = "disabled";
2043 #address-cells = <1>;
2045 ranges = <0x00000000 0x000a4000 0x00001000>,
2046 <0x00001000 0x000a5000 0x00001000>;
2049 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2050 compatible = "ti,sysc";
2051 status = "disabled";
2052 #address-cells = <1>;
2054 ranges = <0x0 0xa8000 0x4000>;
2057 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2058 compatible = "ti,sysc-omap4", "ti,sysc";
2059 reg = <0xad000 0x4>,
2061 reg-names = "rev", "sysc";
2062 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2063 SYSC_OMAP4_SOFTRESET)>;
2064 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2067 <SYSC_IDLE_SMART_WKUP>;
2068 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2071 <SYSC_IDLE_SMART_WKUP>;
2072 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2073 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2074 clock-names = "fck";
2075 #address-cells = <1>;
2077 ranges = <0x0 0xad000 0x1000>;
2080 compatible = "ti,dra7-sdhci";
2082 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2083 status = "disabled";
2084 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2085 max-frequency = <64000000>;
2086 /* SDMA is not supported */
2087 sdhci-caps-mask = <0x0 0x400000>;
2091 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2092 compatible = "ti,sysc-omap2", "ti,sysc";
2093 ti,hwmods = "hdq1w";
2094 reg = <0xb2000 0x4>,
2097 reg-names = "rev", "sysc", "syss";
2098 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2099 SYSC_OMAP2_AUTOIDLE)>;
2101 ti,no-reset-on-init;
2102 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2103 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2104 clock-names = "fck";
2105 #address-cells = <1>;
2107 ranges = <0x0 0xb2000 0x1000>;
2110 compatible = "ti,omap3-1w";
2112 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2116 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2117 compatible = "ti,sysc-omap4", "ti,sysc";
2118 reg = <0xb4000 0x4>,
2120 reg-names = "rev", "sysc";
2121 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2122 SYSC_OMAP4_SOFTRESET)>;
2123 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2126 <SYSC_IDLE_SMART_WKUP>;
2127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2130 <SYSC_IDLE_SMART_WKUP>;
2131 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2132 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2133 clock-names = "fck";
2134 #address-cells = <1>;
2136 ranges = <0x0 0xb4000 0x1000>;
2139 compatible = "ti,dra7-sdhci";
2141 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2142 status = "disabled";
2143 max-frequency = <192000000>;
2144 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2145 sdhci-caps-mask = <0x7 0x0>;
2152 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2153 compatible = "ti,sysc-omap4", "ti,sysc";
2154 reg = <0xb8000 0x4>,
2156 reg-names = "rev", "sysc";
2157 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2158 SYSC_OMAP4_SOFTRESET)>;
2159 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2162 <SYSC_IDLE_SMART_WKUP>;
2163 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2164 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2165 clock-names = "fck";
2166 #address-cells = <1>;
2168 ranges = <0x0 0xb8000 0x1000>;
2171 compatible = "ti,omap4-mcspi";
2173 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2174 #address-cells = <1>;
2176 ti,spi-num-cs = <2>;
2177 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2178 dma-names = "tx0", "rx0";
2179 status = "disabled";
2183 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2184 compatible = "ti,sysc-omap4", "ti,sysc";
2185 reg = <0xba000 0x4>,
2187 reg-names = "rev", "sysc";
2188 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2189 SYSC_OMAP4_SOFTRESET)>;
2190 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2193 <SYSC_IDLE_SMART_WKUP>;
2194 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2195 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2196 clock-names = "fck";
2197 #address-cells = <1>;
2199 ranges = <0x0 0xba000 0x1000>;
2202 compatible = "ti,omap4-mcspi";
2204 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2205 #address-cells = <1>;
2207 ti,spi-num-cs = <1>;
2208 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2209 dma-names = "tx0", "rx0";
2210 status = "disabled";
2214 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2215 compatible = "ti,sysc-omap4", "ti,sysc";
2216 reg = <0xd1000 0x4>,
2218 reg-names = "rev", "sysc";
2219 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2220 SYSC_OMAP4_SOFTRESET)>;
2221 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2224 <SYSC_IDLE_SMART_WKUP>;
2225 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2228 <SYSC_IDLE_SMART_WKUP>;
2229 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2230 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2231 clock-names = "fck";
2232 #address-cells = <1>;
2234 ranges = <0x0 0xd1000 0x1000>;
2237 compatible = "ti,dra7-sdhci";
2239 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2240 status = "disabled";
2241 max-frequency = <192000000>;
2242 /* SDMA is not supported */
2243 sdhci-caps-mask = <0x0 0x400000>;
2247 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2248 compatible = "ti,sysc";
2249 status = "disabled";
2250 #address-cells = <1>;
2252 ranges = <0x0 0xd5000 0x1000>;
2256 segment@200000 { /* 0x48200000 */
2257 compatible = "simple-bus";
2258 #address-cells = <1>;
2263 &l4_per2 { /* 0x48400000 */
2264 compatible = "ti,dra7-l4-per2", "simple-bus";
2265 reg = <0x48400000 0x800>,
2270 reg-names = "ap", "la", "ia0", "ia1", "ia2";
2271 #address-cells = <1>;
2273 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2274 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2275 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2276 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2277 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2278 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2279 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2280 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2281 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2283 segment@0 { /* 0x48400000 */
2284 compatible = "simple-bus";
2285 #address-cells = <1>;
2287 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2288 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2289 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2290 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2291 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2292 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2293 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2294 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2295 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2296 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2297 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2298 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2299 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2300 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2301 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2302 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2303 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2304 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2305 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2306 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2307 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2308 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2309 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2310 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2311 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2312 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2313 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2314 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2315 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2316 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2317 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2318 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2319 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2320 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2321 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2322 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2323 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2324 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2325 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2326 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2327 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2328 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2329 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2330 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2331 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2332 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2333 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2334 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2335 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2336 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2337 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2338 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2339 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2340 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2341 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2342 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2343 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2344 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2345 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2346 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2347 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2348 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2349 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2350 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2351 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2352 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2353 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2354 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2355 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2356 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2357 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2359 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2360 compatible = "ti,sysc-omap2", "ti,sysc";
2361 reg = <0x20050 0x4>,
2364 reg-names = "rev", "sysc", "syss";
2365 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2366 SYSC_OMAP2_SOFTRESET |
2367 SYSC_OMAP2_AUTOIDLE)>;
2368 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2371 <SYSC_IDLE_SMART_WKUP>;
2373 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2374 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2375 clock-names = "fck";
2376 #address-cells = <1>;
2378 ranges = <0x0 0x20000 0x1000>;
2381 compatible = "ti,dra742-uart", "ti,omap4-uart";
2383 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2384 clock-frequency = <48000000>;
2385 status = "disabled";
2389 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2390 compatible = "ti,sysc-omap2", "ti,sysc";
2391 reg = <0x22050 0x4>,
2394 reg-names = "rev", "sysc", "syss";
2395 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2396 SYSC_OMAP2_SOFTRESET |
2397 SYSC_OMAP2_AUTOIDLE)>;
2398 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2401 <SYSC_IDLE_SMART_WKUP>;
2403 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2404 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2405 clock-names = "fck";
2406 #address-cells = <1>;
2408 ranges = <0x0 0x22000 0x1000>;
2411 compatible = "ti,dra742-uart", "ti,omap4-uart";
2413 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2414 clock-frequency = <48000000>;
2415 status = "disabled";
2419 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2420 compatible = "ti,sysc-omap2", "ti,sysc";
2421 reg = <0x24050 0x4>,
2424 reg-names = "rev", "sysc", "syss";
2425 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2426 SYSC_OMAP2_SOFTRESET |
2427 SYSC_OMAP2_AUTOIDLE)>;
2428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2431 <SYSC_IDLE_SMART_WKUP>;
2433 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2434 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2435 clock-names = "fck";
2436 #address-cells = <1>;
2438 ranges = <0x0 0x24000 0x1000>;
2441 compatible = "ti,dra742-uart", "ti,omap4-uart";
2443 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2444 clock-frequency = <48000000>;
2445 status = "disabled";
2449 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2450 compatible = "ti,sysc";
2451 status = "disabled";
2452 #address-cells = <1>;
2454 ranges = <0x0 0x2c000 0x1000>;
2457 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2458 compatible = "ti,sysc";
2459 status = "disabled";
2460 #address-cells = <1>;
2462 ranges = <0x0 0x36000 0x1000>;
2465 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2466 compatible = "ti,sysc";
2467 status = "disabled";
2468 #address-cells = <1>;
2470 ranges = <0x0 0x3a000 0x1000>;
2473 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2474 compatible = "ti,sysc-omap4", "ti,sysc";
2475 reg = <0x3c000 0x4>;
2477 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2478 clock-names = "fck";
2479 #address-cells = <1>;
2481 ranges = <0x0 0x3c000 0x1000>;
2484 compatible = "ti,dra7-atl";
2486 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2487 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2488 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2489 clock-names = "fck";
2490 status = "disabled";
2494 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2495 compatible = "ti,sysc-omap4", "ti,sysc";
2496 ti,hwmods = "epwmss0";
2497 reg = <0x3e000 0x4>,
2499 reg-names = "rev", "sysc";
2500 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2501 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2504 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2505 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2506 clock-names = "fck";
2507 #address-cells = <1>;
2509 ranges = <0x0 0x3e000 0x1000>;
2512 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2514 #address-cells = <1>;
2516 status = "disabled";
2517 ranges = <0 0 0x1000>;
2520 compatible = "ti,dra746-ecap",
2524 clocks = <&l4_root_clk_div>;
2525 clock-names = "fck";
2526 status = "disabled";
2530 compatible = "ti,dra746-ehrpwm",
2534 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2535 clock-names = "tbclk", "fck";
2536 status = "disabled";
2541 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2542 compatible = "ti,sysc-omap4", "ti,sysc";
2543 ti,hwmods = "epwmss1";
2544 reg = <0x40000 0x4>,
2546 reg-names = "rev", "sysc";
2547 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2548 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2551 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2552 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2553 clock-names = "fck";
2554 #address-cells = <1>;
2556 ranges = <0x0 0x40000 0x1000>;
2559 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2561 #address-cells = <1>;
2563 status = "disabled";
2564 ranges = <0 0 0x1000>;
2567 compatible = "ti,dra746-ecap",
2571 clocks = <&l4_root_clk_div>;
2572 clock-names = "fck";
2573 status = "disabled";
2577 compatible = "ti,dra746-ehrpwm",
2581 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2582 clock-names = "tbclk", "fck";
2583 status = "disabled";
2588 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2589 compatible = "ti,sysc-omap4", "ti,sysc";
2590 ti,hwmods = "epwmss2";
2591 reg = <0x42000 0x4>,
2593 reg-names = "rev", "sysc";
2594 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2595 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2598 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2599 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2600 clock-names = "fck";
2601 #address-cells = <1>;
2603 ranges = <0x0 0x42000 0x1000>;
2606 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2608 #address-cells = <1>;
2610 status = "disabled";
2611 ranges = <0 0 0x1000>;
2614 compatible = "ti,dra746-ecap",
2618 clocks = <&l4_root_clk_div>;
2619 clock-names = "fck";
2620 status = "disabled";
2624 compatible = "ti,dra746-ehrpwm",
2628 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2629 clock-names = "tbclk", "fck";
2630 status = "disabled";
2635 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2636 compatible = "ti,sysc";
2637 status = "disabled";
2638 #address-cells = <1>;
2640 ranges = <0x0 0x46000 0x1000>;
2643 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2644 compatible = "ti,sysc";
2645 status = "disabled";
2646 #address-cells = <1>;
2648 ranges = <0x0 0x48000 0x1000>;
2651 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2652 compatible = "ti,sysc";
2653 status = "disabled";
2654 #address-cells = <1>;
2656 ranges = <0x0 0x4a000 0x1000>;
2659 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2660 compatible = "ti,sysc";
2661 status = "disabled";
2662 #address-cells = <1>;
2664 ranges = <0x0 0x4c000 0x1000>;
2667 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2668 compatible = "ti,sysc";
2669 status = "disabled";
2670 #address-cells = <1>;
2672 ranges = <0x0 0x50000 0x1000>;
2675 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2676 compatible = "ti,sysc";
2677 status = "disabled";
2678 #address-cells = <1>;
2680 ranges = <0x0 0x54000 0x1000>;
2683 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2684 compatible = "ti,sysc";
2685 status = "disabled";
2686 #address-cells = <1>;
2688 ranges = <0x0 0x58000 0x2000>;
2691 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2692 compatible = "ti,sysc";
2693 status = "disabled";
2694 #address-cells = <1>;
2696 ranges = <0x0 0x5b000 0x1000>;
2699 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2700 compatible = "ti,sysc";
2701 status = "disabled";
2702 #address-cells = <1>;
2704 ranges = <0x0 0x5d000 0x1000>;
2707 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2708 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2709 reg = <0x60000 0x4>,
2711 reg-names = "rev", "sysc";
2712 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2715 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2716 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2717 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2718 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2719 clock-names = "fck", "ahclkx", "ahclkr";
2720 #address-cells = <1>;
2722 ranges = <0x0 0x60000 0x2000>,
2723 <0x45800000 0x45800000 0x400000>;
2726 compatible = "ti,dra7-mcasp-audio";
2728 <0x45800000 0x1000>; /* L3 data port */
2729 reg-names = "mpu","dat";
2730 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2731 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2732 interrupt-names = "tx", "rx";
2733 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2734 dma-names = "tx", "rx";
2735 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2736 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2737 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2738 clock-names = "fck", "ahclkx", "ahclkr";
2739 status = "disabled";
2743 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2744 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2745 reg = <0x64000 0x4>,
2747 reg-names = "rev", "sysc";
2748 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2751 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2752 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2753 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2754 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2755 clock-names = "fck", "ahclkx", "ahclkr";
2756 #address-cells = <1>;
2758 ranges = <0x0 0x64000 0x2000>,
2759 <0x45c00000 0x45c00000 0x400000>;
2762 compatible = "ti,dra7-mcasp-audio";
2764 <0x45c00000 0x1000>; /* L3 data port */
2765 reg-names = "mpu","dat";
2766 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2767 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2768 interrupt-names = "tx", "rx";
2769 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2770 dma-names = "tx", "rx";
2771 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2772 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2773 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2774 clock-names = "fck", "ahclkx", "ahclkr";
2775 status = "disabled";
2779 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2780 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2781 reg = <0x68000 0x4>,
2783 reg-names = "rev", "sysc";
2784 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2787 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2788 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2789 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2790 clock-names = "fck", "ahclkx";
2791 #address-cells = <1>;
2793 ranges = <0x0 0x68000 0x2000>,
2794 <0x46000000 0x46000000 0x400000>;
2797 compatible = "ti,dra7-mcasp-audio";
2799 <0x46000000 0x1000>; /* L3 data port */
2800 reg-names = "mpu","dat";
2801 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2803 interrupt-names = "tx", "rx";
2804 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2805 dma-names = "tx", "rx";
2806 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2807 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2808 clock-names = "fck", "ahclkx";
2809 status = "disabled";
2813 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2814 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2815 reg = <0x6c000 0x4>,
2817 reg-names = "rev", "sysc";
2818 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2821 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2822 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2823 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2824 clock-names = "fck", "ahclkx";
2825 #address-cells = <1>;
2827 ranges = <0x0 0x6c000 0x2000>,
2828 <0x48436000 0x48436000 0x400000>;
2831 compatible = "ti,dra7-mcasp-audio";
2833 <0x48436000 0x1000>; /* L3 data port */
2834 reg-names = "mpu","dat";
2835 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2836 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2837 interrupt-names = "tx", "rx";
2838 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2839 dma-names = "tx", "rx";
2840 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2841 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2842 clock-names = "fck", "ahclkx";
2843 status = "disabled";
2847 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2848 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2849 reg = <0x70000 0x4>,
2851 reg-names = "rev", "sysc";
2852 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2855 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2856 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2857 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2858 clock-names = "fck", "ahclkx";
2859 #address-cells = <1>;
2861 ranges = <0x0 0x70000 0x2000>,
2862 <0x4843a000 0x4843a000 0x400000>;
2865 compatible = "ti,dra7-mcasp-audio";
2867 <0x4843a000 0x1000>; /* L3 data port */
2868 reg-names = "mpu","dat";
2869 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2870 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2871 interrupt-names = "tx", "rx";
2872 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2873 dma-names = "tx", "rx";
2874 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2875 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2876 clock-names = "fck", "ahclkx";
2877 status = "disabled";
2881 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2882 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2883 reg = <0x74000 0x4>,
2885 reg-names = "rev", "sysc";
2886 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2889 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2890 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2891 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2892 clock-names = "fck", "ahclkx";
2893 #address-cells = <1>;
2895 ranges = <0x0 0x74000 0x2000>,
2896 <0x4844c000 0x4844c000 0x400000>;
2899 compatible = "ti,dra7-mcasp-audio";
2901 <0x4844c000 0x1000>; /* L3 data port */
2902 reg-names = "mpu","dat";
2903 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2904 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2905 interrupt-names = "tx", "rx";
2906 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2907 dma-names = "tx", "rx";
2908 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2909 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2910 clock-names = "fck", "ahclkx";
2911 status = "disabled";
2915 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2916 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2917 reg = <0x78000 0x4>,
2919 reg-names = "rev", "sysc";
2920 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2923 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2924 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2925 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2926 clock-names = "fck", "ahclkx";
2927 #address-cells = <1>;
2929 ranges = <0x0 0x78000 0x2000>,
2930 <0x48450000 0x48450000 0x400000>;
2933 compatible = "ti,dra7-mcasp-audio";
2935 <0x48450000 0x1000>; /* L3 data port */
2936 reg-names = "mpu","dat";
2937 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2939 interrupt-names = "tx", "rx";
2940 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2941 dma-names = "tx", "rx";
2942 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2943 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2944 clock-names = "fck", "ahclkx";
2945 status = "disabled";
2949 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2950 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2951 reg = <0x7c000 0x4>,
2953 reg-names = "rev", "sysc";
2954 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2957 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2958 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2959 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2960 clock-names = "fck", "ahclkx";
2961 #address-cells = <1>;
2963 ranges = <0x0 0x7c000 0x2000>,
2964 <0x48454000 0x48454000 0x400000>;
2967 compatible = "ti,dra7-mcasp-audio";
2969 <0x48454000 0x1000>; /* L3 data port */
2970 reg-names = "mpu","dat";
2971 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2972 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2973 interrupt-names = "tx", "rx";
2974 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2975 dma-names = "tx", "rx";
2976 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2977 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2978 clock-names = "fck", "ahclkx";
2979 status = "disabled";
2983 target-module@80000 { /* 0x48480000, ap 31 16.0 */
2984 compatible = "ti,sysc-omap4", "ti,sysc";
2985 reg = <0x80020 0x4>;
2987 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
2988 clock-names = "fck";
2989 #address-cells = <1>;
2991 ranges = <0x0 0x80000 0x2000>;
2994 compatible = "ti,dra7-d_can";
2996 syscon-raminit = <&scm_conf 0x558 1>;
2997 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
2998 clocks = <&sys_clkin1>;
2999 status = "disabled";
3003 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3004 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3005 reg = <0x85200 0x4>,
3008 reg-names = "rev", "sysc", "syss";
3010 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3012 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3015 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3016 clock-names = "fck";
3017 #address-cells = <1>;
3019 ranges = <0x0 0x84000 0x4000>;
3021 * Do not allow gating of cpsw clock as workaround
3022 * for errata i877. Keeping internal clock disabled
3023 * causes the device switching characteristics
3024 * to degrade over time and eventually fail to meet
3025 * the data manual delay time/skew specs.
3030 compatible = "ti,dra7-cpsw","ti,cpsw";
3031 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3032 clock-names = "fck", "cpts";
3033 cpdma_channels = <8>;
3034 ale_entries = <1024>;
3035 bd_ram_size = <0x2000>;
3036 mac_control = <0x20>;
3039 cpts_clock_mult = <0x784CFE14>;
3040 cpts_clock_shift = <29>;
3043 #address-cells = <1>;
3052 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3056 ranges = <0 0 0x4000>;
3057 syscon = <&scm_conf>;
3058 status = "disabled";
3060 davinci_mdio: mdio@1000 {
3061 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3062 clocks = <&gmac_main_clk>;
3063 clock-names = "fck";
3064 #address-cells = <1>;
3066 bus_freq = <1000000>;
3067 reg = <0x1000 0x100>;
3070 cpsw_emac0: slave@200 {
3071 /* Filled in by U-Boot */
3072 mac-address = [ 00 00 00 00 00 00 ];
3073 phys = <&phy_gmii_sel 1>;
3076 cpsw_emac1: slave@300 {
3077 /* Filled in by U-Boot */
3078 mac-address = [ 00 00 00 00 00 00 ];
3079 phys = <&phy_gmii_sel 2>;
3086 &l4_per3 { /* 0x48800000 */
3087 compatible = "ti,dra7-l4-per3", "simple-bus";
3088 reg = <0x48800000 0x800>,
3093 reg-names = "ap", "la", "ia0", "ia1", "ia2";
3094 #address-cells = <1>;
3096 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3098 segment@0 { /* 0x48800000 */
3099 compatible = "simple-bus";
3100 #address-cells = <1>;
3102 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3103 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3104 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3105 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3106 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3107 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3108 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3109 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3110 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3111 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3112 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3113 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3114 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3115 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3116 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3117 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3118 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3119 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3120 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3121 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3122 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3123 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3124 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3125 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3126 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3127 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3128 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3129 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3130 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3131 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3132 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3133 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3134 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3135 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3136 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3137 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3138 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3139 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3140 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3141 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3142 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3143 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3144 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3145 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3146 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3147 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3148 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3149 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3150 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3151 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3152 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3153 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3154 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3155 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3156 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3157 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3158 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3159 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3160 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3161 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3162 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3163 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3164 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3165 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3166 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3167 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3168 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3169 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3170 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3171 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3172 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3173 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3174 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3175 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3176 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3177 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3178 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3179 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3180 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3181 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3182 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3183 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3184 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3185 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3186 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3187 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3188 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3189 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3190 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3191 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3192 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3193 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3194 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3195 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3196 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3197 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3198 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3200 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3201 compatible = "ti,sysc-omap4", "ti,sysc";
3202 ti,hwmods = "mailbox13";
3205 reg-names = "rev", "sysc";
3206 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3210 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3211 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3212 clock-names = "fck";
3213 #address-cells = <1>;
3215 ranges = <0x0 0x2000 0x1000>;
3217 mailbox13: mailbox@0 {
3218 compatible = "ti,omap4-mailbox";
3220 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3221 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3222 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3223 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3225 ti,mbox-num-users = <4>;
3226 ti,mbox-num-fifos = <12>;
3227 status = "disabled";
3231 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3232 compatible = "ti,sysc";
3233 status = "disabled";
3234 #address-cells = <1>;
3236 ranges = <0x0 0x4000 0x1000>;
3239 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3240 compatible = "ti,sysc";
3241 status = "disabled";
3242 #address-cells = <1>;
3244 ranges = <0x0 0xa000 0x1000>;
3247 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3248 compatible = "ti,sysc";
3249 status = "disabled";
3250 #address-cells = <1>;
3252 ranges = <0x0 0x10000 0x1000>;
3255 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3256 compatible = "ti,sysc";
3257 status = "disabled";
3258 #address-cells = <1>;
3260 ranges = <0x0 0x16000 0x1000>;
3263 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3264 compatible = "ti,sysc";
3265 status = "disabled";
3266 #address-cells = <1>;
3268 ranges = <0x0 0x1c000 0x1000>;
3271 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3272 compatible = "ti,sysc";
3273 status = "disabled";
3274 #address-cells = <1>;
3276 ranges = <0x0 0x1e000 0x1000>;
3279 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3280 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3281 ti,hwmods = "timer5";
3282 reg = <0x20000 0x4>,
3284 reg-names = "rev", "sysc";
3285 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3286 SYSC_OMAP4_SOFTRESET)>;
3287 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3290 <SYSC_IDLE_SMART_WKUP>;
3291 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3292 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3293 clock-names = "fck";
3294 #address-cells = <1>;
3296 ranges = <0x0 0x20000 0x1000>;
3299 compatible = "ti,omap5430-timer";
3301 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3302 clock-names = "fck";
3303 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3307 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3308 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3309 ti,hwmods = "timer6";
3310 reg = <0x22000 0x4>,
3312 reg-names = "rev", "sysc";
3313 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3314 SYSC_OMAP4_SOFTRESET)>;
3315 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3318 <SYSC_IDLE_SMART_WKUP>;
3319 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3320 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3321 clock-names = "fck";
3322 #address-cells = <1>;
3324 ranges = <0x0 0x22000 0x1000>;
3327 compatible = "ti,omap5430-timer";
3329 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3330 clock-names = "fck";
3331 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3335 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3336 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3337 ti,hwmods = "timer7";
3338 reg = <0x24000 0x4>,
3340 reg-names = "rev", "sysc";
3341 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3342 SYSC_OMAP4_SOFTRESET)>;
3343 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3346 <SYSC_IDLE_SMART_WKUP>;
3347 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3348 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3349 clock-names = "fck";
3350 #address-cells = <1>;
3352 ranges = <0x0 0x24000 0x1000>;
3355 compatible = "ti,omap5430-timer";
3357 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3358 clock-names = "fck";
3359 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3363 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3364 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3365 ti,hwmods = "timer8";
3366 reg = <0x26000 0x4>,
3368 reg-names = "rev", "sysc";
3369 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3370 SYSC_OMAP4_SOFTRESET)>;
3371 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3374 <SYSC_IDLE_SMART_WKUP>;
3375 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3376 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3377 clock-names = "fck";
3378 #address-cells = <1>;
3380 ranges = <0x0 0x26000 0x1000>;
3383 compatible = "ti,omap5430-timer";
3385 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3386 clock-names = "fck";
3387 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3391 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3392 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3393 ti,hwmods = "timer13";
3394 reg = <0x28000 0x4>,
3396 reg-names = "rev", "sysc";
3397 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3398 SYSC_OMAP4_SOFTRESET)>;
3399 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3402 <SYSC_IDLE_SMART_WKUP>;
3403 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3404 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3405 clock-names = "fck";
3406 #address-cells = <1>;
3408 ranges = <0x0 0x28000 0x1000>;
3411 compatible = "ti,omap5430-timer";
3413 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3414 clock-names = "fck";
3415 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3420 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3421 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3422 ti,hwmods = "timer14";
3423 reg = <0x2a000 0x4>,
3425 reg-names = "rev", "sysc";
3426 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3427 SYSC_OMAP4_SOFTRESET)>;
3428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3431 <SYSC_IDLE_SMART_WKUP>;
3432 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3433 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3434 clock-names = "fck";
3435 #address-cells = <1>;
3437 ranges = <0x0 0x2a000 0x1000>;
3440 compatible = "ti,omap5430-timer";
3442 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3443 clock-names = "fck";
3444 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3449 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3450 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3451 ti,hwmods = "timer15";
3452 reg = <0x2c000 0x4>,
3454 reg-names = "rev", "sysc";
3455 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3456 SYSC_OMAP4_SOFTRESET)>;
3457 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3460 <SYSC_IDLE_SMART_WKUP>;
3461 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3462 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3463 clock-names = "fck";
3464 #address-cells = <1>;
3466 ranges = <0x0 0x2c000 0x1000>;
3469 compatible = "ti,omap5430-timer";
3471 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3472 clock-names = "fck";
3473 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3478 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3479 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3480 ti,hwmods = "timer16";
3481 reg = <0x2e000 0x4>,
3483 reg-names = "rev", "sysc";
3484 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3485 SYSC_OMAP4_SOFTRESET)>;
3486 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3489 <SYSC_IDLE_SMART_WKUP>;
3490 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3491 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3492 clock-names = "fck";
3493 #address-cells = <1>;
3495 ranges = <0x0 0x2e000 0x1000>;
3498 compatible = "ti,omap5430-timer";
3500 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3501 clock-names = "fck";
3502 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3507 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3508 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3509 ti,hwmods = "rtcss";
3510 reg = <0x38074 0x4>,
3512 reg-names = "rev", "sysc";
3513 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3516 <SYSC_IDLE_SMART_WKUP>;
3517 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3518 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3519 clock-names = "fck";
3520 #address-cells = <1>;
3522 ranges = <0x0 0x38000 0x1000>;
3525 compatible = "ti,am3352-rtc";
3527 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3529 clocks = <&sys_32k_ck>;
3533 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3534 compatible = "ti,sysc-omap4", "ti,sysc";
3535 ti,hwmods = "mailbox2";
3536 reg = <0x3a000 0x4>,
3538 reg-names = "rev", "sysc";
3539 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3540 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3543 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3544 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3545 clock-names = "fck";
3546 #address-cells = <1>;
3548 ranges = <0x0 0x3a000 0x1000>;
3550 mailbox2: mailbox@0 {
3551 compatible = "ti,omap4-mailbox";
3553 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3558 ti,mbox-num-users = <4>;
3559 ti,mbox-num-fifos = <12>;
3560 status = "disabled";
3564 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3565 compatible = "ti,sysc-omap4", "ti,sysc";
3566 ti,hwmods = "mailbox3";
3567 reg = <0x3c000 0x4>,
3569 reg-names = "rev", "sysc";
3570 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3571 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3574 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3575 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3576 clock-names = "fck";
3577 #address-cells = <1>;
3579 ranges = <0x0 0x3c000 0x1000>;
3581 mailbox3: mailbox@0 {
3582 compatible = "ti,omap4-mailbox";
3584 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3589 ti,mbox-num-users = <4>;
3590 ti,mbox-num-fifos = <12>;
3591 status = "disabled";
3595 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3596 compatible = "ti,sysc-omap4", "ti,sysc";
3597 ti,hwmods = "mailbox4";
3598 reg = <0x3e000 0x4>,
3600 reg-names = "rev", "sysc";
3601 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3602 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3605 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3606 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3607 clock-names = "fck";
3608 #address-cells = <1>;
3610 ranges = <0x0 0x3e000 0x1000>;
3612 mailbox4: mailbox@0 {
3613 compatible = "ti,omap4-mailbox";
3615 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3620 ti,mbox-num-users = <4>;
3621 ti,mbox-num-fifos = <12>;
3622 status = "disabled";
3626 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3627 compatible = "ti,sysc-omap4", "ti,sysc";
3628 ti,hwmods = "mailbox5";
3629 reg = <0x40000 0x4>,
3631 reg-names = "rev", "sysc";
3632 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3633 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3636 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3637 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3638 clock-names = "fck";
3639 #address-cells = <1>;
3641 ranges = <0x0 0x40000 0x1000>;
3643 mailbox5: mailbox@0 {
3644 compatible = "ti,omap4-mailbox";
3646 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3647 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3648 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3649 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3651 ti,mbox-num-users = <4>;
3652 ti,mbox-num-fifos = <12>;
3653 status = "disabled";
3657 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3658 compatible = "ti,sysc-omap4", "ti,sysc";
3659 ti,hwmods = "mailbox6";
3660 reg = <0x42000 0x4>,
3662 reg-names = "rev", "sysc";
3663 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3664 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3667 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3668 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3669 clock-names = "fck";
3670 #address-cells = <1>;
3672 ranges = <0x0 0x42000 0x1000>;
3674 mailbox6: mailbox@0 {
3675 compatible = "ti,omap4-mailbox";
3677 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3678 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3679 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3680 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3682 ti,mbox-num-users = <4>;
3683 ti,mbox-num-fifos = <12>;
3684 status = "disabled";
3688 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3689 compatible = "ti,sysc-omap4", "ti,sysc";
3690 ti,hwmods = "mailbox7";
3691 reg = <0x44000 0x4>,
3693 reg-names = "rev", "sysc";
3694 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3695 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3698 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3699 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3700 clock-names = "fck";
3701 #address-cells = <1>;
3703 ranges = <0x0 0x44000 0x1000>;
3705 mailbox7: mailbox@0 {
3706 compatible = "ti,omap4-mailbox";
3708 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3709 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3710 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3711 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3713 ti,mbox-num-users = <4>;
3714 ti,mbox-num-fifos = <12>;
3715 status = "disabled";
3719 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3720 compatible = "ti,sysc-omap4", "ti,sysc";
3721 ti,hwmods = "mailbox8";
3722 reg = <0x46000 0x4>,
3724 reg-names = "rev", "sysc";
3725 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3726 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3729 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3730 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3731 clock-names = "fck";
3732 #address-cells = <1>;
3734 ranges = <0x0 0x46000 0x1000>;
3736 mailbox8: mailbox@0 {
3737 compatible = "ti,omap4-mailbox";
3739 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3740 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3741 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3742 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3744 ti,mbox-num-users = <4>;
3745 ti,mbox-num-fifos = <12>;
3746 status = "disabled";
3750 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3751 compatible = "ti,sysc";
3752 status = "disabled";
3753 #address-cells = <1>;
3755 ranges = <0x0 0x48000 0x1000>;
3758 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3759 compatible = "ti,sysc";
3760 status = "disabled";
3761 #address-cells = <1>;
3763 ranges = <0x0 0x4a000 0x1000>;
3766 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3767 compatible = "ti,sysc";
3768 status = "disabled";
3769 #address-cells = <1>;
3771 ranges = <0x0 0x4c000 0x1000>;
3774 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3775 compatible = "ti,sysc";
3776 status = "disabled";
3777 #address-cells = <1>;
3779 ranges = <0x0 0x4e000 0x1000>;
3782 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3783 compatible = "ti,sysc";
3784 status = "disabled";
3785 #address-cells = <1>;
3787 ranges = <0x0 0x50000 0x1000>;
3790 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3791 compatible = "ti,sysc";
3792 status = "disabled";
3793 #address-cells = <1>;
3795 ranges = <0x0 0x52000 0x1000>;
3798 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3799 compatible = "ti,sysc";
3800 status = "disabled";
3801 #address-cells = <1>;
3803 ranges = <0x0 0x54000 0x1000>;
3806 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3807 compatible = "ti,sysc";
3808 status = "disabled";
3809 #address-cells = <1>;
3811 ranges = <0x0 0x56000 0x1000>;
3814 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3815 compatible = "ti,sysc";
3816 status = "disabled";
3817 #address-cells = <1>;
3819 ranges = <0x0 0x58000 0x1000>;
3822 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3823 compatible = "ti,sysc";
3824 status = "disabled";
3825 #address-cells = <1>;
3827 ranges = <0x0 0x5a000 0x1000>;
3830 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3831 compatible = "ti,sysc";
3832 status = "disabled";
3833 #address-cells = <1>;
3835 ranges = <0x0 0x5c000 0x1000>;
3838 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3839 compatible = "ti,sysc-omap4", "ti,sysc";
3840 ti,hwmods = "mailbox9";
3841 reg = <0x5e000 0x4>,
3843 reg-names = "rev", "sysc";
3844 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3845 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3848 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3849 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3850 clock-names = "fck";
3851 #address-cells = <1>;
3853 ranges = <0x0 0x5e000 0x1000>;
3855 mailbox9: mailbox@0 {
3856 compatible = "ti,omap4-mailbox";
3858 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3859 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3860 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3861 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3863 ti,mbox-num-users = <4>;
3864 ti,mbox-num-fifos = <12>;
3865 status = "disabled";
3869 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3870 compatible = "ti,sysc-omap4", "ti,sysc";
3871 ti,hwmods = "mailbox10";
3872 reg = <0x60000 0x4>,
3874 reg-names = "rev", "sysc";
3875 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3876 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3879 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3880 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3881 clock-names = "fck";
3882 #address-cells = <1>;
3884 ranges = <0x0 0x60000 0x1000>;
3886 mailbox10: mailbox@0 {
3887 compatible = "ti,omap4-mailbox";
3889 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3890 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3892 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3894 ti,mbox-num-users = <4>;
3895 ti,mbox-num-fifos = <12>;
3896 status = "disabled";
3900 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3901 compatible = "ti,sysc-omap4", "ti,sysc";
3902 ti,hwmods = "mailbox11";
3903 reg = <0x62000 0x4>,
3905 reg-names = "rev", "sysc";
3906 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3907 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3910 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3911 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3912 clock-names = "fck";
3913 #address-cells = <1>;
3915 ranges = <0x0 0x62000 0x1000>;
3917 mailbox11: mailbox@0 {
3918 compatible = "ti,omap4-mailbox";
3920 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3921 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3922 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3923 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3925 ti,mbox-num-users = <4>;
3926 ti,mbox-num-fifos = <12>;
3927 status = "disabled";
3931 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3932 compatible = "ti,sysc-omap4", "ti,sysc";
3933 ti,hwmods = "mailbox12";
3934 reg = <0x64000 0x4>,
3936 reg-names = "rev", "sysc";
3937 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3938 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3941 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3942 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3943 clock-names = "fck";
3944 #address-cells = <1>;
3946 ranges = <0x0 0x64000 0x1000>;
3948 mailbox12: mailbox@0 {
3949 compatible = "ti,omap4-mailbox";
3951 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3952 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3953 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3954 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3956 ti,mbox-num-users = <4>;
3957 ti,mbox-num-fifos = <12>;
3958 status = "disabled";
3962 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3963 compatible = "ti,sysc-omap4", "ti,sysc";
3964 ti,hwmods = "usb_otg_ss1";
3965 reg = <0x80000 0x4>,
3967 reg-names = "rev", "sysc";
3968 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
3969 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3972 <SYSC_IDLE_SMART_WKUP>;
3973 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3976 <SYSC_IDLE_SMART_WKUP>;
3977 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
3978 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
3979 clock-names = "fck";
3980 #address-cells = <1>;
3982 ranges = <0x0 0x80000 0x20000>;
3984 omap_dwc3_1: omap_dwc3_1@0 {
3985 compatible = "ti,dwc3";
3986 reg = <0x0 0x10000>;
3987 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3988 #address-cells = <1>;
3991 ranges = <0 0 0x20000>;
3994 compatible = "snps,dwc3";
3995 reg = <0x10000 0x17000>;
3996 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3997 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3998 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3999 interrupt-names = "peripheral",
4002 phys = <&usb2_phy1>, <&usb3_phy1>;
4003 phy-names = "usb2-phy", "usb3-phy";
4004 maximum-speed = "super-speed";
4006 snps,dis_u3_susphy_quirk;
4007 snps,dis_u2_susphy_quirk;
4012 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4013 compatible = "ti,sysc-omap4", "ti,sysc";
4014 ti,hwmods = "usb_otg_ss2";
4015 reg = <0xc0000 0x4>,
4017 reg-names = "rev", "sysc";
4018 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4019 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4022 <SYSC_IDLE_SMART_WKUP>;
4023 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4026 <SYSC_IDLE_SMART_WKUP>;
4027 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4028 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4029 clock-names = "fck";
4030 #address-cells = <1>;
4032 ranges = <0x0 0xc0000 0x20000>;
4034 omap_dwc3_2: omap_dwc3_2@0 {
4035 compatible = "ti,dwc3";
4036 reg = <0x0 0x10000>;
4037 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4038 #address-cells = <1>;
4041 ranges = <0 0 0x20000>;
4044 compatible = "snps,dwc3";
4045 reg = <0x10000 0x17000>;
4046 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4047 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4048 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4049 interrupt-names = "peripheral",
4052 phys = <&usb2_phy2>;
4053 phy-names = "usb2-phy";
4054 maximum-speed = "high-speed";
4056 snps,dis_u3_susphy_quirk;
4057 snps,dis_u2_susphy_quirk;
4058 snps,dis_metastability_quirk;
4063 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4064 compatible = "ti,sysc-omap4", "ti,sysc";
4065 ti,hwmods = "usb_otg_ss3";
4066 reg = <0x100000 0x4>,
4068 reg-names = "rev", "sysc";
4069 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4070 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4073 <SYSC_IDLE_SMART_WKUP>;
4074 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4077 <SYSC_IDLE_SMART_WKUP>;
4078 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4079 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4080 clock-names = "fck";
4081 #address-cells = <1>;
4083 ranges = <0x0 0x100000 0x20000>;
4085 omap_dwc3_3: omap_dwc3_3@0 {
4086 compatible = "ti,dwc3";
4087 reg = <0x0 0x10000>;
4088 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4089 #address-cells = <1>;
4092 ranges = <0 0 0x20000>;
4093 status = "disabled";
4096 compatible = "snps,dwc3";
4097 reg = <0x10000 0x17000>;
4098 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4099 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4100 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4101 interrupt-names = "peripheral",
4104 maximum-speed = "high-speed";
4106 snps,dis_u3_susphy_quirk;
4107 snps,dis_u2_susphy_quirk;
4112 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
4113 compatible = "ti,sysc-omap4", "ti,sysc";
4114 ti,hwmods = "usb_otg_ss4";
4115 reg = <0x140000 0x4>,
4117 reg-names = "rev", "sysc";
4118 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4119 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4122 <SYSC_IDLE_SMART_WKUP>;
4123 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4126 <SYSC_IDLE_SMART_WKUP>;
4127 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4128 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4129 clock-names = "fck";
4130 #address-cells = <1>;
4132 ranges = <0x0 0x140000 0x20000>;
4135 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4136 compatible = "ti,sysc";
4137 status = "disabled";
4138 #address-cells = <1>;
4140 ranges = <0x0 0x170000 0x10000>;
4143 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4144 compatible = "ti,sysc";
4145 status = "disabled";
4146 #address-cells = <1>;
4148 ranges = <0x0 0x190000 0x10000>;
4151 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4152 compatible = "ti,sysc";
4153 status = "disabled";
4154 #address-cells = <1>;
4156 ranges = <0x0 0x1b0000 0x10000>;
4159 target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
4160 compatible = "ti,sysc";
4161 status = "disabled";
4162 #address-cells = <1>;
4164 ranges = <0x0 0x1d0000 0x10000>;
4169 &l4_wkup { /* 0x4ae00000 */
4170 compatible = "ti,dra7-l4-wkup", "simple-bus";
4171 reg = <0x4ae00000 0x800>,
4173 <0x4ae01000 0x1000>;
4174 reg-names = "ap", "la", "ia0";
4175 #address-cells = <1>;
4177 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4178 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4179 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4180 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4182 segment@0 { /* 0x4ae00000 */
4183 compatible = "simple-bus";
4184 #address-cells = <1>;
4186 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4187 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4188 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4189 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4190 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4191 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4192 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4193 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4194 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4196 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4197 compatible = "ti,sysc-omap2", "ti,sysc";
4198 ti,hwmods = "counter_32k";
4201 reg-names = "rev", "sysc";
4202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4205 <SYSC_IDLE_SMART_WKUP>;
4206 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4207 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4208 clock-names = "fck";
4209 #address-cells = <1>;
4211 ranges = <0x0 0x4000 0x1000>;
4213 counter32k: counter@0 {
4214 compatible = "ti,omap-counter32k";
4219 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4220 compatible = "ti,sysc-omap4", "ti,sysc";
4223 #address-cells = <1>;
4225 ranges = <0x0 0x6000 0x2000>;
4228 compatible = "ti,dra7-prm", "simple-bus";
4230 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4231 #address-cells = <1>;
4233 ranges = <0 0 0x3000>;
4235 prm_clocks: clocks {
4236 #address-cells = <1>;
4240 prm_clockdomains: clockdomains {
4245 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4246 compatible = "ti,sysc-omap4", "ti,sysc";
4249 #address-cells = <1>;
4251 ranges = <0x0 0xc000 0x1000>;
4253 scm_wkup: scm_conf@0 {
4254 compatible = "syscon";
4260 segment@10000 { /* 0x4ae10000 */
4261 compatible = "simple-bus";
4262 #address-cells = <1>;
4264 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4265 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4266 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4267 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4268 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4269 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4270 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4271 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4273 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4274 compatible = "ti,sysc-omap2", "ti,sysc";
4278 reg-names = "rev", "sysc", "syss";
4279 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4280 SYSC_OMAP2_SOFTRESET |
4281 SYSC_OMAP2_AUTOIDLE)>;
4282 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4285 <SYSC_IDLE_SMART_WKUP>;
4287 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4288 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4289 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4290 clock-names = "fck", "dbclk";
4291 #address-cells = <1>;
4293 ranges = <0x0 0x0 0x1000>;
4296 compatible = "ti,omap4-gpio";
4298 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4301 interrupt-controller;
4302 #interrupt-cells = <2>;
4306 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4307 compatible = "ti,sysc-omap2", "ti,sysc";
4308 ti,hwmods = "wd_timer2";
4312 reg-names = "rev", "sysc", "syss";
4313 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4314 SYSC_OMAP2_SOFTRESET)>;
4315 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4318 <SYSC_IDLE_SMART_WKUP>;
4320 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4321 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4322 clock-names = "fck";
4323 #address-cells = <1>;
4325 ranges = <0x0 0x4000 0x1000>;
4328 compatible = "ti,omap3-wdt";
4330 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4334 target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4335 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4336 ti,hwmods = "timer1";
4339 reg-names = "rev", "sysc";
4340 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4341 SYSC_OMAP4_SOFTRESET)>;
4342 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4345 <SYSC_IDLE_SMART_WKUP>;
4346 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4347 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4348 clock-names = "fck";
4349 #address-cells = <1>;
4351 ranges = <0x0 0x8000 0x1000>;
4354 compatible = "ti,omap5430-timer";
4356 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4357 clock-names = "fck";
4358 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4363 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4364 compatible = "ti,sysc";
4365 status = "disabled";
4366 #address-cells = <1>;
4368 ranges = <0x0 0xc000 0x1000>;
4372 segment@20000 { /* 0x4ae20000 */
4373 compatible = "simple-bus";
4374 #address-cells = <1>;
4376 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4377 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4378 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4379 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4380 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4381 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4382 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4383 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4384 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4385 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4386 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4387 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4388 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4389 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4391 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4392 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4393 ti,hwmods = "timer12";
4396 reg-names = "rev", "sysc";
4397 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4398 SYSC_OMAP4_SOFTRESET)>;
4399 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4402 <SYSC_IDLE_SMART_WKUP>;
4403 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4404 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4405 clock-names = "fck";
4406 #address-cells = <1>;
4408 ranges = <0x0 0x0 0x1000>;
4411 compatible = "ti,omap5430-timer";
4413 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4419 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4420 compatible = "ti,sysc";
4421 status = "disabled";
4422 #address-cells = <1>;
4424 ranges = <0x0 0x2000 0x1000>;
4427 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4428 compatible = "ti,sysc";
4429 status = "disabled";
4430 #address-cells = <1>;
4432 ranges = <0x00000000 0x00006000 0x00001000>,
4433 <0x00001000 0x00007000 0x00000400>,
4434 <0x00002000 0x00008000 0x00000800>,
4435 <0x00002800 0x00008800 0x00000200>,
4436 <0x00002a00 0x00008a00 0x00000100>,
4437 <0x00003000 0x00009000 0x00000100>;
4440 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4441 compatible = "ti,sysc-omap2", "ti,sysc";
4445 reg-names = "rev", "sysc", "syss";
4446 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4447 SYSC_OMAP2_SOFTRESET |
4448 SYSC_OMAP2_AUTOIDLE)>;
4449 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4452 <SYSC_IDLE_SMART_WKUP>;
4454 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4455 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4456 clock-names = "fck";
4457 #address-cells = <1>;
4459 ranges = <0x0 0xb000 0x1000>;
4462 compatible = "ti,dra742-uart", "ti,omap4-uart";
4464 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4465 clock-frequency = <48000000>;
4466 status = "disabled";
4470 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4471 compatible = "ti,sysc";
4472 status = "disabled";
4473 #address-cells = <1>;
4475 ranges = <0x0 0xf000 0x1000>;
4479 segment@30000 { /* 0x4ae30000 */
4480 compatible = "simple-bus";
4481 #address-cells = <1>;
4483 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4484 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4485 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4486 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4487 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4488 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4489 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4490 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4491 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4492 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4493 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4494 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4495 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4497 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4498 compatible = "ti,sysc";
4499 status = "disabled";
4500 #address-cells = <1>;
4502 ranges = <0x0 0x1000 0x1000>;
4505 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4506 compatible = "ti,sysc";
4507 status = "disabled";
4508 #address-cells = <1>;
4510 ranges = <0x0 0x3000 0x1000>;
4513 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4514 compatible = "ti,sysc";
4515 status = "disabled";
4516 #address-cells = <1>;
4518 ranges = <0x0 0x5000 0x1000>;
4521 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4522 compatible = "ti,sysc";
4523 status = "disabled";
4524 #address-cells = <1>;
4526 ranges = <0x0 0x7000 0x1000>;
4529 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4530 compatible = "ti,sysc";
4531 status = "disabled";
4532 #address-cells = <1>;
4534 ranges = <0x0 0x9000 0x1000>;
4537 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4538 compatible = "ti,sysc-omap4", "ti,sysc";
4541 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4542 clock-names = "fck";
4543 #address-cells = <1>;
4545 ranges = <0x0 0xc000 0x2000>;
4548 compatible = "ti,dra7-d_can";
4550 syscon-raminit = <&scm_conf 0x558 0>;
4551 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4552 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4553 status = "disabled";