arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
  22         };
  23
  24         evm_3v3_sd: fixedregulator-sd {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "evm_3v3_sd";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 enable-active-high;
  30                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  31         };
  32
  33         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_3v3_sw";
  36                 vin-supply = <&sysen1>;
  37                 regulator-min-microvolt = <3300000>;
  38                 regulator-max-microvolt = <3300000>;
  39         };
  40
  41         aic_dvdd: fixedregulator-aic_dvdd {
  42                 /* TPS77018DBVT */
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "aic_dvdd";
  45                 vin-supply = <&evm_3v3_sw>;
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48         };
  49
  50         extcon_usb1: extcon_usb1 {
  51                 compatible = "linux,extcon-usb-gpio";
  52                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  53         };
  54
  55         extcon_usb2: extcon_usb2 {
  56                 compatible = "linux,extcon-usb-gpio";
  57                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  58         };
  59
  60         vtt_fixed: fixedregulator-vtt {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "vtt_fixed";
  63                 regulator-min-microvolt = <1350000>;
  64                 regulator-max-microvolt = <1350000>;
  65                 regulator-always-on;
  66                 regulator-boot-on;
  67                 enable-active-high;
  68                 vin-supply = <&sysen2>;
  69                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  70         };
  71
  72         sound0: sound0 {
  73                 compatible = "simple-audio-card";
  74                 simple-audio-card,name = "DRA7xx-EVM";
  75                 simple-audio-card,widgets =
  76                         "Headphone", "Headphone Jack",
  77                         "Line", "Line Out",
  78                         "Microphone", "Mic Jack",
  79                         "Line", "Line In";
  80                 simple-audio-card,routing =
  81                         "Headphone Jack",       "HPLOUT",
  82                         "Headphone Jack",       "HPROUT",
  83                         "Line Out",             "LLOUT",
  84                         "Line Out",             "RLOUT",
  85                         "MIC3L",                "Mic Jack",
  86                         "MIC3R",                "Mic Jack",
  87                         "Mic Jack",             "Mic Bias",
  88                         "LINE1L",               "Line In",
  89                         "LINE1R",               "Line In";
  90                 simple-audio-card,format = "dsp_b";
  91                 simple-audio-card,bitclock-master = <&sound0_master>;
  92                 simple-audio-card,frame-master = <&sound0_master>;
  93                 simple-audio-card,bitclock-inversion;
  94
  95                 sound0_master: simple-audio-card,cpu {
  96                         sound-dai = <&mcasp3>;
  97                         system-clock-frequency = <5644800>;
  98                 };
  99
 100                 simple-audio-card,codec {
 101                         sound-dai = <&tlv320aic3106>;
 102                         clocks = <&atl_clkin2_ck>;
 103                 };
 104         };
 105
 106         leds {
 107                 compatible = "gpio-leds";
 108                 led0 {
 109                         label = "dra7:usr1";
 110                         gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
 111                         default-state = "off";
 112                 };
 113
 114                 led1 {
 115                         label = "dra7:usr2";
 116                         gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
 117                         default-state = "off";
 118                 };
 119
 120                 led2 {
 121                         label = "dra7:usr3";
 122                         gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
 123                         default-state = "off";
 124                 };
 125
 126                 led3 {
 127                         label = "dra7:usr4";
 128                         gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         gpio_keys {
 134                 compatible = "gpio-keys";
 135                 #address-cells = <1>;
 136                 #size-cells = <0>;
 137                 autorepeat;
 138
 139                 USER1 {
 140                         label = "btnUser1";
 141                         linux,code = <BTN_0>;
 142                         gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
 143                 };
 144
 145                 USER2 {
 146                         label = "btnUser2";
 147                         linux,code = <BTN_1>;
 148                         gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
 149                 };
 150         };
 151 };
 152
 153 &dra7_pmx_core {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&vtt_pin>;
 156
 157         vtt_pin: pinmux_vtt_pin {
 158                 pinctrl-single,pins = <
 159                         DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
 160                 >;
 161         };
 162
 163         i2c1_pins: pinmux_i2c1_pins {
 164                 pinctrl-single,pins = <
 165                         DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
 166                         DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
 167                 >;
 168         };
 169
 170         i2c2_pins: pinmux_i2c2_pins {
 171                 pinctrl-single,pins = <
 172                         DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 173                         DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 174                 >;
 175         };
 176
 177         i2c3_pins: pinmux_i2c3_pins {
 178                 pinctrl-single,pins = <
 179                         DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
 180                         DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
 181                 >;
 182         };
 183
 184         mcspi1_pins: pinmux_mcspi1_pins {
 185                 pinctrl-single,pins = <
 186                         DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
 187                         DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 188                         DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 189                         DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 190                         DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 191                         DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 192                 >;
 193         };
 194
 195         mcspi2_pins: pinmux_mcspi2_pins {
 196                 pinctrl-single,pins = <
 197                         DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 198                         DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 199                         DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 200                         DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 201                 >;
 202         };
 203
 204         uart1_pins: pinmux_uart1_pins {
 205                 pinctrl-single,pins = <
 206                         DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 207                         DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 208                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 209                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 210                 >;
 211         };
 212
 213         uart2_pins: pinmux_uart2_pins {
 214                 pinctrl-single,pins = <
 215                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 216                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
 217                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 218                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 219                 >;
 220         };
 221
 222         uart3_pins: pinmux_uart3_pins {
 223                 pinctrl-single,pins = <
 224                         DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 225                         DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 226                 >;
 227         };
 228
 229         usb1_pins: pinmux_usb1_pins {
 230                 pinctrl-single,pins = <
 231                         DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 232                 >;
 233         };
 234
 235         usb2_pins: pinmux_usb2_pins {
 236                 pinctrl-single,pins = <
 237                         DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 238                 >;
 239         };
 240
 241         nand_flash_x16: nand_flash_x16 {
 242                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 243                  * So NAND flash requires following switch settings:
 244                  * SW5.1 (NAND_BOOTn) = ON (LOW)
 245                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 246                  */
 247                 pinctrl-single,pins = <
 248                         DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad0     */
 249                         DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad1     */
 250                         DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad2     */
 251                         DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad3     */
 252                         DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad4     */
 253                         DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad5     */
 254                         DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad6     */
 255                         DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad7     */
 256                         DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad8     */
 257                         DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad9     */
 258                         DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad10    */
 259                         DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad11    */
 260                         DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad12    */
 261                         DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad13    */
 262                         DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad14    */
 263                         DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0)       /* gpmc_ad15    */
 264                         DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP  | MUX_MODE0)        /* gpmc_wait0   */
 265                         DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0)       /* gpmc_wen     */
 266                         DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* gpmc_csn0    */
 267                         DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0)       /* gpmc_advn_ale */
 268                         DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0)       /* gpmc_oen_ren  */
 269                         DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_be0n_cle */
 270                 >;
 271         };
 272
 273         cpsw_default: cpsw_default {
 274                 pinctrl-single,pins = <
 275                         /* Slave 1 */
 276                         DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txc.rgmii0_txc */
 277                         DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txctl.rgmii0_txctl */
 278                         DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_td3.rgmii0_txd3 */
 279                         DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd2.rgmii0_txd2 */
 280                         DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd1.rgmii0_txd1 */
 281                         DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)       /* rgmii0_txd0.rgmii0_txd0 */
 282                         DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxc.rgmii0_rxc */
 283                         DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxctl.rgmii0_rxctl */
 284                         DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd3.rgmii0_rxd3 */
 285                         DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd2.rgmii0_rxd2 */
 286                         DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd1.rgmii0_rxd1 */
 287                         DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)        /* rgmii0_rxd0.rgmii0_rxd0 */
 288
 289                         /* Slave 2 */
 290                         DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d12.rgmii1_txc */
 291                         DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d13.rgmii1_tctl */
 292                         DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d14.rgmii1_td3 */
 293                         DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d15.rgmii1_td2 */
 294                         DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d16.rgmii1_td1 */
 295                         DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d17.rgmii1_td0 */
 296                         DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)        /* vin2a_d18.rgmii1_rclk */
 297                         DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)        /* vin2a_d19.rgmii1_rctl */
 298                         DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)        /* vin2a_d20.rgmii1_rd3 */
 299                         DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)        /* vin2a_d21.rgmii1_rd2 */
 300                         DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)        /* vin2a_d22.rgmii1_rd1 */
 301                         DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)        /* vin2a_d23.rgmii1_rd0 */
 302                 >;
 303
 304         };
 305
 306         cpsw_sleep: cpsw_sleep {
 307                 pinctrl-single,pins = <
 308                         /* Slave 1 */
 309                         DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
 310                         DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
 311                         DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
 312                         DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
 313                         DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
 314                         DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
 315                         DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
 316                         DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
 317                         DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
 318                         DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
 319                         DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
 320                         DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
 321
 322                         /* Slave 2 */
 323                         DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
 324                         DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
 325                         DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
 326                         DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
 327                         DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
 328                         DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
 329                         DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
 330                         DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
 331                         DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
 332                         DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
 333                         DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
 334                         DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
 335                 >;
 336         };
 337
 338         davinci_mdio_default: davinci_mdio_default {
 339                 pinctrl-single,pins = <
 340                         DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* mdio_d.mdio_d */
 341                         DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
 342                 >;
 343         };
 344
 345         davinci_mdio_sleep: davinci_mdio_sleep {
 346                 pinctrl-single,pins = <
 347                         DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
 348                         DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
 349                 >;
 350         };
 351
 352         dcan1_pins_default: dcan1_pins_default {
 353                 pinctrl-single,pins = <
 354                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 355                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 356                 >;
 357         };
 358
 359         dcan1_pins_sleep: dcan1_pins_sleep {
 360                 pinctrl-single,pins = <
 361                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 362                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 363                 >;
 364         };
 365
 366         atl_pins: pinmux_atl_pins {
 367                 pinctrl-single,pins = <
 368                         DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)       /* xref_clk1.atl_clk1 */
 369                         DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)       /* xref_clk2.atl_clk2 */
 370                 >;
 371         };
 372
 373         mcasp3_pins: pinmux_mcasp3_pins {
 374                 pinctrl-single,pins = <
 375                         DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_aclkx */
 376                         DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_fsx */
 377                         DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_axr0 */
 378                         DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcasp3_axr1 */
 379                 >;
 380         };
 381
 382         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 383                 pinctrl-single,pins = <
 384                         DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
 385                         DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
 386                         DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
 387                         DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
 388                 >;
 389         };
 390 };
 391
 392 &i2c1 {
 393         status = "okay";
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&i2c1_pins>;
 396         clock-frequency = <400000>;
 397
 398         tps659038: tps659038@58 {
 399                 compatible = "ti,tps659038";
 400                 reg = <0x58>;
 401                 ti,palmas-override-powerhold;
 402                 ti,system-power-controller;
 403
 404                 tps659038_pmic {
 405                         compatible = "ti,tps659038-pmic";
 406
 407                         regulators {
 408                                 smps123_reg: smps123 {
 409                                         /* VDD_MPU */
 410                                         regulator-name = "smps123";
 411                                         regulator-min-microvolt = < 850000>;
 412                                         regulator-max-microvolt = <1250000>;
 413                                         regulator-always-on;
 414                                         regulator-boot-on;
 415                                 };
 416
 417                                 smps45_reg: smps45 {
 418                                         /* VDD_DSPEVE */
 419                                         regulator-name = "smps45";
 420                                         regulator-min-microvolt = < 850000>;
 421                                         regulator-max-microvolt = <1250000>;
 422                                         regulator-always-on;
 423                                         regulator-boot-on;
 424                                 };
 425
 426                                 smps6_reg: smps6 {
 427                                         /* VDD_GPU - over VDD_SMPS6 */
 428                                         regulator-name = "smps6";
 429                                         regulator-min-microvolt = <850000>;
 430                                         regulator-max-microvolt = <1250000>;
 431                                         regulator-always-on;
 432                                         regulator-boot-on;
 433                                 };
 434
 435                                 smps7_reg: smps7 {
 436                                         /* CORE_VDD */
 437                                         regulator-name = "smps7";
 438                                         regulator-min-microvolt = <850000>;
 439                                         regulator-max-microvolt = <1150000>;
 440                                         regulator-always-on;
 441                                         regulator-boot-on;
 442                                 };
 443
 444                                 smps8_reg: smps8 {
 445                                         /* VDD_IVAHD */
 446                                         regulator-name = "smps8";
 447                                         regulator-min-microvolt = < 850000>;
 448                                         regulator-max-microvolt = <1250000>;
 449                                         regulator-always-on;
 450                                         regulator-boot-on;
 451                                 };
 452
 453                                 smps9_reg: smps9 {
 454                                         /* VDDS1V8 */
 455                                         regulator-name = "smps9";
 456                                         regulator-min-microvolt = <1800000>;
 457                                         regulator-max-microvolt = <1800000>;
 458                                         regulator-always-on;
 459                                         regulator-boot-on;
 460                                 };
 461
 462                                 ldo1_reg: ldo1 {
 463                                         /* LDO1_OUT --> SDIO  */
 464                                         regulator-name = "ldo1";
 465                                         regulator-min-microvolt = <1800000>;
 466                                         regulator-max-microvolt = <3300000>;
 467                                         regulator-always-on;
 468                                         regulator-boot-on;
 469                                 };
 470
 471                                 ldo2_reg: ldo2 {
 472                                         /* VDD_RTCIO */
 473                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 474                                         regulator-name = "ldo2";
 475                                         regulator-min-microvolt = <3300000>;
 476                                         regulator-max-microvolt = <3300000>;
 477                                         regulator-always-on;
 478                                         regulator-boot-on;
 479                                 };
 480
 481                                 ldo3_reg: ldo3 {
 482                                         /* VDDA_1V8_PHY */
 483                                         regulator-name = "ldo3";
 484                                         regulator-min-microvolt = <1800000>;
 485                                         regulator-max-microvolt = <1800000>;
 486                                         regulator-always-on;
 487                                         regulator-boot-on;
 488                                 };
 489
 490                                 ldo9_reg: ldo9 {
 491                                         /* VDD_RTC */
 492                                         regulator-name = "ldo9";
 493                                         regulator-min-microvolt = <1050000>;
 494                                         regulator-max-microvolt = <1050000>;
 495                                         regulator-always-on;
 496                                         regulator-boot-on;
 497                                         regulator-allow-bypass;
 498                                 };
 499
 500                                 ldoln_reg: ldoln {
 501                                         /* VDDA_1V8_PLL */
 502                                         regulator-name = "ldoln";
 503                                         regulator-min-microvolt = <1800000>;
 504                                         regulator-max-microvolt = <1800000>;
 505                                         regulator-always-on;
 506                                         regulator-boot-on;
 507                                 };
 508
 509                                 ldousb_reg: ldousb {
 510                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 511                                         regulator-name = "ldousb";
 512                                         regulator-min-microvolt = <3300000>;
 513                                         regulator-max-microvolt = <3300000>;
 514                                         regulator-boot-on;
 515                                 };
 516
 517                                 /* REGEN1 is unused */
 518
 519                                 regen2: regen2 {
 520                                         /* Needed for PMIC internal resources */
 521                                         regulator-name = "regen2";
 522                                         regulator-boot-on;
 523                                         regulator-always-on;
 524                                 };
 525
 526                                 /* REGEN3 is unused */
 527
 528                                 sysen1: sysen1 {
 529                                         /* PMIC_REGEN_3V3 */
 530                                         regulator-name = "sysen1";
 531                                         regulator-boot-on;
 532                                         regulator-always-on;
 533                                 };
 534
 535                                 sysen2: sysen2 {
 536                                         /* PMIC_REGEN_DDR */
 537                                         regulator-name = "sysen2";
 538                                         regulator-boot-on;
 539                                         regulator-always-on;
 540                                 };
 541                         };
 542                 };
 543         };
 544
 545         pcf_lcd: gpio@20 {
 546                 compatible = "ti,pcf8575", "nxp,pcf8575";
 547                 reg = <0x20>;
 548                 gpio-controller;
 549                 #gpio-cells = <2>;
 550                 interrupt-parent = <&gpio6>;
 551                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 552                 interrupt-controller;
 553                 #interrupt-cells = <2>;
 554         };
 555
 556         pcf_gpio_21: gpio@21 {
 557                 compatible = "ti,pcf8575", "nxp,pcf8575";
 558                 reg = <0x21>;
 559                 lines-initial-states = <0x1408>;
 560                 gpio-controller;
 561                 #gpio-cells = <2>;
 562                 interrupt-parent = <&gpio6>;
 563                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 564                 interrupt-controller;
 565                 #interrupt-cells = <2>;
 566         };
 567
 568         tlv320aic3106: tlv320aic3106@19 {
 569                 #sound-dai-cells = <0>;
 570                 compatible = "ti,tlv320aic3106";
 571                 reg = <0x19>;
 572                 adc-settle-ms = <40>;
 573                 ai3x-micbias-vg = <1>;          /* 2.0V */
 574                 status = "okay";
 575
 576                 /* Regulators */
 577                 AVDD-supply = <&evm_3v3_sw>;
 578                 IOVDD-supply = <&evm_3v3_sw>;
 579                 DRVDD-supply = <&evm_3v3_sw>;
 580                 DVDD-supply = <&aic_dvdd>;
 581         };
 582 };
 583
 584 &i2c2 {
 585         status = "okay";
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&i2c2_pins>;
 588         clock-frequency = <400000>;
 589
 590         pcf_hdmi: gpio@26 {
 591                 compatible = "ti,pcf8575", "nxp,pcf8575";
 592                 reg = <0x26>;
 593                 gpio-controller;
 594                 #gpio-cells = <2>;
 595                 p1 {
 596                         /* vin6_sel_s0: high: VIN6, low: audio */
 597                         gpio-hog;
 598                         gpios = <1 GPIO_ACTIVE_HIGH>;
 599                         output-low;
 600                         line-name = "vin6_sel_s0";
 601                 };
 602         };
 603 };
 604
 605 &i2c3 {
 606         status = "okay";
 607         pinctrl-names = "default";
 608         pinctrl-0 = <&i2c3_pins>;
 609         clock-frequency = <400000>;
 610 };
 611
 612 &mcspi1 {
 613         status = "okay";
 614         pinctrl-names = "default";
 615         pinctrl-0 = <&mcspi1_pins>;
 616 };
 617
 618 &mcspi2 {
 619         status = "okay";
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&mcspi2_pins>;
 622 };
 623
 624 &uart1 {
 625         status = "okay";
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&uart1_pins>;
 628         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 629                               <&dra7_pmx_core 0x3e0>;
 630 };
 631
 632 &uart2 {
 633         status = "okay";
 634         pinctrl-names = "default";
 635         pinctrl-0 = <&uart2_pins>;
 636 };
 637
 638 &uart3 {
 639         status = "okay";
 640         pinctrl-names = "default";
 641         pinctrl-0 = <&uart3_pins>;
 642 };
 643
 644 &mmc1 {
 645         status = "okay";
 646         vmmc-supply = <&evm_3v3_sd>;
 647         vmmc_aux-supply = <&ldo1_reg>;
 648         bus-width = <4>;
 649         /*
 650          * SDCD signal is not being used here - using the fact that GPIO mode
 651          * is always hardwired.
 652          */
 653         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 654 };
 655
 656 &mmc2 {
 657         status = "okay";
 658         vmmc-supply = <&evm_3v3_sw>;
 659         bus-width = <8>;
 660 };
 661
 662 &cpu0 {
 663         cpu0-supply = <&smps123_reg>;
 664 };
 665
 666 &qspi {
 667         status = "okay";
 668
 669         spi-max-frequency = <76800000>;
 670         m25p80@0 {
 671                 compatible = "s25fl256s1";
 672                 spi-max-frequency = <76800000>;
 673                 reg = <0>;
 674                 spi-tx-bus-width = <1>;
 675                 spi-rx-bus-width = <4>;
 676                 #address-cells = <1>;
 677                 #size-cells = <1>;
 678
 679                 /* MTD partition table.
 680                  * The ROM checks the first four physical blocks
 681                  * for a valid file to boot and the flash here is
 682                  * 64KiB block size.
 683                  */
 684                 partition@0 {
 685                         label = "QSPI.SPL";
 686                         reg = <0x00000000 0x000010000>;
 687                 };
 688                 partition@1 {
 689                         label = "QSPI.SPL.backup1";
 690                         reg = <0x00010000 0x00010000>;
 691                 };
 692                 partition@2 {
 693                         label = "QSPI.SPL.backup2";
 694                         reg = <0x00020000 0x00010000>;
 695                 };
 696                 partition@3 {
 697                         label = "QSPI.SPL.backup3";
 698                         reg = <0x00030000 0x00010000>;
 699                 };
 700                 partition@4 {
 701                         label = "QSPI.u-boot";
 702                         reg = <0x00040000 0x00100000>;
 703                 };
 704                 partition@5 {
 705                         label = "QSPI.u-boot-spl-os";
 706                         reg = <0x00140000 0x00080000>;
 707                 };
 708                 partition@6 {
 709                         label = "QSPI.u-boot-env";
 710                         reg = <0x001c0000 0x00010000>;
 711                 };
 712                 partition@7 {
 713                         label = "QSPI.u-boot-env.backup1";
 714                         reg = <0x001d0000 0x0010000>;
 715                 };
 716                 partition@8 {
 717                         label = "QSPI.kernel";
 718                         reg = <0x001e0000 0x0800000>;
 719                 };
 720                 partition@9 {
 721                         label = "QSPI.file-system";
 722                         reg = <0x009e0000 0x01620000>;
 723                 };
 724         };
 725 };
 726
 727 &omap_dwc3_1 {
 728         extcon = <&extcon_usb1>;
 729 };
 730
 731 &omap_dwc3_2 {
 732         extcon = <&extcon_usb2>;
 733 };
 734
 735 &usb1 {
 736         dr_mode = "peripheral";
 737         pinctrl-names = "default";
 738         pinctrl-0 = <&usb1_pins>;
 739 };
 740
 741 &usb2 {
 742         dr_mode = "host";
 743         pinctrl-names = "default";
 744         pinctrl-0 = <&usb2_pins>;
 745 };
 746
 747 &elm {
 748         status = "okay";
 749 };
 750
 751 &gpmc {
 752         status = "okay";
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&nand_flash_x16>;
 755         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 756         nand@0,0 {
 757                 compatible = "ti,omap2-nand";
 758                 reg = <0 0 4>;          /* device IO registers */
 759                 interrupt-parent = <&gpmc>;
 760                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 761                              <1 IRQ_TYPE_NONE>; /* termcount */
 762                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 763                 ti,nand-ecc-opt = "bch8";
 764                 ti,elm-id = <&elm>;
 765                 nand-bus-width = <16>;
 766                 gpmc,device-width = <2>;
 767                 gpmc,sync-clk-ps = <0>;
 768                 gpmc,cs-on-ns = <0>;
 769                 gpmc,cs-rd-off-ns = <80>;
 770                 gpmc,cs-wr-off-ns = <80>;
 771                 gpmc,adv-on-ns = <0>;
 772                 gpmc,adv-rd-off-ns = <60>;
 773                 gpmc,adv-wr-off-ns = <60>;
 774                 gpmc,we-on-ns = <10>;
 775                 gpmc,we-off-ns = <50>;
 776                 gpmc,oe-on-ns = <4>;
 777                 gpmc,oe-off-ns = <40>;
 778                 gpmc,access-ns = <40>;
 779                 gpmc,wr-access-ns = <80>;
 780                 gpmc,rd-cycle-ns = <80>;
 781                 gpmc,wr-cycle-ns = <80>;
 782                 gpmc,bus-turnaround-ns = <0>;
 783                 gpmc,cycle2cycle-delay-ns = <0>;
 784                 gpmc,clk-activation-ns = <0>;
 785                 gpmc,wr-data-mux-bus-ns = <0>;
 786                 /* MTD partition table */
 787                 /* All SPL-* partitions are sized to minimal length
 788                  * which can be independently programmable. For
 789                  * NAND flash this is equal to size of erase-block */
 790                 #address-cells = <1>;
 791                 #size-cells = <1>;
 792                 partition@0 {
 793                         label = "NAND.SPL";
 794                         reg = <0x00000000 0x000020000>;
 795                 };
 796                 partition@1 {
 797                         label = "NAND.SPL.backup1";
 798                         reg = <0x00020000 0x00020000>;
 799                 };
 800                 partition@2 {
 801                         label = "NAND.SPL.backup2";
 802                         reg = <0x00040000 0x00020000>;
 803                 };
 804                 partition@3 {
 805                         label = "NAND.SPL.backup3";
 806                         reg = <0x00060000 0x00020000>;
 807                 };
 808                 partition@4 {
 809                         label = "NAND.u-boot-spl-os";
 810                         reg = <0x00080000 0x00040000>;
 811                 };
 812                 partition@5 {
 813                         label = "NAND.u-boot";
 814                         reg = <0x000c0000 0x00100000>;
 815                 };
 816                 partition@6 {
 817                         label = "NAND.u-boot-env";
 818                         reg = <0x001c0000 0x00020000>;
 819                 };
 820                 partition@7 {
 821                         label = "NAND.u-boot-env.backup1";
 822                         reg = <0x001e0000 0x00020000>;
 823                 };
 824                 partition@8 {
 825                         label = "NAND.kernel";
 826                         reg = <0x00200000 0x00800000>;
 827                 };
 828                 partition@9 {
 829                         label = "NAND.file-system";
 830                         reg = <0x00a00000 0x0f600000>;
 831                 };
 832         };
 833 };
 834
 835 &usb2_phy1 {
 836         phy-supply = <&ldousb_reg>;
 837 };
 838
 839 &usb2_phy2 {
 840         phy-supply = <&ldousb_reg>;
 841 };
 842
 843 &gpio7 {
 844         ti,no-reset-on-init;
 845         ti,no-idle-on-init;
 846 };
 847
 848 &mac {
 849         status = "okay";
 850         pinctrl-names = "default", "sleep";
 851         pinctrl-0 = <&cpsw_default>;
 852         pinctrl-1 = <&cpsw_sleep>;
 853         dual_emac;
 854 };
 855
 856 &cpsw_emac0 {
 857         phy_id = <&davinci_mdio>, <2>;
 858         phy-mode = "rgmii";
 859         dual_emac_res_vlan = <1>;
 860 };
 861
 862 &cpsw_emac1 {
 863         phy_id = <&davinci_mdio>, <3>;
 864         phy-mode = "rgmii";
 865         dual_emac_res_vlan = <2>;
 866 };
 867
 868 &davinci_mdio {
 869         pinctrl-names = "default", "sleep";
 870         pinctrl-0 = <&davinci_mdio_default>;
 871         pinctrl-1 = <&davinci_mdio_sleep>;
 872 };
 873
 874 &dcan1 {
 875         status = "ok";
 876         pinctrl-names = "default", "sleep", "active";
 877         pinctrl-0 = <&dcan1_pins_sleep>;
 878         pinctrl-1 = <&dcan1_pins_sleep>;
 879         pinctrl-2 = <&dcan1_pins_default>;
 880 };
 881
 882 &atl {
 883         pinctrl-names = "default";
 884         pinctrl-0 = <&atl_pins>;
 885
 886         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 887                           <&atl_gfclk_mux>,
 888                           <&dpll_abe_ck>,
 889                           <&dpll_abe_m2x2_ck>,
 890                           <&atl_clkin2_ck>;
 891         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 892         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 893
 894         status = "okay";
 895
 896         atl2 {
 897                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 898                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 899         };
 900 };
 901
 902 &mcasp3 {
 903         #sound-dai-cells = <0>;
 904         pinctrl-names = "default", "sleep";
 905         pinctrl-0 = <&mcasp3_pins>;
 906         pinctrl-1 = <&mcasp3_sleep_pins>;
 907
 908         assigned-clocks = <&mcasp3_ahclkx_mux>;
 909         assigned-clock-parents = <&atl_clkin2_ck>;
 910
 911         status = "okay";
 912
 913         op-mode = <0>;          /* MCASP_IIS_MODE */
 914         tdm-slots = <2>;
 915         /* 4 serializer */
 916         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 917                 1 2 0 0
 918         >;
 919         tx-num-evt = <32>;
 920         rx-num-evt = <32>;
 921 };
 922
 923 &mailbox5 {
 924         status = "okay";
 925         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 926                 status = "okay";
 927         };
 928         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 929                 status = "okay";
 930         };
 931 };
 932
 933 &mailbox6 {
 934         status = "okay";
 935         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 936                 status = "okay";
 937         };
 938         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 939                 status = "okay";
 940         };
 941 };