arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  22         };
  23
  24         evm_3v3_sd: fixedregulator-sd {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "evm_3v3_sd";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 enable-active-high;
  30                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  31         };
  32
  33         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "evm_3v3_sw";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38         };
  39
  40         aic_dvdd: fixedregulator-aic_dvdd {
  41                 /* TPS77018DBVT */
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "aic_dvdd";
  44                 vin-supply = <&evm_3v3_sw>;
  45                 regulator-min-microvolt = <1800000>;
  46                 regulator-max-microvolt = <1800000>;
  47         };
  48
  49         extcon_usb1: extcon_usb1 {
  50                 compatible = "linux,extcon-usb-gpio";
  51                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  52         };
  53
  54         extcon_usb2: extcon_usb2 {
  55                 compatible = "linux,extcon-usb-gpio";
  56                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  57         };
  58
  59         vtt_fixed: fixedregulator-vtt {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "vtt_fixed";
  62                 regulator-min-microvolt = <1350000>;
  63                 regulator-max-microvolt = <1350000>;
  64                 regulator-always-on;
  65                 regulator-boot-on;
  66                 enable-active-high;
  67                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  68         };
  69
  70         sound0: sound@0 {
  71                 compatible = "simple-audio-card";
  72                 simple-audio-card,name = "DRA7xx-EVM";
  73                 simple-audio-card,widgets =
  74                         "Headphone", "Headphone Jack",
  75                         "Line", "Line Out",
  76                         "Microphone", "Mic Jack",
  77                         "Line", "Line In";
  78                 simple-audio-card,routing =
  79                         "Headphone Jack",       "HPLOUT",
  80                         "Headphone Jack",       "HPROUT",
  81                         "Line Out",             "LLOUT",
  82                         "Line Out",             "RLOUT",
  83                         "MIC3L",                "Mic Jack",
  84                         "MIC3R",                "Mic Jack",
  85                         "Mic Jack",             "Mic Bias",
  86                         "LINE1L",               "Line In",
  87                         "LINE1R",               "Line In";
  88                 simple-audio-card,format = "dsp_b";
  89                 simple-audio-card,bitclock-master = <&sound0_master>;
  90                 simple-audio-card,frame-master = <&sound0_master>;
  91                 simple-audio-card,bitclock-inversion;
  92
  93                 sound0_master: simple-audio-card,cpu {
  94                         sound-dai = <&mcasp3>;
  95                         system-clock-frequency = <5644800>;
  96                 };
  97
  98                 simple-audio-card,codec {
  99                         sound-dai = <&tlv320aic3106>;
 100                         clocks = <&atl_clkin2_ck>;
 101                 };
 102         };
 103
 104         leds {
 105                 compatible = "gpio-leds";
 106                 led@0 {
 107                         label = "dra7:usr1";
 108                         gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
 109                         default-state = "off";
 110                 };
 111
 112                 led@1 {
 113                         label = "dra7:usr2";
 114                         gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
 115                         default-state = "off";
 116                 };
 117
 118                 led@2 {
 119                         label = "dra7:usr3";
 120                         gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
 121                         default-state = "off";
 122                 };
 123
 124                 led@3 {
 125                         label = "dra7:usr4";
 126                         gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
 127                         default-state = "off";
 128                 };
 129         };
 130
 131         gpio_keys {
 132                 compatible = "gpio-keys";
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135                 autorepeat;
 136
 137                 USER1 {
 138                         label = "btnUser1";
 139                         linux,code = <BTN_0>;
 140                         gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
 141                 };
 142
 143                 USER2 {
 144                         label = "btnUser2";
 145                         linux,code = <BTN_1>;
 146                         gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
 147                 };
 148         };
 149 };
 150
 151 &dra7_pmx_core {
 152         pinctrl-names = "default";
 153         pinctrl-0 = <&vtt_pin>;
 154
 155         vtt_pin: pinmux_vtt_pin {
 156                 pinctrl-single,pins = <
 157                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
 158                 >;
 159         };
 160
 161         i2c1_pins: pinmux_i2c1_pins {
 162                 pinctrl-single,pins = <
 163                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
 164                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
 165                 >;
 166         };
 167
 168         i2c2_pins: pinmux_i2c2_pins {
 169                 pinctrl-single,pins = <
 170                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 171                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 172                 >;
 173         };
 174
 175         i2c3_pins: pinmux_i2c3_pins {
 176                 pinctrl-single,pins = <
 177                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
 178                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
 179                 >;
 180         };
 181
 182         mcspi1_pins: pinmux_mcspi1_pins {
 183                 pinctrl-single,pins = <
 184                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
 185                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
 186                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
 187                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
 188                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
 189                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
 190                 >;
 191         };
 192
 193         mcspi2_pins: pinmux_mcspi2_pins {
 194                 pinctrl-single,pins = <
 195                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
 196                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 197                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
 198                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
 199                 >;
 200         };
 201
 202         uart1_pins: pinmux_uart1_pins {
 203                 pinctrl-single,pins = <
 204                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
 205                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
 206                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
 207                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
 208                 >;
 209         };
 210
 211         uart2_pins: pinmux_uart2_pins {
 212                 pinctrl-single,pins = <
 213                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 214                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 215                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 216                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 217                 >;
 218         };
 219
 220         uart3_pins: pinmux_uart3_pins {
 221                 pinctrl-single,pins = <
 222                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 223                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 224                 >;
 225         };
 226
 227         qspi1_pins: pinmux_qspi1_pins {
 228                 pinctrl-single,pins = <
 229                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 230                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 231                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 232                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 233                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 234                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 235                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 236                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 237                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 238                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 239                 >;
 240         };
 241
 242         usb1_pins: pinmux_usb1_pins {
 243                 pinctrl-single,pins = <
 244                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 245                 >;
 246         };
 247
 248         usb2_pins: pinmux_usb2_pins {
 249                 pinctrl-single,pins = <
 250                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 251                 >;
 252         };
 253
 254         nand_flash_x16: nand_flash_x16 {
 255                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 256                  * So NAND flash requires following switch settings:
 257                  * SW5.9 (GPMC_WPN) = LOW
 258                  * SW5.1 (NAND_BOOTn) = HIGH */
 259                 pinctrl-single,pins = <
 260                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 261                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 262                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 263                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 264                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 265                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 266                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 267                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 268                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 269                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 270                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 271                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 272                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 273                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 274                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 275                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 276                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 277                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 278                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 279                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 280                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 281                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 282                 >;
 283         };
 284
 285         cpsw_default: cpsw_default {
 286                 pinctrl-single,pins = <
 287                         /* Slave 1 */
 288                         0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txc.rgmii0_txc */
 289                         0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txctl.rgmii0_txctl */
 290                         0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_td3.rgmii0_txd3 */
 291                         0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd2.rgmii0_txd2 */
 292                         0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd1.rgmii0_txd1 */
 293                         0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii0_txd0.rgmii0_txd0 */
 294                         0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxc.rgmii0_rxc */
 295                         0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxctl.rgmii0_rxctl */
 296                         0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd3.rgmii0_rxd3 */
 297                         0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd2.rgmii0_rxd2 */
 298                         0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd1.rgmii0_rxd1 */
 299                         0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii0_rxd0.rgmii0_rxd0 */
 300
 301                         /* Slave 2 */
 302                         0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
 303                         0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
 304                         0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
 305                         0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
 306                         0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
 307                         0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
 308                         0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
 309                         0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
 310                         0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
 311                         0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
 312                         0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
 313                         0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
 314                 >;
 315
 316         };
 317
 318         cpsw_sleep: cpsw_sleep {
 319                 pinctrl-single,pins = <
 320                         /* Slave 1 */
 321                         0x250 (MUX_MODE15)
 322                         0x254 (MUX_MODE15)
 323                         0x258 (MUX_MODE15)
 324                         0x25c (MUX_MODE15)
 325                         0x260 (MUX_MODE15)
 326                         0x264 (MUX_MODE15)
 327                         0x268 (MUX_MODE15)
 328                         0x26c (MUX_MODE15)
 329                         0x270 (MUX_MODE15)
 330                         0x274 (MUX_MODE15)
 331                         0x278 (MUX_MODE15)
 332                         0x27c (MUX_MODE15)
 333
 334                         /* Slave 2 */
 335                         0x198 (MUX_MODE15)
 336                         0x19c (MUX_MODE15)
 337                         0x1a0 (MUX_MODE15)
 338                         0x1a4 (MUX_MODE15)
 339                         0x1a8 (MUX_MODE15)
 340                         0x1ac (MUX_MODE15)
 341                         0x1b0 (MUX_MODE15)
 342                         0x1b4 (MUX_MODE15)
 343                         0x1b8 (MUX_MODE15)
 344                         0x1bc (MUX_MODE15)
 345                         0x1c0 (MUX_MODE15)
 346                         0x1c4 (MUX_MODE15)
 347                 >;
 348         };
 349
 350         davinci_mdio_default: davinci_mdio_default {
 351                 pinctrl-single,pins = <
 352                         0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
 353                         0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
 354                 >;
 355         };
 356
 357         davinci_mdio_sleep: davinci_mdio_sleep {
 358                 pinctrl-single,pins = <
 359                         0x23c (MUX_MODE15)
 360                         0x240 (MUX_MODE15)
 361                 >;
 362         };
 363
 364         dcan1_pins_default: dcan1_pins_default {
 365                 pinctrl-single,pins = <
 366                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 367                         0x418   (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 368                 >;
 369         };
 370
 371         dcan1_pins_sleep: dcan1_pins_sleep {
 372                 pinctrl-single,pins = <
 373                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 374                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 375                 >;
 376         };
 377
 378         atl_pins: pinmux_atl_pins {
 379                 pinctrl-single,pins = <
 380                         0x298 (PIN_OUTPUT | MUX_MODE5)  /* xref_clk1.atl_clk1 */
 381                         0x29c (PIN_OUTPUT | MUX_MODE5)  /* xref_clk2.atl_clk2 */
 382                 >;
 383         };
 384
 385         mcasp3_pins: pinmux_mcasp3_pins {
 386                 pinctrl-single,pins = <
 387                         0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
 388                         0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
 389                         0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
 390                         0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp3_axr1 */
 391                 >;
 392         };
 393
 394         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 395                 pinctrl-single,pins = <
 396                         0x324 (MUX_MODE15)
 397                         0x328 (MUX_MODE15)
 398                         0x32c (MUX_MODE15)
 399                         0x330 (MUX_MODE15)
 400                 >;
 401         };
 402 };
 403
 404 &i2c1 {
 405         status = "okay";
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&i2c1_pins>;
 408         clock-frequency = <400000>;
 409
 410         tps659038: tps659038@58 {
 411                 compatible = "ti,tps659038";
 412                 reg = <0x58>;
 413                 ti,palmas-override-powerhold;
 414                 ti,system-power-controller;
 415
 416                 tps659038_pmic {
 417                         compatible = "ti,tps659038-pmic";
 418
 419                         regulators {
 420                                 smps123_reg: smps123 {
 421                                         /* VDD_MPU */
 422                                         regulator-name = "smps123";
 423                                         regulator-min-microvolt = < 850000>;
 424                                         regulator-max-microvolt = <1250000>;
 425                                         regulator-always-on;
 426                                         regulator-boot-on;
 427                                 };
 428
 429                                 smps45_reg: smps45 {
 430                                         /* VDD_DSPEVE */
 431                                         regulator-name = "smps45";
 432                                         regulator-min-microvolt = < 850000>;
 433                                         regulator-max-microvolt = <1150000>;
 434                                         regulator-always-on;
 435                                         regulator-boot-on;
 436                                 };
 437
 438                                 smps6_reg: smps6 {
 439                                         /* VDD_GPU - over VDD_SMPS6 */
 440                                         regulator-name = "smps6";
 441                                         regulator-min-microvolt = <850000>;
 442                                         regulator-max-microvolt = <1250000>;
 443                                         regulator-always-on;
 444                                         regulator-boot-on;
 445                                 };
 446
 447                                 smps7_reg: smps7 {
 448                                         /* CORE_VDD */
 449                                         regulator-name = "smps7";
 450                                         regulator-min-microvolt = <850000>;
 451                                         regulator-max-microvolt = <1060000>;
 452                                         regulator-always-on;
 453                                         regulator-boot-on;
 454                                 };
 455
 456                                 smps8_reg: smps8 {
 457                                         /* VDD_IVAHD */
 458                                         regulator-name = "smps8";
 459                                         regulator-min-microvolt = < 850000>;
 460                                         regulator-max-microvolt = <1250000>;
 461                                         regulator-always-on;
 462                                         regulator-boot-on;
 463                                 };
 464
 465                                 smps9_reg: smps9 {
 466                                         /* VDDS1V8 */
 467                                         regulator-name = "smps9";
 468                                         regulator-min-microvolt = <1800000>;
 469                                         regulator-max-microvolt = <1800000>;
 470                                         regulator-always-on;
 471                                         regulator-boot-on;
 472                                 };
 473
 474                                 ldo1_reg: ldo1 {
 475                                         /* LDO1_OUT --> SDIO  */
 476                                         regulator-name = "ldo1";
 477                                         regulator-min-microvolt = <1800000>;
 478                                         regulator-max-microvolt = <3300000>;
 479                                         regulator-always-on;
 480                                         regulator-boot-on;
 481                                 };
 482
 483                                 ldo2_reg: ldo2 {
 484                                         /* VDD_RTCIO */
 485                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 486                                         regulator-name = "ldo2";
 487                                         regulator-min-microvolt = <3300000>;
 488                                         regulator-max-microvolt = <3300000>;
 489                                         regulator-always-on;
 490                                         regulator-boot-on;
 491                                 };
 492
 493                                 ldo3_reg: ldo3 {
 494                                         /* VDDA_1V8_PHY */
 495                                         regulator-name = "ldo3";
 496                                         regulator-min-microvolt = <1800000>;
 497                                         regulator-max-microvolt = <1800000>;
 498                                         regulator-always-on;
 499                                         regulator-boot-on;
 500                                 };
 501
 502                                 ldo9_reg: ldo9 {
 503                                         /* VDD_RTC */
 504                                         regulator-name = "ldo9";
 505                                         regulator-min-microvolt = <1050000>;
 506                                         regulator-max-microvolt = <1050000>;
 507                                         regulator-always-on;
 508                                         regulator-boot-on;
 509                                 };
 510
 511                                 ldoln_reg: ldoln {
 512                                         /* VDDA_1V8_PLL */
 513                                         regulator-name = "ldoln";
 514                                         regulator-min-microvolt = <1800000>;
 515                                         regulator-max-microvolt = <1800000>;
 516                                         regulator-always-on;
 517                                         regulator-boot-on;
 518                                 };
 519
 520                                 ldousb_reg: ldousb {
 521                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 522                                         regulator-name = "ldousb";
 523                                         regulator-min-microvolt = <3300000>;
 524                                         regulator-max-microvolt = <3300000>;
 525                                         regulator-boot-on;
 526                                 };
 527                         };
 528                 };
 529         };
 530
 531         pcf_lcd: gpio@20 {
 532                 compatible = "nxp,pcf8575";
 533                 reg = <0x20>;
 534                 gpio-controller;
 535                 #gpio-cells = <2>;
 536                 interrupt-parent = <&gpio6>;
 537                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 538                 interrupt-controller;
 539                 #interrupt-cells = <2>;
 540         };
 541
 542         pcf_gpio_21: gpio@21 {
 543                 compatible = "ti,pcf8575";
 544                 reg = <0x21>;
 545                 lines-initial-states = <0x1408>;
 546                 gpio-controller;
 547                 #gpio-cells = <2>;
 548                 interrupt-parent = <&gpio6>;
 549                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 550                 interrupt-controller;
 551                 #interrupt-cells = <2>;
 552         };
 553
 554         tlv320aic3106: tlv320aic3106@19 {
 555                 #sound-dai-cells = <0>;
 556                 compatible = "ti,tlv320aic3106";
 557                 reg = <0x19>;
 558                 adc-settle-ms = <40>;
 559                 ai3x-micbias-vg = <1>;          /* 2.0V */
 560                 status = "okay";
 561
 562                 /* Regulators */
 563                 AVDD-supply = <&evm_3v3_sw>;
 564                 IOVDD-supply = <&evm_3v3_sw>;
 565                 DRVDD-supply = <&evm_3v3_sw>;
 566                 DVDD-supply = <&aic_dvdd>;
 567         };
 568 };
 569
 570 &i2c2 {
 571         status = "okay";
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&i2c2_pins>;
 574         clock-frequency = <400000>;
 575
 576         pcf_hdmi: gpio@26 {
 577                 compatible = "nxp,pcf8575";
 578                 reg = <0x26>;
 579                 gpio-controller;
 580                 #gpio-cells = <2>;
 581                 p1 {
 582                         /* vin6_sel_s0: high: VIN6, low: audio */
 583                         gpio-hog;
 584                         gpios = <1 GPIO_ACTIVE_HIGH>;
 585                         output-low;
 586                         line-name = "vin6_sel_s0";
 587                 };
 588         };
 589 };
 590
 591 &i2c3 {
 592         status = "okay";
 593         pinctrl-names = "default";
 594         pinctrl-0 = <&i2c3_pins>;
 595         clock-frequency = <400000>;
 596 };
 597
 598 &mcspi1 {
 599         status = "okay";
 600         pinctrl-names = "default";
 601         pinctrl-0 = <&mcspi1_pins>;
 602 };
 603
 604 &mcspi2 {
 605         status = "okay";
 606         pinctrl-names = "default";
 607         pinctrl-0 = <&mcspi2_pins>;
 608 };
 609
 610 &uart1 {
 611         status = "okay";
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&uart1_pins>;
 614         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 615                               <&dra7_pmx_core 0x3e0>;
 616 };
 617
 618 &uart2 {
 619         status = "okay";
 620         pinctrl-names = "default";
 621         pinctrl-0 = <&uart2_pins>;
 622 };
 623
 624 &uart3 {
 625         status = "okay";
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&uart3_pins>;
 628 };
 629
 630 &mmc1 {
 631         status = "okay";
 632         vmmc-supply = <&evm_3v3_sd>;
 633         vmmc_aux-supply = <&ldo1_reg>;
 634         bus-width = <4>;
 635         /*
 636          * SDCD signal is not being used here - using the fact that GPIO mode
 637          * is always hardwired.
 638          */
 639         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 640 };
 641
 642 &mmc2 {
 643         status = "okay";
 644         vmmc-supply = <&evm_3v3_sw>;
 645         bus-width = <8>;
 646 };
 647
 648 &cpu0 {
 649         cpu0-supply = <&smps123_reg>;
 650 };
 651
 652 &qspi {
 653         status = "okay";
 654         pinctrl-names = "default";
 655         pinctrl-0 = <&qspi1_pins>;
 656
 657         spi-max-frequency = <48000000>;
 658         m25p80@0 {
 659                 compatible = "s25fl256s1";
 660                 spi-max-frequency = <48000000>;
 661                 reg = <0>;
 662                 spi-tx-bus-width = <1>;
 663                 spi-rx-bus-width = <4>;
 664                 spi-cpol;
 665                 spi-cpha;
 666                 #address-cells = <1>;
 667                 #size-cells = <1>;
 668
 669                 /* MTD partition table.
 670                  * The ROM checks the first four physical blocks
 671                  * for a valid file to boot and the flash here is
 672                  * 64KiB block size.
 673                  */
 674                 partition@0 {
 675                         label = "QSPI.SPL";
 676                         reg = <0x00000000 0x000010000>;
 677                 };
 678                 partition@1 {
 679                         label = "QSPI.SPL.backup1";
 680                         reg = <0x00010000 0x00010000>;
 681                 };
 682                 partition@2 {
 683                         label = "QSPI.SPL.backup2";
 684                         reg = <0x00020000 0x00010000>;
 685                 };
 686                 partition@3 {
 687                         label = "QSPI.SPL.backup3";
 688                         reg = <0x00030000 0x00010000>;
 689                 };
 690                 partition@4 {
 691                         label = "QSPI.u-boot";
 692                         reg = <0x00040000 0x00100000>;
 693                 };
 694                 partition@5 {
 695                         label = "QSPI.u-boot-spl-os";
 696                         reg = <0x00140000 0x00080000>;
 697                 };
 698                 partition@6 {
 699                         label = "QSPI.u-boot-env";
 700                         reg = <0x001c0000 0x00010000>;
 701                 };
 702                 partition@7 {
 703                         label = "QSPI.u-boot-env.backup1";
 704                         reg = <0x001d0000 0x0010000>;
 705                 };
 706                 partition@8 {
 707                         label = "QSPI.kernel";
 708                         reg = <0x001e0000 0x0800000>;
 709                 };
 710                 partition@9 {
 711                         label = "QSPI.file-system";
 712                         reg = <0x009e0000 0x01620000>;
 713                 };
 714         };
 715 };
 716
 717 &omap_dwc3_1 {
 718         extcon = <&extcon_usb1>;
 719 };
 720
 721 &omap_dwc3_2 {
 722         extcon = <&extcon_usb2>;
 723 };
 724
 725 &usb1 {
 726         dr_mode = "peripheral";
 727         pinctrl-names = "default";
 728         pinctrl-0 = <&usb1_pins>;
 729 };
 730
 731 &usb2 {
 732         dr_mode = "host";
 733         pinctrl-names = "default";
 734         pinctrl-0 = <&usb2_pins>;
 735 };
 736
 737 &elm {
 738         status = "okay";
 739 };
 740
 741 &gpmc {
 742         status = "okay";
 743         pinctrl-names = "default";
 744         pinctrl-0 = <&nand_flash_x16>;
 745         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 746         nand@0,0 {
 747                 reg = <0 0 4>;          /* device IO registers */
 748                 ti,nand-ecc-opt = "bch8";
 749                 ti,elm-id = <&elm>;
 750                 nand-bus-width = <16>;
 751                 gpmc,device-width = <2>;
 752                 gpmc,sync-clk-ps = <0>;
 753                 gpmc,cs-on-ns = <0>;
 754                 gpmc,cs-rd-off-ns = <80>;
 755                 gpmc,cs-wr-off-ns = <80>;
 756                 gpmc,adv-on-ns = <0>;
 757                 gpmc,adv-rd-off-ns = <60>;
 758                 gpmc,adv-wr-off-ns = <60>;
 759                 gpmc,we-on-ns = <10>;
 760                 gpmc,we-off-ns = <50>;
 761                 gpmc,oe-on-ns = <4>;
 762                 gpmc,oe-off-ns = <40>;
 763                 gpmc,access-ns = <40>;
 764                 gpmc,wr-access-ns = <80>;
 765                 gpmc,rd-cycle-ns = <80>;
 766                 gpmc,wr-cycle-ns = <80>;
 767                 gpmc,bus-turnaround-ns = <0>;
 768                 gpmc,cycle2cycle-delay-ns = <0>;
 769                 gpmc,clk-activation-ns = <0>;
 770                 gpmc,wait-monitoring-ns = <0>;
 771                 gpmc,wr-data-mux-bus-ns = <0>;
 772                 /* MTD partition table */
 773                 /* All SPL-* partitions are sized to minimal length
 774                  * which can be independently programmable. For
 775                  * NAND flash this is equal to size of erase-block */
 776                 #address-cells = <1>;
 777                 #size-cells = <1>;
 778                 partition@0 {
 779                         label = "NAND.SPL";
 780                         reg = <0x00000000 0x000020000>;
 781                 };
 782                 partition@1 {
 783                         label = "NAND.SPL.backup1";
 784                         reg = <0x00020000 0x00020000>;
 785                 };
 786                 partition@2 {
 787                         label = "NAND.SPL.backup2";
 788                         reg = <0x00040000 0x00020000>;
 789                 };
 790                 partition@3 {
 791                         label = "NAND.SPL.backup3";
 792                         reg = <0x00060000 0x00020000>;
 793                 };
 794                 partition@4 {
 795                         label = "NAND.u-boot-spl-os";
 796                         reg = <0x00080000 0x00040000>;
 797                 };
 798                 partition@5 {
 799                         label = "NAND.u-boot";
 800                         reg = <0x000c0000 0x00100000>;
 801                 };
 802                 partition@6 {
 803                         label = "NAND.u-boot-env";
 804                         reg = <0x001c0000 0x00020000>;
 805                 };
 806                 partition@7 {
 807                         label = "NAND.u-boot-env.backup1";
 808                         reg = <0x001e0000 0x00020000>;
 809                 };
 810                 partition@8 {
 811                         label = "NAND.kernel";
 812                         reg = <0x00200000 0x00800000>;
 813                 };
 814                 partition@9 {
 815                         label = "NAND.file-system";
 816                         reg = <0x00a00000 0x0f600000>;
 817                 };
 818         };
 819 };
 820
 821 &usb2_phy1 {
 822         phy-supply = <&ldousb_reg>;
 823 };
 824
 825 &usb2_phy2 {
 826         phy-supply = <&ldousb_reg>;
 827 };
 828
 829 &gpio7 {
 830         ti,no-reset-on-init;
 831         ti,no-idle-on-init;
 832 };
 833
 834 &mac {
 835         status = "okay";
 836         pinctrl-names = "default", "sleep";
 837         pinctrl-0 = <&cpsw_default>;
 838         pinctrl-1 = <&cpsw_sleep>;
 839         dual_emac;
 840 };
 841
 842 &cpsw_emac0 {
 843         phy_id = <&davinci_mdio>, <2>;
 844         phy-mode = "rgmii";
 845         dual_emac_res_vlan = <1>;
 846 };
 847
 848 &cpsw_emac1 {
 849         phy_id = <&davinci_mdio>, <3>;
 850         phy-mode = "rgmii";
 851         dual_emac_res_vlan = <2>;
 852 };
 853
 854 &davinci_mdio {
 855         pinctrl-names = "default", "sleep";
 856         pinctrl-0 = <&davinci_mdio_default>;
 857         pinctrl-1 = <&davinci_mdio_sleep>;
 858 };
 859
 860 &dcan1 {
 861         status = "ok";
 862         pinctrl-names = "default", "sleep", "active";
 863         pinctrl-0 = <&dcan1_pins_sleep>;
 864         pinctrl-1 = <&dcan1_pins_sleep>;
 865         pinctrl-2 = <&dcan1_pins_default>;
 866 };
 867
 868 &atl {
 869         pinctrl-names = "default";
 870         pinctrl-0 = <&atl_pins>;
 871
 872         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 873                           <&atl_gfclk_mux>,
 874                           <&dpll_abe_ck>,
 875                           <&dpll_abe_m2x2_ck>,
 876                           <&atl_clkin2_ck>;
 877         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 878         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 879
 880         status = "okay";
 881
 882         atl2 {
 883                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 884                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 885         };
 886 };
 887
 888 &mcasp3 {
 889         #sound-dai-cells = <0>;
 890         pinctrl-names = "default", "sleep";
 891         pinctrl-0 = <&mcasp3_pins>;
 892         pinctrl-1 = <&mcasp3_sleep_pins>;
 893
 894         assigned-clocks = <&mcasp3_ahclkx_mux>;
 895         assigned-clock-parents = <&atl_clkin2_ck>;
 896
 897         status = "okay";
 898
 899         op-mode = <0>;          /* MCASP_IIS_MODE */
 900         tdm-slots = <2>;
 901         /* 4 serializer */
 902         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 903                 1 2 0 0
 904         >;
 905 };
 906
 907 &mailbox5 {
 908         status = "okay";
 909         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 910                 status = "okay";
 911         };
 912         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 913                 status = "okay";
 914         };
 915 };
 916
 917 &mailbox6 {
 918         status = "okay";
 919         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 920                 status = "okay";
 921         };
 922         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 923                 status = "okay";
 924         };
 925 };