arch/arm/boot/dts/dm816x-clocks.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 &scrm {
   8         main_fapll: main_fapll {
   9                 #clock-cells = <1>;
  10                 compatible = "ti,dm816-fapll-clock";
  11                 reg = <0x400 0x40>;
  12                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
  13                 clock-indices = <1>, <2>, <3>, <4>, <5>,
  14                                 <6>, <7>;
  15                 clock-output-names = "main_pll_clk1",
  16                                      "main_pll_clk2",
  17                                      "main_pll_clk3",
  18                                      "main_pll_clk4",
  19                                      "main_pll_clk5",
  20                                      "main_pll_clk6",
  21                                      "main_pll_clk7";
  22         };
  23
  24         ddr_fapll: ddr_fapll {
  25                 #clock-cells = <1>;
  26                 compatible = "ti,dm816-fapll-clock";
  27                 reg = <0x440 0x30>;
  28                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
  29                 clock-indices = <1>, <2>, <3>, <4>;
  30                 clock-output-names = "ddr_pll_clk1",
  31                                      "ddr_pll_clk2",
  32                                      "ddr_pll_clk3",
  33                                      "ddr_pll_clk4";
  34         };
  35
  36         video_fapll: video_fapll {
  37                 #clock-cells = <1>;
  38                 compatible = "ti,dm816-fapll-clock";
  39                 reg = <0x470 0x30>;
  40                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
  41                 clock-indices = <1>, <2>, <3>;
  42                 clock-output-names = "video_pll_clk1",
  43                                      "video_pll_clk2",
  44                                      "video_pll_clk3";
  45         };
  46
  47         audio_fapll: audio_fapll {
  48                 #clock-cells = <1>;
  49                 compatible = "ti,dm816-fapll-clock";
  50                 reg = <0x4a0 0x30>;
  51                 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
  52                 clock-indices = <1>, <2>, <3>, <4>, <5>;
  53                 clock-output-names = "audio_pll_clk1",
  54                                      "audio_pll_clk2",
  55                                      "audio_pll_clk3",
  56                                      "audio_pll_clk4",
  57                                      "audio_pll_clk5";
  58         };
  59 };
  60
  61 &scrm_clocks {
  62         secure_32k_ck: secure_32k_ck {
  63                 #clock-cells = <0>;
  64                 compatible = "fixed-clock";
  65                 clock-frequency = <32768>;
  66         };
  67
  68         sys_32k_ck: sys_32k_ck {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <32768>;
  72         };
  73
  74         tclkin_ck: tclkin_ck {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <32768>;
  78         };
  79
  80         sys_clkin_ck: sys_clkin_ck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-clock";
  83                 clock-frequency = <27000000>;
  84         };
  85 };
  86
  87 /* 0x48180000 */
  88 &prcm_clocks {
  89         clkout_pre_ck: clkout_pre_ck@100 {
  90                 #clock-cells = <0>;
  91                 compatible = "ti,mux-clock";
  92                 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
  93                           &audio_fapll 1>;
  94                 reg = <0x100>;
  95         };
  96
  97         clkout_div_ck: clkout_div_ck@100 {
  98                 #clock-cells = <0>;
  99                 compatible = "ti,divider-clock";
 100                 clocks = <&clkout_pre_ck>;
 101                 ti,bit-shift = <3>;
 102                 ti,max-div = <8>;
 103                 reg = <0x100>;
 104         };
 105
 106         clkout_ck: clkout_ck@100 {
 107                 #clock-cells = <0>;
 108                 compatible = "ti,gate-clock";
 109                 clocks = <&clkout_div_ck>;
 110                 ti,bit-shift = <7>;
 111                 reg = <0x100>;
 112         };
 113
 114         /* CM_DPLL clocks p1795 */
 115         sysclk1_ck: sysclk1_ck@300 {
 116                 #clock-cells = <0>;
 117                 compatible = "ti,divider-clock";
 118                 clocks = <&main_fapll 1>;
 119                 ti,max-div = <7>;
 120                 reg = <0x0300>;
 121         };
 122
 123         sysclk2_ck: sysclk2_ck@304 {
 124                 #clock-cells = <0>;
 125                 compatible = "ti,divider-clock";
 126                 clocks = <&main_fapll 2>;
 127                 ti,max-div = <7>;
 128                 reg = <0x0304>;
 129         };
 130
 131         sysclk3_ck: sysclk3_ck@308 {
 132                 #clock-cells = <0>;
 133                 compatible = "ti,divider-clock";
 134                 clocks = <&main_fapll 3>;
 135                 ti,max-div = <7>;
 136                 reg = <0x0308>;
 137         };
 138
 139         sysclk4_ck: sysclk4_ck@30c {
 140                 #clock-cells = <0>;
 141                 compatible = "ti,divider-clock";
 142                 clocks = <&main_fapll 4>;
 143                 ti,max-div = <1>;
 144                 reg = <0x030c>;
 145         };
 146
 147         sysclk5_ck: sysclk5_ck@310 {
 148                 #clock-cells = <0>;
 149                 compatible = "ti,divider-clock";
 150                 clocks = <&sysclk4_ck>;
 151                 ti,max-div = <1>;
 152                 reg = <0x0310>;
 153         };
 154
 155         sysclk6_ck: sysclk6_ck@314 {
 156                 #clock-cells = <0>;
 157                 compatible = "ti,divider-clock";
 158                 clocks = <&main_fapll 4>;
 159                 ti,dividers = <2>, <4>;
 160                 reg = <0x0314>;
 161         };
 162
 163         sysclk10_ck: sysclk10_ck@324 {
 164                 #clock-cells = <0>;
 165                 compatible = "ti,divider-clock";
 166                 clocks = <&ddr_fapll 2>;
 167                 ti,max-div = <7>;
 168                 reg = <0x0324>;
 169         };
 170
 171         sysclk24_ck: sysclk24_ck@3b4 {
 172                 #clock-cells = <0>;
 173                 compatible = "ti,divider-clock";
 174                 clocks = <&main_fapll 5>;
 175                 ti,max-div = <7>;
 176                 reg = <0x03b4>;
 177         };
 178
 179         mpu_ck: mpu_ck@15dc {
 180                 #clock-cells = <0>;
 181                 compatible = "ti,gate-clock";
 182                 clocks = <&sysclk2_ck>;
 183                 ti,bit-shift = <1>;
 184                 reg = <0x15dc>;
 185         };
 186
 187         audio_pll_a_ck: audio_pll_a_ck@35c {
 188                 #clock-cells = <0>;
 189                 compatible = "ti,divider-clock";
 190                 clocks = <&audio_fapll 1>;
 191                 ti,max-div = <7>;
 192                 reg = <0x035c>;
 193         };
 194
 195         sysclk18_ck: sysclk18_ck@378 {
 196                 #clock-cells = <0>;
 197                 compatible = "ti,mux-clock";
 198                 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
 199                 reg = <0x0378>;
 200         };
 201
 202         timer1_fck: timer1_fck@390 {
 203                 #clock-cells = <0>;
 204                 compatible = "ti,mux-clock";
 205                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 206                 reg = <0x0390>;
 207         };
 208
 209         timer2_fck: timer2_fck@394 {
 210                 #clock-cells = <0>;
 211                 compatible = "ti,mux-clock";
 212                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 213                 reg = <0x0394>;
 214         };
 215
 216         timer3_fck: timer3_fck@398 {
 217                 #clock-cells = <0>;
 218                 compatible = "ti,mux-clock";
 219                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 220                 reg = <0x0398>;
 221         };
 222
 223         timer4_fck: timer4_fck@39c {
 224                 #clock-cells = <0>;
 225                 compatible = "ti,mux-clock";
 226                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 227                 reg = <0x039c>;
 228         };
 229
 230         timer5_fck: timer5_fck@3a0 {
 231                 #clock-cells = <0>;
 232                 compatible = "ti,mux-clock";
 233                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 234                 reg = <0x03a0>;
 235         };
 236
 237         timer6_fck: timer6_fck@3a4 {
 238                 #clock-cells = <0>;
 239                 compatible = "ti,mux-clock";
 240                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 241                 reg = <0x03a4>;
 242         };
 243
 244         timer7_fck: timer7_fck@3a8 {
 245                 #clock-cells = <0>;
 246                 compatible = "ti,mux-clock";
 247                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
 248                 reg = <0x03a8>;
 249         };
 250 };
 251
 252 &prcm {
 253         default_cm: default_cm@500 {
 254                 compatible = "ti,omap4-cm";
 255                 reg = <0x500 0x100>;
 256                 #address-cells = <1>;
 257                 #size-cells = <1>;
 258                 ranges = <0 0x500 0x100>;
 259
 260                 default_clkctrl: clk@0 {
 261                         compatible = "ti,clkctrl";
 262                         reg = <0x0 0x5c>;
 263                         #clock-cells = <2>;
 264                 };
 265         };
 266
 267         alwon_cm: alwon_cm@1400 {
 268                 compatible = "ti,omap4-cm";
 269                 reg = <0x1400 0x300>;
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272                 ranges = <0 0x1400 0x300>;
 273
 274                 alwon_clkctrl: clk@0 {
 275                         compatible = "ti,clkctrl";
 276                         reg = <0x0 0x208>;
 277                         #clock-cells = <2>;
 278                 };
 279         };
 280 };