1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "brcm,bcm6855", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
50 compatible = "arm,armv7-timer";
51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
55 arm,cpu-registers-not-fw-configured;
59 compatible = "arm,cortex-a7-pmu";
60 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
67 periph_clk: periph-clk {
68 compatible = "fixed-clock";
70 clock-frequency = <200000000>;
74 compatible = "fixed-factor-clock";
76 clocks = <&periph_clk>;
83 compatible = "arm,psci-0.2";
88 compatible = "simple-bus";
91 ranges = <0 0x81000000 0x8000>;
93 gic: interrupt-controller@1000 {
94 compatible = "arm,cortex-a7-gic";
95 #interrupt-cells = <3>;
97 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
98 reg = <0x1000 0x1000>,
106 compatible = "simple-bus";
107 #address-cells = <1>;
109 ranges = <0 0xff800000 0x800000>;
111 uart0: serial@12000 {
112 compatible = "arm,pl011", "arm,primecell";
113 reg = <0x12000 0x1000>;
114 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&uart_clk>, <&uart_clk>;
116 clock-names = "uartclk", "apb_pclk";