1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "brcm,bcm6846", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
42 compatible = "arm,armv7-timer";
43 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
47 arm,cpu-registers-not-fw-configured;
51 compatible = "arm,cortex-a7-pmu";
52 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
54 interrupt-affinity = <&CA7_0>, <&CA7_1>;
58 periph_clk: periph-clk {
59 compatible = "fixed-clock";
61 clock-frequency = <200000000>;
66 compatible = "arm,psci-0.2";
71 compatible = "simple-bus";
74 ranges = <0 0x81000000 0x8000>;
76 gic: interrupt-controller@1000 {
77 compatible = "arm,cortex-a7-gic";
78 #interrupt-cells = <3>;
80 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
81 reg = <0x1000 0x1000>,
89 compatible = "simple-bus";
92 ranges = <0 0xff800000 0x800000>;
95 compatible = "brcm,bcm6345-uart";
97 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&periph_clk>;
99 clock-names = "refclk";