1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "brcm,bcm6756", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
38 compatible = "arm,cortex-a7";
40 next-level-cache = <&L2_0>;
41 enable-method = "psci";
46 compatible = "arm,cortex-a7";
48 next-level-cache = <&L2_0>;
49 enable-method = "psci";
58 compatible = "arm,armv7-timer";
59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
60 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
63 arm,cpu-registers-not-fw-configured;
67 compatible = "arm,cortex-a7-pmu";
68 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-affinity = <&CA7_0>, <&CA7_1>,
77 periph_clk: periph-clk {
78 compatible = "fixed-clock";
80 clock-frequency = <200000000>;
84 compatible = "fixed-factor-clock";
86 clocks = <&periph_clk>;
93 compatible = "arm,psci-0.2";
98 compatible = "simple-bus";
101 ranges = <0 0x81000000 0x8000>;
103 gic: interrupt-controller@1000 {
104 compatible = "arm,cortex-a7-gic";
105 #interrupt-cells = <3>;
106 interrupt-controller;
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
108 reg = <0x1000 0x1000>,
116 compatible = "simple-bus";
117 #address-cells = <1>;
119 ranges = <0 0xff800000 0x800000>;
121 uart0: serial@12000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x12000 0x1000>;
124 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&uart_clk>, <&uart_clk>;
126 clock-names = "uartclk", "apb_pclk";