arch/arm/boot/dts/bcm6756.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 Broadcom Ltd.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 / {
  10         compatible = "brcm,bcm6756", "brcm,bcmbca";
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         interrupt-parent = <&gic>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 CA7_0: cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a7";
  23                         reg = <0x0>;
  24                         next-level-cache = <&L2_0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 CA7_1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0x1>;
  32                         next-level-cache = <&L2_0>;
  33                         enable-method = "psci";
  34                 };
  35
  36                 CA7_2: cpu@2 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a7";
  39                         reg = <0x2>;
  40                         next-level-cache = <&L2_0>;
  41                         enable-method = "psci";
  42                 };
  43
  44                 CA7_3: cpu@3 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a7";
  47                         reg = <0x3>;
  48                         next-level-cache = <&L2_0>;
  49                         enable-method = "psci";
  50                 };
  51
  52                 L2_0: l2-cache0 {
  53                         compatible = "cache";
  54                 };
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv7-timer";
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  60                         <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  61                         <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  62                         <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  63                 arm,cpu-registers-not-fw-configured;
  64         };
  65
  66         pmu: pmu {
  67                 compatible = "arm,cortex-a7-pmu";
  68                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  69                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  70                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  71                         <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  72                 interrupt-affinity = <&CA7_0>, <&CA7_1>,
  73                         <&CA7_2>, <&CA7_3>;
  74         };
  75
  76         clocks: clocks {
  77                 periph_clk: periph-clk {
  78                         compatible = "fixed-clock";
  79                         #clock-cells = <0>;
  80                         clock-frequency = <200000000>;
  81                 };
  82
  83                 uart_clk: uart-clk {
  84                         compatible = "fixed-factor-clock";
  85                         #clock-cells = <0>;
  86                         clocks = <&periph_clk>;
  87                         clock-div = <4>;
  88                         clock-mult = <1>;
  89                 };
  90         };
  91
  92         psci {
  93                 compatible = "arm,psci-0.2";
  94                 method = "smc";
  95         };
  96
  97         axi@81000000 {
  98                 compatible = "simple-bus";
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 ranges = <0 0x81000000 0x8000>;
 102
 103                 gic: interrupt-controller@1000 {
 104                         compatible = "arm,cortex-a7-gic";
 105                         #interrupt-cells = <3>;
 106                         interrupt-controller;
 107                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 108                         reg = <0x1000 0x1000>,
 109                                 <0x2000 0x2000>,
 110                                 <0x4000 0x2000>,
 111                                 <0x6000 0x2000>;
 112                 };
 113         };
 114
 115         bus@ff800000 {
 116                 compatible = "simple-bus";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges = <0 0xff800000 0x800000>;
 120
 121                 uart0: serial@12000 {
 122                         compatible = "arm,pl011", "arm,primecell";
 123                         reg = <0x12000 0x1000>;
 124                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 125                         clocks = <&uart_clk>, <&uart_clk>;
 126                         clock-names = "uartclk", "apb_pclk";
 127                         status = "disabled";
 128                 };
 129         };
 130 };