2 * Broadcom BCM63138 DSL SoCs Device Tree
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "skeleton.dtsi"
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
29 enable-method = "brcm,bcm63138";
34 compatible = "arm,cortex-a9";
35 next-level-cache = <&L2>;
37 enable-method = "brcm,bcm63138";
46 /* UBUS peripheral clock */
47 periph_clk: periph_clk {
49 compatible = "fixed-clock";
50 clock-frequency = <50000000>;
51 clock-output-names = "periph";
54 /* peripheral clock for system timer */
57 compatible = "fixed-factor-clock";
66 compatible = "fixed-factor-clock";
75 compatible = "simple-bus";
76 ranges = <0 0x80000000 0x784000>;
80 L2: cache-controller@1d000 {
81 compatible = "arm,pl310-cache";
82 reg = <0x1d000 0x1000>;
85 cache-size = <524288>;
87 cache-line-size = <32>;
88 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
92 compatible = "arm,cortex-a9-scu";
93 reg = <0x1e000 0x100>;
96 gic: interrupt-controller@1e100 {
97 compatible = "arm,cortex-a9-gic";
100 #interrupt-cells = <3>;
101 #address-cells = <0>;
102 interrupt-controller;
105 global_timer: timer@1e200 {
106 compatible = "arm,cortex-a9-global-timer";
107 reg = <0x1e200 0x20>;
108 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
112 local_timer: local-timer@1e600 {
113 compatible = "arm,cortex-a9-twd-timer";
114 reg = <0x1e600 0x20>;
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
116 IRQ_TYPE_EDGE_RISING)>;
120 twd_watchdog: watchdog@1e620 {
121 compatible = "arm,cortex-a9-twd-wdt";
122 reg = <0x1e620 0x20>;
123 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
124 IRQ_TYPE_LEVEL_HIGH)>;
129 compatible = "brcm,bcm63138-armpll";
130 clocks = <&periph_clk>;
131 reg = <0x20000 0xf00>;
134 pmb0: reset-controller@4800c0 {
135 compatible = "brcm,bcm63138-pmb";
136 reg = <0x4800c0 0x10>;
140 pmb1: reset-controller@4800e0 {
141 compatible = "brcm,bcm63138-pmb";
142 reg = <0x4800e0 0x10>;
147 /* Legacy UBUS base */
149 compatible = "simple-bus";
150 #address-cells = <1>;
152 ranges = <0 0xfffe8000 0x8100>;
155 compatible = "brcm,bcm6328-timer", "syscon";
159 serial0: serial@600 {
160 compatible = "brcm,bcm6345-uart";
162 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&periph_clk>;
164 clock-names = "periph";
168 serial1: serial@620 {
169 compatible = "brcm,bcm6345-uart";
171 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&periph_clk>;
173 clock-names = "periph";
177 nand_controller: nand-controller@2000 {
178 #address-cells = <1>;
180 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
181 reg = <0x2000 0x600>, <0xf0 0x10>;
182 reg-names = "nand", "nand-int-base";
184 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "nand";
188 bootlut: bootlut@8000 {
189 compatible = "brcm,bcm63138-bootlut";
194 compatible = "syscon-reboot";