2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
22 chipcommon-a-bus@18000000 {
23 compatible = "simple-bus";
24 ranges = <0x00000000 0x18000000 0x00001000>;
29 compatible = "ns16550";
31 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&iprocslow>;
37 compatible = "ns16550";
39 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
40 clocks = <&iprocslow>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinmux_uart1>;
48 compatible = "simple-bus";
49 ranges = <0x00000000 0x19000000 0x00023000>;
55 compatible = "brcm,nsp-armpll";
57 reg = <0x00000 0x1000>;
61 compatible = "arm,cortex-a9-scu";
62 reg = <0x20000 0x100>;
66 compatible = "arm,cortex-a9-global-timer";
67 reg = <0x20200 0x100>;
68 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
69 clocks = <&periph_clk>;
73 compatible = "arm,cortex-a9-twd-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
76 IRQ_TYPE_EDGE_RISING)>;
77 clocks = <&periph_clk>;
81 compatible = "arm,cortex-a9-twd-wdt";
83 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
84 IRQ_TYPE_EDGE_RISING)>;
85 clocks = <&periph_clk>;
88 gic: interrupt-controller@21000 {
89 compatible = "arm,cortex-a9-gic";
90 #interrupt-cells = <3>;
93 reg = <0x21000 0x1000>,
97 L2: cache-controller@22000 {
98 compatible = "arm,pl310-cache";
99 reg = <0x22000 0x1000>;
103 prefetch-instr = <1>;
109 compatible = "arm,cortex-a9-pmu";
111 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
116 #address-cells = <1>;
122 compatible = "fixed-clock";
123 clock-frequency = <25000000>;
128 compatible = "fixed-factor-clock";
129 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
134 iprocslow: iprocslow {
136 compatible = "fixed-factor-clock";
137 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
142 periph_clk: periph_clk {
144 compatible = "fixed-factor-clock";
152 compatible = "brcm,bus-axi";
153 reg = <0x18000000 0x1000>;
154 ranges = <0x00000000 0x18000000 0x00100000>;
155 #address-cells = <1>;
158 #interrupt-cells = <1>;
159 interrupt-map-mask = <0x000fffff 0xffff>;
162 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
164 /* Switch Register Access Block */
165 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
179 /* PCIe Controller 0 */
180 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
181 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
187 /* PCIe Controller 1 */
188 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
189 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
195 /* PCIe Controller 2 */
196 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
197 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
203 /* USB 2.0 Controller */
204 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
206 /* USB 3.0 Controller */
207 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
209 /* Ethernet Controller 0 */
210 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
212 /* Ethernet Controller 1 */
213 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
215 /* Ethernet Controller 2 */
216 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
218 /* Ethernet Controller 3 */
219 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
221 /* NAND Controller */
222 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
223 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
224 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
225 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
226 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
227 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
228 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
229 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
231 chipcommon: chipcommon@0 {
232 reg = <0x00000000 0x1000>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
241 reg = <0x00012000 0x1000>;
245 reg = <0x00013000 0x1000>;
249 reg = <0x00014000 0x1000>;
253 reg = <0x00021000 0x1000>;
255 #address-cells = <1>;
259 interrupt-parent = <&gic>;
264 compatible = "generic-ehci";
265 reg = <0x00021000 0x1000>;
266 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
274 #trigger-source-cells = <0>;
279 #trigger-source-cells = <0>;
286 compatible = "generic-ohci";
287 reg = <0x00022000 0x1000>;
288 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
290 #address-cells = <1>;
295 #trigger-source-cells = <0>;
300 #trigger-source-cells = <0>;
306 reg = <0x00023000 0x1000>;
308 #address-cells = <1>;
312 interrupt-parent = <&gic>;
317 compatible = "generic-xhci";
318 reg = <0x00023000 0x1000>;
319 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
328 #trigger-source-cells = <0>;
333 gmac0: ethernet@24000 {
334 reg = <0x24000 0x800>;
337 gmac1: ethernet@25000 {
338 reg = <0x25000 0x800>;
341 gmac2: ethernet@26000 {
342 reg = <0x26000 0x800>;
345 gmac3: ethernet@27000 {
346 reg = <0x27000 0x800>;
351 compatible = "brcm,iproc-pwm";
352 reg = <0x18002000 0x28>;
358 mdio: mdio@18003000 {
359 compatible = "brcm,iproc-mdio";
360 reg = <0x18003000 0x8>;
362 #address-cells = <1>;
366 compatible = "mdio-mux-mmioreg", "mdio-mux";
367 mdio-parent-bus = <&mdio>;
368 #address-cells = <1>;
370 reg = <0x18003000 0x4>;
375 #address-cells = <1>;
378 usb3_phy: usb3-phy@10 {
379 compatible = "brcm,ns-ax-usb3-phy";
381 usb3-dmp-syscon = <&usb3_dmp>;
388 usb3_dmp: syscon@18105000 {
389 reg = <0x18105000 0x1000>;
392 uart2: serial@18008000 {
393 compatible = "ns16550a";
394 reg = <0x18008000 0x20>;
395 clocks = <&iprocslow>;
396 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
402 compatible = "brcm,iproc-i2c";
403 reg = <0x18009000 0x50>;
404 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
405 #address-cells = <1>;
407 clock-frequency = <100000>;
412 compatible = "simple-bus";
413 ranges = <0 0x1800c000 0x1000>;
414 #address-cells = <1>;
418 compatible = "brcm,ns-cru", "simple-mfd";
421 #address-cells = <1>;
424 lcpll0: clock-controller@100 {
426 compatible = "brcm,nsp-lcpll0";
429 clock-output-names = "lcpll0", "pcie_phy",
433 genpll: clock-controller@140 {
435 compatible = "brcm,nsp-genpll";
438 clock-output-names = "genpll", "phy",
440 "usbclk", "iprocfast",
445 compatible = "brcm,ns-usb2-phy";
447 brcm,syscon-clkset = <&cru_clkset>;
448 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
449 clock-names = "phy-ref-clk";
453 cru_clkset: syscon@180 {
454 compatible = "brcm,cru-clkset", "syscon";
458 pinctrl: pinctrl@1c0 {
459 compatible = "brcm,bcm4708-pinmux";
461 reg-names = "cru_gpio_control";
468 pinmux_i2c: i2c-pins {
473 pinmux_pwm: pwm-pins {
474 groups = "pwm0_grp", "pwm1_grp",
475 "pwm2_grp", "pwm3_grp";
479 pinmux_uart1: uart1-pins {
480 groups = "uart1_grp";
485 thermal: thermal@2c0 {
486 compatible = "brcm,ns-thermal";
488 #thermal-sensor-cells = <0>;
493 srab: ethernet-switch@18007000 {
494 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
495 reg = <0x18007000 0x1000>;
499 /* ports are defined in board DTS */
501 #address-cells = <1>;
507 compatible = "brcm,bcm5301x-rng";
508 reg = <0x18004000 0x14>;
511 nand_controller: nand-controller@18028000 {
512 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
513 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
514 reg-names = "nand", "iproc-idm", "iproc-ext";
515 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
524 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
525 reg = <0x18029200 0x184>,
529 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
530 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
537 interrupt-names = "mspi_done",
539 "spi_lr_fullness_reached",
540 "spi_lr_session_aborted",
542 "spi_lr_session_done",
544 clocks = <&iprocmed>;
546 #address-cells = <1>;
550 compatible = "jedec,spi-nor";
552 spi-max-frequency = <20000000>;
556 compatible = "brcm,bcm947xx-cfe-partitions";
562 cpu_thermal: cpu-thermal {
563 polling-delay-passive = <0>;
564 polling-delay = <1000>;
565 coefficients = <(-556) 418000>;
566 thermal-sensors = <&thermal>;
570 temperature = <125000>;