2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
19 interrupt-parent = <&gic>;
26 compatible = "simple-bus";
27 ranges = <0x00000000 0x18000000 0x00001000>;
32 compatible = "ns16550";
34 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&iprocslow>;
40 compatible = "ns16550";
42 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&iprocslow>;
49 compatible = "simple-bus";
50 ranges = <0x00000000 0x19000000 0x00023000>;
54 a9pll: arm_clk@00000 {
56 compatible = "brcm,nsp-armpll";
58 reg = <0x00000 0x1000>;
62 compatible = "arm,cortex-a9-scu";
63 reg = <0x20000 0x100>;
67 compatible = "arm,cortex-a9-global-timer";
68 reg = <0x20200 0x100>;
69 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
70 clocks = <&periph_clk>;
74 compatible = "arm,cortex-a9-twd-timer";
75 reg = <0x20600 0x100>;
76 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
77 clocks = <&periph_clk>;
80 gic: interrupt-controller@21000 {
81 compatible = "arm,cortex-a9-gic";
82 #interrupt-cells = <3>;
85 reg = <0x21000 0x1000>,
89 L2: cache-controller@22000 {
90 compatible = "arm,pl310-cache";
91 reg = <0x22000 0x1000>;
101 compatible = "arm,cortex-a9-pmu";
103 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
108 #address-cells = <1>;
114 compatible = "fixed-clock";
115 clock-frequency = <25000000>;
120 compatible = "fixed-factor-clock";
121 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
126 iprocslow: iprocslow {
128 compatible = "fixed-factor-clock";
129 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
134 periph_clk: periph_clk {
136 compatible = "fixed-factor-clock";
144 compatible = "brcm,ns-usb2-phy";
145 reg = <0x1800c000 0x1000>;
148 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
149 clock-names = "phy-ref-clk";
153 compatible = "brcm,bus-axi";
154 reg = <0x18000000 0x1000>;
155 ranges = <0x00000000 0x18000000 0x00100000>;
156 #address-cells = <1>;
159 #interrupt-cells = <1>;
160 interrupt-map-mask = <0x000fffff 0xffff>;
163 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
165 /* Switch Register Access Block */
166 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
167 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
168 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
169 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
180 /* PCIe Controller 0 */
181 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
186 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
188 /* PCIe Controller 1 */
189 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
194 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
196 /* PCIe Controller 2 */
197 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
202 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
204 /* USB 2.0 Controller */
205 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
207 /* USB 3.0 Controller */
208 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
210 /* Ethernet Controller 0 */
211 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
213 /* Ethernet Controller 1 */
214 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
216 /* Ethernet Controller 2 */
217 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
219 /* Ethernet Controller 3 */
220 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
222 /* NAND Controller */
223 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
224 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
225 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
226 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
227 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
228 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
229 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
230 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
232 chipcommon: chipcommon@0 {
233 reg = <0x00000000 0x1000>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
242 reg = <0x00021000 0x1000>;
244 #address-cells = <1>;
251 reg = <0x00023000 0x1000>;
253 #address-cells = <1>;
258 reg = <0x00029000 0x1000>;
259 #address-cells = <1>;
263 compatible = "jedec,spi-nor";
265 spi-max-frequency = <20000000>;
266 linux,part-probe = "ofpart", "bcm47xxpart";
271 gmac0: ethernet@24000 {
272 reg = <0x24000 0x800>;
275 gmac1: ethernet@25000 {
276 reg = <0x25000 0x800>;
279 gmac2: ethernet@26000 {
280 reg = <0x26000 0x800>;
283 gmac3: ethernet@27000 {
284 reg = <0x27000 0x800>;
288 lcpll0: lcpll0@1800c100 {
290 compatible = "brcm,nsp-lcpll0";
291 reg = <0x1800c100 0x14>;
293 clock-output-names = "lcpll0", "pcie_phy", "sdio",
297 genpll: genpll@1800c140 {
299 compatible = "brcm,nsp-genpll";
300 reg = <0x1800c140 0x24>;
302 clock-output-names = "genpll", "phy", "ethernetclk",
303 "usbclk", "iprocfast", "sata1",
307 srab: srab@18007000 {
308 compatible = "brcm,bcm5301x-srab";
309 reg = <0x18007000 0x1000>;
310 #address-cells = <1>;
315 /* ports are defined in board DTS */
319 compatible = "brcm,bcm5301x-rng";
320 reg = <0x18004000 0x14>;
323 nand: nand@18028000 {
324 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
325 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
326 reg-names = "nand", "iproc-idm", "iproc-ext";
327 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;