arch/arm/boot/dts/bcm5301x.dtsi

   1 /*
   2  * Broadcom BCM470X / BCM5301X ARM platform code.
   3  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
   4  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
   5  *
   6  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <dt-bindings/clock/bcm-nsp.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20         interrupt-parent = <&gic>;
  21
  22         chipcommonA@18000000 {
  23                 compatible = "simple-bus";
  24                 ranges = <0x00000000 0x18000000 0x00001000>;
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27
  28                 uart0: serial@300 {
  29                         compatible = "ns16550";
  30                         reg = <0x0300 0x100>;
  31                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  32                         clocks = <&iprocslow>;
  33                         status = "disabled";
  34                 };
  35
  36                 uart1: serial@400 {
  37                         compatible = "ns16550";
  38                         reg = <0x0400 0x100>;
  39                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  40                         clocks = <&iprocslow>;
  41                         pinctrl-names = "default";
  42                         pinctrl-0 = <&pinmux_uart1>;
  43                         status = "disabled";
  44                 };
  45         };
  46
  47         mpcore@19000000 {
  48                 compatible = "simple-bus";
  49                 ranges = <0x00000000 0x19000000 0x00023000>;
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 a9pll: arm_clk@0 {
  54                         #clock-cells = <0>;
  55                         compatible = "brcm,nsp-armpll";
  56                         clocks = <&osc>;
  57                         reg = <0x00000 0x1000>;
  58                 };
  59
  60                 scu@20000 {
  61                         compatible = "arm,cortex-a9-scu";
  62                         reg = <0x20000 0x100>;
  63                 };
  64
  65                 timer@20200 {
  66                         compatible = "arm,cortex-a9-global-timer";
  67                         reg = <0x20200 0x100>;
  68                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  69                         clocks = <&periph_clk>;
  70                 };
  71
  72                 timer@20600 {
  73                         compatible = "arm,cortex-a9-twd-timer";
  74                         reg = <0x20600 0x20>;
  75                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  76                                                   IRQ_TYPE_EDGE_RISING)>;
  77                         clocks = <&periph_clk>;
  78                 };
  79
  80                 watchdog@20620 {
  81                         compatible = "arm,cortex-a9-twd-wdt";
  82                         reg = <0x20620 0x20>;
  83                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  84                                                   IRQ_TYPE_EDGE_RISING)>;
  85                         clocks = <&periph_clk>;
  86                 };
  87
  88                 gic: interrupt-controller@21000 {
  89                         compatible = "arm,cortex-a9-gic";
  90                         #interrupt-cells = <3>;
  91                         #address-cells = <0>;
  92                         interrupt-controller;
  93                         reg = <0x21000 0x1000>,
  94                               <0x20100 0x100>;
  95                 };
  96
  97                 L2: cache-controller@22000 {
  98                         compatible = "arm,pl310-cache";
  99                         reg = <0x22000 0x1000>;
 100                         cache-unified;
 101                         arm,shared-override;
 102                         prefetch-data = <1>;
 103                         prefetch-instr = <1>;
 104                         cache-level = <2>;
 105                 };
 106         };
 107
 108         pmu {
 109                 compatible = "arm,cortex-a9-pmu";
 110                 interrupts =
 111                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 112                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 113         };
 114
 115         clocks {
 116                 #address-cells = <1>;
 117                 #size-cells = <1>;
 118                 ranges;
 119
 120                 osc: oscillator {
 121                         #clock-cells = <0>;
 122                         compatible = "fixed-clock";
 123                         clock-frequency = <25000000>;
 124                 };
 125
 126                 iprocmed: iprocmed {
 127                         #clock-cells = <0>;
 128                         compatible = "fixed-factor-clock";
 129                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 130                         clock-div = <2>;
 131                         clock-mult = <1>;
 132                 };
 133
 134                 iprocslow: iprocslow {
 135                         #clock-cells = <0>;
 136                         compatible = "fixed-factor-clock";
 137                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 138                         clock-div = <4>;
 139                         clock-mult = <1>;
 140                 };
 141
 142                 periph_clk: periph_clk {
 143                         #clock-cells = <0>;
 144                         compatible = "fixed-factor-clock";
 145                         clocks = <&a9pll>;
 146                         clock-div = <2>;
 147                         clock-mult = <1>;
 148                 };
 149         };
 150
 151         usb2_phy: usb2-phy@1800c000 {
 152                 compatible = "brcm,ns-usb2-phy";
 153                 reg = <0x1800c000 0x1000>;
 154                 reg-names = "dmu";
 155                 #phy-cells = <0>;
 156                 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
 157                 clock-names = "phy-ref-clk";
 158         };
 159
 160         axi@18000000 {
 161                 compatible = "brcm,bus-axi";
 162                 reg = <0x18000000 0x1000>;
 163                 ranges = <0x00000000 0x18000000 0x00100000>;
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166
 167                 #interrupt-cells = <1>;
 168                 interrupt-map-mask = <0x000fffff 0xffff>;
 169                 interrupt-map =
 170                         /* ChipCommon */
 171                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 172
 173                         /* Switch Register Access Block */
 174                         <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 175                         <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 176                         <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 177                         <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 178                         <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 179                         <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 180                         <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 181                         <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 182                         <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 183                         <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 184                         <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 185                         <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 186                         <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 187
 188                         /* PCIe Controller 0 */
 189                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 190                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 191                         <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 192                         <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 193                         <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 194                         <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 195
 196                         /* PCIe Controller 1 */
 197                         <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 198                         <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 199                         <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 200                         <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 201                         <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 202                         <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 203
 204                         /* PCIe Controller 2 */
 205                         <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 206                         <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 207                         <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 208                         <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 209                         <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 210                         <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 211
 212                         /* USB 2.0 Controller */
 213                         <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 214
 215                         /* USB 3.0 Controller */
 216                         <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 217
 218                         /* Ethernet Controller 0 */
 219                         <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 220
 221                         /* Ethernet Controller 1 */
 222                         <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 223
 224                         /* Ethernet Controller 2 */
 225                         <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 226
 227                         /* Ethernet Controller 3 */
 228                         <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 229
 230                         /* NAND Controller */
 231                         <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 232                         <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 233                         <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 234                         <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 235                         <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 236                         <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 237                         <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 238                         <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 239
 240                 chipcommon: chipcommon@0 {
 241                         reg = <0x00000000 0x1000>;
 242
 243                         gpio-controller;
 244                         #gpio-cells = <2>;
 245                         interrupt-controller;
 246                         #interrupt-cells = <2>;
 247                 };
 248
 249                 pcie0: pcie@12000 {
 250                         reg = <0x00012000 0x1000>;
 251                 };
 252
 253                 pcie1: pcie@13000 {
 254                         reg = <0x00013000 0x1000>;
 255                 };
 256
 257                 usb2: usb2@21000 {
 258                         reg = <0x00021000 0x1000>;
 259
 260                         #address-cells = <1>;
 261                         #size-cells = <1>;
 262                         ranges;
 263
 264                         interrupt-parent = <&gic>;
 265
 266                         ehci: ehci@21000 {
 267                                 #usb-cells = <0>;
 268
 269                                 compatible = "generic-ehci";
 270                                 reg = <0x00021000 0x1000>;
 271                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 272                                 phys = <&usb2_phy>;
 273
 274                                 #address-cells = <1>;
 275                                 #size-cells = <0>;
 276
 277                                 ehci_port1: port@1 {
 278                                         reg = <1>;
 279                                         #trigger-source-cells = <0>;
 280                                 };
 281
 282                                 ehci_port2: port@2 {
 283                                         reg = <2>;
 284                                         #trigger-source-cells = <0>;
 285                                 };
 286                         };
 287
 288                         ohci: ohci@22000 {
 289                                 #usb-cells = <0>;
 290
 291                                 compatible = "generic-ohci";
 292                                 reg = <0x00022000 0x1000>;
 293                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 294
 295                                 #address-cells = <1>;
 296                                 #size-cells = <0>;
 297
 298                                 ohci_port1: port@1 {
 299                                         reg = <1>;
 300                                         #trigger-source-cells = <0>;
 301                                 };
 302
 303                                 ohci_port2: port@2 {
 304                                         reg = <2>;
 305                                         #trigger-source-cells = <0>;
 306                                 };
 307                         };
 308                 };
 309
 310                 usb3: usb3@23000 {
 311                         reg = <0x00023000 0x1000>;
 312
 313                         #address-cells = <1>;
 314                         #size-cells = <1>;
 315                         ranges;
 316
 317                         interrupt-parent = <&gic>;
 318
 319                         xhci: xhci@23000 {
 320                                 #usb-cells = <0>;
 321
 322                                 compatible = "generic-xhci";
 323                                 reg = <0x00023000 0x1000>;
 324                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 325                                 phys = <&usb3_phy>;
 326                                 phy-names = "usb";
 327
 328                                 #address-cells = <1>;
 329                                 #size-cells = <0>;
 330
 331                                 xhci_port1: port@1 {
 332                                         reg = <1>;
 333                                         #trigger-source-cells = <0>;
 334                                 };
 335                         };
 336                 };
 337
 338                 gmac0: ethernet@24000 {
 339                         reg = <0x24000 0x800>;
 340                 };
 341
 342                 gmac1: ethernet@25000 {
 343                         reg = <0x25000 0x800>;
 344                 };
 345
 346                 gmac2: ethernet@26000 {
 347                         reg = <0x26000 0x800>;
 348                 };
 349
 350                 gmac3: ethernet@27000 {
 351                         reg = <0x27000 0x800>;
 352                 };
 353         };
 354
 355         mdio: mdio@18003000 {
 356                 compatible = "brcm,iproc-mdio";
 357                 reg = <0x18003000 0x8>;
 358                 #size-cells = <0>;
 359                 #address-cells = <1>;
 360         };
 361
 362         mdio-bus-mux@18003000 {
 363                 compatible = "mdio-mux-mmioreg";
 364                 mdio-parent-bus = <&mdio>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 reg = <0x18003000 0x4>;
 368                 mux-mask = <0x200>;
 369
 370                 mdio@0 {
 371                         reg = <0x0>;
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374
 375                         usb3_phy: usb3-phy@10 {
 376                                 compatible = "brcm,ns-ax-usb3-phy";
 377                                 reg = <0x10>;
 378                                 usb3-dmp-syscon = <&usb3_dmp>;
 379                                 #phy-cells = <0>;
 380                                 status = "disabled";
 381                         };
 382                 };
 383         };
 384
 385         usb3_dmp: syscon@18105000 {
 386                 reg = <0x18105000 0x1000>;
 387         };
 388
 389         i2c0: i2c@18009000 {
 390                 compatible = "brcm,iproc-i2c";
 391                 reg = <0x18009000 0x50>;
 392                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-frequency = <100000>;
 396                 status = "disabled";
 397         };
 398
 399         dmu@1800c000 {
 400                 compatible = "simple-bus";
 401                 ranges = <0 0x1800c000 0x1000>;
 402                 #address-cells = <1>;
 403                 #size-cells = <1>;
 404
 405                 cru@100 {
 406                         compatible = "simple-bus";
 407                         reg = <0x100 0x1a4>;
 408                         ranges;
 409                         #address-cells = <1>;
 410                         #size-cells = <1>;
 411
 412                         pin-controller@1c0 {
 413                                 compatible = "brcm,bcm4708-pinmux";
 414                                 reg = <0x1c0 0x24>;
 415                                 reg-names = "cru_gpio_control";
 416
 417                                 spi-pins {
 418                                         groups = "spi_grp";
 419                                         function = "spi";
 420                                 };
 421
 422                                 i2c {
 423                                         groups = "i2c_grp";
 424                                         function = "i2c";
 425                                 };
 426
 427                                 pwm {
 428                                         groups = "pwm0_grp", "pwm1_grp",
 429                                                  "pwm2_grp", "pwm3_grp";
 430                                         function = "pwm";
 431                                 };
 432
 433                                 pinmux_uart1: uart1 {
 434                                         groups = "uart1_grp";
 435                                         function = "uart1";
 436                                 };
 437                         };
 438                 };
 439         };
 440
 441         lcpll0: lcpll0@1800c100 {
 442                 #clock-cells = <1>;
 443                 compatible = "brcm,nsp-lcpll0";
 444                 reg = <0x1800c100 0x14>;
 445                 clocks = <&osc>;
 446                 clock-output-names = "lcpll0", "pcie_phy", "sdio",
 447                                      "ddr_phy";
 448         };
 449
 450         genpll: genpll@1800c140 {
 451                 #clock-cells = <1>;
 452                 compatible = "brcm,nsp-genpll";
 453                 reg = <0x1800c140 0x24>;
 454                 clocks = <&osc>;
 455                 clock-output-names = "genpll", "phy", "ethernetclk",
 456                                      "usbclk", "iprocfast", "sata1",
 457                                      "sata2";
 458         };
 459
 460         thermal: thermal@1800c2c0 {
 461                 compatible = "brcm,ns-thermal";
 462                 reg = <0x1800c2c0 0x10>;
 463                 #thermal-sensor-cells = <0>;
 464         };
 465
 466         srab: srab@18007000 {
 467                 compatible = "brcm,bcm5301x-srab";
 468                 reg = <0x18007000 0x1000>;
 469
 470                 status = "disabled";
 471
 472                 /* ports are defined in board DTS */
 473         };
 474
 475         rng: rng@18004000 {
 476                 compatible = "brcm,bcm5301x-rng";
 477                 reg = <0x18004000 0x14>;
 478         };
 479
 480         nand: nand@18028000 {
 481                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 482                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 483                 reg-names = "nand", "iproc-idm", "iproc-ext";
 484                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 485
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488
 489                 brcm,nand-has-wp;
 490         };
 491
 492         spi@18029200 {
 493                 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
 494                 reg = <0x18029200 0x184>,
 495                       <0x18029000 0x124>,
 496                       <0x1811b408 0x004>,
 497                       <0x180293a0 0x01c>;
 498                 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
 499                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 500                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 501                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 502                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 503                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 504                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 505                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 506                 interrupt-names = "mspi_done",
 507                                   "mspi_halted",
 508                                   "spi_lr_fullness_reached",
 509                                   "spi_lr_session_aborted",
 510                                   "spi_lr_impatient",
 511                                   "spi_lr_session_done",
 512                                   "spi_lr_overread";
 513                 clocks = <&iprocmed>;
 514                 num-cs = <2>;
 515                 #address-cells = <1>;
 516                 #size-cells = <0>;
 517
 518                 spi_nor: flash@0 {
 519                         compatible = "jedec,spi-nor";
 520                         reg = <0>;
 521                         spi-max-frequency = <20000000>;
 522                         status = "disabled";
 523
 524                         partitions {
 525                                 compatible = "brcm,bcm947xx-cfe-partitions";
 526                         };
 527                 };
 528         };
 529
 530         thermal-zones {
 531                 cpu_thermal: cpu-thermal {
 532                         polling-delay-passive = <0>;
 533                         polling-delay = <1000>;
 534                         coefficients = <(-556) 418000>;
 535                         thermal-sensors = <&thermal>;
 536
 537                         trips {
 538                                 cpu-crit {
 539                                         temperature     = <125000>;
 540                                         hysteresis      = <0>;
 541                                         type            = "critical";
 542                                 };
 543                         };
 544
 545                         cooling-maps {
 546                         };
 547                 };
 548         };
 549 };