arch/arm/boot/dts/bcm5301x.dtsi

   1 /*
   2  * Broadcom BCM470X / BCM5301X ARM platform code.
   3  * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
   4  * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
   5  *
   6  * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include <dt-bindings/clock/bcm-nsp.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include "skeleton.dtsi"
  17
  18 / {
  19         interrupt-parent = <&gic>;
  20
  21         chipcommonA {
  22                 compatible = "simple-bus";
  23                 ranges = <0x00000000 0x18000000 0x00001000>;
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26
  27                 uart0: serial@300 {
  28                         compatible = "ns16550";
  29                         reg = <0x0300 0x100>;
  30                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  31                         clocks = <&iprocslow>;
  32                         status = "disabled";
  33                 };
  34
  35                 uart1: serial@400 {
  36                         compatible = "ns16550";
  37                         reg = <0x0400 0x100>;
  38                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  39                         clocks = <&iprocslow>;
  40                         status = "disabled";
  41                 };
  42         };
  43
  44         mpcore {
  45                 compatible = "simple-bus";
  46                 ranges = <0x00000000 0x19000000 0x00023000>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49
  50                 a9pll: arm_clk@0 {
  51                         #clock-cells = <0>;
  52                         compatible = "brcm,nsp-armpll";
  53                         clocks = <&osc>;
  54                         reg = <0x00000 0x1000>;
  55                 };
  56
  57                 scu@20000 {
  58                         compatible = "arm,cortex-a9-scu";
  59                         reg = <0x20000 0x100>;
  60                 };
  61
  62                 timer@20200 {
  63                         compatible = "arm,cortex-a9-global-timer";
  64                         reg = <0x20200 0x100>;
  65                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  66                         clocks = <&periph_clk>;
  67                 };
  68
  69                 timer@20600 {
  70                         compatible = "arm,cortex-a9-twd-timer";
  71                         reg = <0x20600 0x20>;
  72                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  73                                                   IRQ_TYPE_EDGE_RISING)>;
  74                         clocks = <&periph_clk>;
  75                 };
  76
  77                 watchdog@20620 {
  78                         compatible = "arm,cortex-a9-twd-wdt";
  79                         reg = <0x20620 0x20>;
  80                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  81                                                   IRQ_TYPE_EDGE_RISING)>;
  82                         clocks = <&periph_clk>;
  83                 };
  84
  85                 gic: interrupt-controller@21000 {
  86                         compatible = "arm,cortex-a9-gic";
  87                         #interrupt-cells = <3>;
  88                         #address-cells = <0>;
  89                         interrupt-controller;
  90                         reg = <0x21000 0x1000>,
  91                               <0x20100 0x100>;
  92                 };
  93
  94                 L2: cache-controller@22000 {
  95                         compatible = "arm,pl310-cache";
  96                         reg = <0x22000 0x1000>;
  97                         cache-unified;
  98                         arm,shared-override;
  99                         prefetch-data = <1>;
 100                         prefetch-instr = <1>;
 101                         cache-level = <2>;
 102                 };
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a9-pmu";
 107                 interrupts =
 108                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 109                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 110         };
 111
 112         clocks {
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 ranges;
 116
 117                 osc: oscillator {
 118                         #clock-cells = <0>;
 119                         compatible = "fixed-clock";
 120                         clock-frequency = <25000000>;
 121                 };
 122
 123                 iprocmed: iprocmed {
 124                         #clock-cells = <0>;
 125                         compatible = "fixed-factor-clock";
 126                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 127                         clock-div = <2>;
 128                         clock-mult = <1>;
 129                 };
 130
 131                 iprocslow: iprocslow {
 132                         #clock-cells = <0>;
 133                         compatible = "fixed-factor-clock";
 134                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 135                         clock-div = <4>;
 136                         clock-mult = <1>;
 137                 };
 138
 139                 periph_clk: periph_clk {
 140                         #clock-cells = <0>;
 141                         compatible = "fixed-factor-clock";
 142                         clocks = <&a9pll>;
 143                         clock-div = <2>;
 144                         clock-mult = <1>;
 145                 };
 146         };
 147
 148         usb2_phy: usb2-phy {
 149                 compatible = "brcm,ns-usb2-phy";
 150                 reg = <0x1800c000 0x1000>;
 151                 reg-names = "dmu";
 152                 #phy-cells = <0>;
 153                 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
 154                 clock-names = "phy-ref-clk";
 155         };
 156
 157         axi@18000000 {
 158                 compatible = "brcm,bus-axi";
 159                 reg = <0x18000000 0x1000>;
 160                 ranges = <0x00000000 0x18000000 0x00100000>;
 161                 #address-cells = <1>;
 162                 #size-cells = <1>;
 163
 164                 #interrupt-cells = <1>;
 165                 interrupt-map-mask = <0x000fffff 0xffff>;
 166                 interrupt-map =
 167                         /* ChipCommon */
 168                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 169
 170                         /* Switch Register Access Block */
 171                         <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 172                         <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 173                         <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 174                         <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 175                         <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 176                         <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 177                         <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 178                         <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 179                         <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 180                         <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 181                         <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 182                         <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 183                         <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 184
 185                         /* PCIe Controller 0 */
 186                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 187                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 188                         <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 189                         <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 190                         <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 191                         <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 192
 193                         /* PCIe Controller 1 */
 194                         <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 195                         <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 196                         <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 197                         <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 198                         <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 199                         <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 200
 201                         /* PCIe Controller 2 */
 202                         <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 203                         <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 204                         <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 205                         <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 206                         <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 207                         <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 208
 209                         /* USB 2.0 Controller */
 210                         <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 211
 212                         /* USB 3.0 Controller */
 213                         <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 214
 215                         /* Ethernet Controller 0 */
 216                         <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 217
 218                         /* Ethernet Controller 1 */
 219                         <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 220
 221                         /* Ethernet Controller 2 */
 222                         <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 223
 224                         /* Ethernet Controller 3 */
 225                         <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 226
 227                         /* NAND Controller */
 228                         <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 229                         <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 230                         <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 231                         <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 232                         <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 233                         <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 234                         <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 235                         <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 236
 237                 chipcommon: chipcommon@0 {
 238                         reg = <0x00000000 0x1000>;
 239
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <2>;
 244                 };
 245
 246                 pcie0: pcie@12000 {
 247                         reg = <0x00012000 0x1000>;
 248                 };
 249
 250                 pcie1: pcie@13000 {
 251                         reg = <0x00013000 0x1000>;
 252                 };
 253
 254                 usb2: usb2@21000 {
 255                         reg = <0x00021000 0x1000>;
 256
 257                         #address-cells = <1>;
 258                         #size-cells = <1>;
 259                         ranges;
 260
 261                         interrupt-parent = <&gic>;
 262
 263                         ehci: ehci@21000 {
 264                                 #usb-cells = <0>;
 265
 266                                 compatible = "generic-ehci";
 267                                 reg = <0x00021000 0x1000>;
 268                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 269                                 phys = <&usb2_phy>;
 270
 271                                 #address-cells = <1>;
 272                                 #size-cells = <0>;
 273
 274                                 ehci_port1: port@1 {
 275                                         reg = <1>;
 276                                         #trigger-source-cells = <0>;
 277                                 };
 278
 279                                 ehci_port2: port@2 {
 280                                         reg = <2>;
 281                                         #trigger-source-cells = <0>;
 282                                 };
 283                         };
 284
 285                         ohci: ohci@22000 {
 286                                 #usb-cells = <0>;
 287
 288                                 compatible = "generic-ohci";
 289                                 reg = <0x00022000 0x1000>;
 290                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 291
 292                                 #address-cells = <1>;
 293                                 #size-cells = <0>;
 294
 295                                 ohci_port1: port@1 {
 296                                         reg = <1>;
 297                                         #trigger-source-cells = <0>;
 298                                 };
 299
 300                                 ohci_port2: port@2 {
 301                                         reg = <2>;
 302                                         #trigger-source-cells = <0>;
 303                                 };
 304                         };
 305                 };
 306
 307                 usb3: usb3@23000 {
 308                         reg = <0x00023000 0x1000>;
 309
 310                         #address-cells = <1>;
 311                         #size-cells = <1>;
 312                         ranges;
 313
 314                         interrupt-parent = <&gic>;
 315
 316                         xhci: xhci@23000 {
 317                                 #usb-cells = <0>;
 318
 319                                 compatible = "generic-xhci";
 320                                 reg = <0x00023000 0x1000>;
 321                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 322                                 phys = <&usb3_phy>;
 323                                 phy-names = "usb";
 324
 325                                 #address-cells = <1>;
 326                                 #size-cells = <0>;
 327
 328                                 xhci_port1: port@1 {
 329                                         reg = <1>;
 330                                         #trigger-source-cells = <0>;
 331                                 };
 332                         };
 333                 };
 334
 335                 gmac0: ethernet@24000 {
 336                         reg = <0x24000 0x800>;
 337                 };
 338
 339                 gmac1: ethernet@25000 {
 340                         reg = <0x25000 0x800>;
 341                 };
 342
 343                 gmac2: ethernet@26000 {
 344                         reg = <0x26000 0x800>;
 345                 };
 346
 347                 gmac3: ethernet@27000 {
 348                         reg = <0x27000 0x800>;
 349                 };
 350         };
 351
 352         mdio: mdio@18003000 {
 353                 compatible = "brcm,iproc-mdio";
 354                 reg = <0x18003000 0x8>;
 355                 #size-cells = <0>;
 356                 #address-cells = <1>;
 357         };
 358
 359         mdio-bus-mux {
 360                 compatible = "mdio-mux-mmioreg";
 361                 mdio-parent-bus = <&mdio>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 reg = <0x18003000 0x4>;
 365                 mux-mask = <0x200>;
 366
 367                 mdio@0 {
 368                         reg = <0x0>;
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371
 372                         usb3_phy: usb3-phy@10 {
 373                                 compatible = "brcm,ns-ax-usb3-phy";
 374                                 reg = <0x10>;
 375                                 usb3-dmp-syscon = <&usb3_dmp>;
 376                                 #phy-cells = <0>;
 377                                 status = "disabled";
 378                         };
 379                 };
 380         };
 381
 382         usb3_dmp: syscon@18105000 {
 383                 reg = <0x18105000 0x1000>;
 384         };
 385
 386         i2c0: i2c@18009000 {
 387                 compatible = "brcm,iproc-i2c";
 388                 reg = <0x18009000 0x50>;
 389                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 clock-frequency = <100000>;
 393                 status = "disabled";
 394         };
 395
 396         lcpll0: lcpll0@1800c100 {
 397                 #clock-cells = <1>;
 398                 compatible = "brcm,nsp-lcpll0";
 399                 reg = <0x1800c100 0x14>;
 400                 clocks = <&osc>;
 401                 clock-output-names = "lcpll0", "pcie_phy", "sdio",
 402                                      "ddr_phy";
 403         };
 404
 405         genpll: genpll@1800c140 {
 406                 #clock-cells = <1>;
 407                 compatible = "brcm,nsp-genpll";
 408                 reg = <0x1800c140 0x24>;
 409                 clocks = <&osc>;
 410                 clock-output-names = "genpll", "phy", "ethernetclk",
 411                                      "usbclk", "iprocfast", "sata1",
 412                                      "sata2";
 413         };
 414
 415         thermal: thermal@1800c2c0 {
 416                 compatible = "brcm,ns-thermal";
 417                 reg = <0x1800c2c0 0x10>;
 418                 #thermal-sensor-cells = <0>;
 419         };
 420
 421         srab: srab@18007000 {
 422                 compatible = "brcm,bcm5301x-srab";
 423                 reg = <0x18007000 0x1000>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426
 427                 status = "disabled";
 428
 429                 /* ports are defined in board DTS */
 430         };
 431
 432         rng: rng@18004000 {
 433                 compatible = "brcm,bcm5301x-rng";
 434                 reg = <0x18004000 0x14>;
 435         };
 436
 437         nand: nand@18028000 {
 438                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
 439                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
 440                 reg-names = "nand", "iproc-idm", "iproc-ext";
 441                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 442
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445
 446                 brcm,nand-has-wp;
 447         };
 448
 449         spi@18029200 {
 450                 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
 451                 reg = <0x18029200 0x184>,
 452                       <0x18029000 0x124>,
 453                       <0x1811b408 0x004>,
 454                       <0x180293a0 0x01c>;
 455                 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
 456                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 461                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 462                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 463                 interrupt-names = "mspi_done",
 464                                   "mspi_halted",
 465                                   "spi_lr_fullness_reached",
 466                                   "spi_lr_session_aborted",
 467                                   "spi_lr_impatient",
 468                                   "spi_lr_session_done",
 469                                   "spi_lr_overread";
 470                 clocks = <&iprocmed>;
 471                 clock-names = "iprocmed";
 472                 num-cs = <2>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475
 476                 spi_nor: flash@0 {
 477                         compatible = "jedec,spi-nor";
 478                         reg = <0>;
 479                         spi-max-frequency = <20000000>;
 480                         linux,part-probe = "ofpart", "bcm47xxpart";
 481                         status = "disabled";
 482                 };
 483         };
 484
 485         thermal-zones {
 486                 cpu_thermal: cpu-thermal {
 487                         polling-delay-passive = <0>;
 488                         polling-delay = <1000>;
 489                         coefficients = <(-556) 418000>;
 490                         thermal-sensors = <&thermal>;
 491
 492                         trips {
 493                                 cpu-crit {
 494                                         temperature     = <125000>;
 495                                         hysteresis      = <0>;
 496                                         type            = "critical";
 497                                 };
 498                         };
 499
 500                         cooling-maps {
 501                         };
 502                 };
 503         };
 504 };