1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2022 Broadcom Ltd.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "brcm,bcm47622", "brcm,bcmbca";
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
24 next-level-cache = <&L2_0>;
25 enable-method = "psci";
30 compatible = "arm,cortex-a7";
32 next-level-cache = <&L2_0>;
33 enable-method = "psci";
37 compatible = "arm,cortex-a7";
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
44 compatible = "arm,cortex-a7";
46 next-level-cache = <&L2_0>;
47 enable-method = "psci";
55 compatible = "arm,armv7-timer";
56 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
57 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
60 arm,cpu-registers-not-fw-configured;
64 compatible = "arm,cortex-a7-pmu";
65 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&CA7_0>, <&CA7_1>,
74 periph_clk: periph-clk {
75 compatible = "fixed-clock";
77 clock-frequency = <200000000>;
80 compatible = "fixed-factor-clock";
82 clocks = <&periph_clk>;
89 compatible = "arm,psci-0.2";
96 compatible = "simple-bus";
99 ranges = <0 0x81000000 0x818000>;
101 gic: interrupt-controller@1000 {
102 compatible = "arm,cortex-a7-gic";
103 #interrupt-cells = <3>;
104 #address-cells = <0>;
105 interrupt-controller;
106 reg = <0x1000 0x1000>,
112 compatible = "simple-bus";
113 #address-cells = <1>;
115 ranges = <0 0xff800000 0x800000>;
117 uart0: serial@12000 {
118 compatible = "arm,pl011", "arm,primecell";
119 reg = <0x12000 0x1000>;
120 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&uart_clk>, <&uart_clk>;
122 clock-names = "uartclk", "apb_pclk";