1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
11 /memreserve/ 0x00000000 0x00001000;
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
19 compatible = "brcm,bcm2835";
21 interrupt-parent = <&intc>;
31 stdout-path = "serial0:115200n8";
35 cpu_thermal: cpu-thermal {
36 polling-delay-passive = <0>;
37 polling-delay = <1000>;
39 thermal-sensors = <&thermal>;
43 temperature = <90000>;
55 compatible = "simple-bus";
60 compatible = "brcm,bcm2835-system-timer";
61 reg = <0x7e003000 0x1000>;
62 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
63 /* This could be a reference to BCM2835_CLOCK_TIMER,
64 * but we don't have the driver using the common clock
67 clock-frequency = <1000000>;
71 compatible = "brcm,bcm2835-txp";
72 reg = <0x7e004000 0x20>;
77 compatible = "brcm,bcm2835-dma";
78 reg = <0x7e007000 0xf00>;
90 /* dma channel 11-14 share one irq */
95 /* unused shared irq for all channels */
97 interrupt-names = "dma0",
114 brcm,dma-channel-mask = <0x7f35>;
117 intc: interrupt-controller@7e00b200 {
118 compatible = "brcm,bcm2835-armctrl-ic";
119 reg = <0x7e00b200 0x200>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
124 pm: watchdog@7e100000 {
125 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
126 #power-domain-cells = <1>;
128 reg = <0x7e100000 0x114>,
130 clocks = <&clocks BCM2835_CLOCK_V3D>,
131 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
132 <&clocks BCM2835_CLOCK_H264>,
133 <&clocks BCM2835_CLOCK_ISP>;
134 clock-names = "v3d", "peri_image", "h264", "isp";
135 system-power-controller;
138 clocks: cprman@7e101000 {
139 compatible = "brcm,bcm2835-cprman";
141 reg = <0x7e101000 0x2000>;
143 /* CPRMAN derives almost everything from the
144 * platform's oscillator. However, the DSI
145 * pixel clocks come from the DSI analog PHY.
148 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
149 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
153 compatible = "brcm,bcm2835-rng";
154 reg = <0x7e104000 0x10>;
158 mailbox: mailbox@7e00b880 {
159 compatible = "brcm,bcm2835-mbox";
160 reg = <0x7e00b880 0x40>;
165 gpio: gpio@7e200000 {
166 compatible = "brcm,bcm2835-gpio";
167 reg = <0x7e200000 0xb4>;
169 * The GPIO IP block is designed for 3 banks of GPIOs.
170 * Each bank has a GPIO interrupt for itself.
171 * There is an overall "any bank" interrupt.
172 * In order, these are GIC interrupts 17, 18, 19, 20.
173 * Since the BCM2835 only has 2 banks, the 2nd bank
174 * interrupt output appears to be mirrored onto the
175 * 3rd bank's interrupt signal.
176 * So, a bank0 interrupt shows up on 17, 20, and
177 * a bank1 interrupt shows up on 18, 19, 20!
179 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 gpio-ranges = <&gpio 0 0 54>;
188 /* Defines pin muxing groups according to
189 * BCM2835-ARM-Peripherals.pdf page 102.
191 * While each pin can have its mux selected
192 * for various functions individually, some
193 * groups only make sense to switch to a
194 * particular function together.
196 dpi_gpio0: dpi_gpio0 {
197 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
198 12 13 14 15 16 17 18 19
199 20 21 22 23 24 25 26 27>;
200 brcm,function = <BCM2835_FSEL_ALT2>;
202 emmc_gpio22: emmc_gpio22 {
203 brcm,pins = <22 23 24 25 26 27>;
204 brcm,function = <BCM2835_FSEL_ALT3>;
206 emmc_gpio34: emmc_gpio34 {
207 brcm,pins = <34 35 36 37 38 39>;
208 brcm,function = <BCM2835_FSEL_ALT3>;
209 brcm,pull = <BCM2835_PUD_OFF
216 emmc_gpio48: emmc_gpio48 {
217 brcm,pins = <48 49 50 51 52 53>;
218 brcm,function = <BCM2835_FSEL_ALT3>;
221 gpclk0_gpio4: gpclk0_gpio4 {
223 brcm,function = <BCM2835_FSEL_ALT0>;
225 gpclk1_gpio5: gpclk1_gpio5 {
227 brcm,function = <BCM2835_FSEL_ALT0>;
229 gpclk1_gpio42: gpclk1_gpio42 {
231 brcm,function = <BCM2835_FSEL_ALT0>;
233 gpclk1_gpio44: gpclk1_gpio44 {
235 brcm,function = <BCM2835_FSEL_ALT0>;
237 gpclk2_gpio6: gpclk2_gpio6 {
239 brcm,function = <BCM2835_FSEL_ALT0>;
241 gpclk2_gpio43: gpclk2_gpio43 {
243 brcm,function = <BCM2835_FSEL_ALT0>;
244 brcm,pull = <BCM2835_PUD_OFF>;
247 i2c0_gpio0: i2c0_gpio0 {
249 brcm,function = <BCM2835_FSEL_ALT0>;
251 i2c0_gpio28: i2c0_gpio28 {
253 brcm,function = <BCM2835_FSEL_ALT0>;
255 i2c0_gpio44: i2c0_gpio44 {
257 brcm,function = <BCM2835_FSEL_ALT1>;
259 i2c1_gpio2: i2c1_gpio2 {
261 brcm,function = <BCM2835_FSEL_ALT0>;
263 i2c1_gpio44: i2c1_gpio44 {
265 brcm,function = <BCM2835_FSEL_ALT2>;
267 i2c_slave_gpio18: i2c_slave_gpio18 {
268 brcm,pins = <18 19 20 21>;
269 brcm,function = <BCM2835_FSEL_ALT3>;
272 jtag_gpio4: jtag_gpio4 {
273 brcm,pins = <4 5 6 12 13>;
274 brcm,function = <BCM2835_FSEL_ALT5>;
276 jtag_gpio22: jtag_gpio22 {
277 brcm,pins = <22 23 24 25 26 27>;
278 brcm,function = <BCM2835_FSEL_ALT4>;
281 pcm_gpio18: pcm_gpio18 {
282 brcm,pins = <18 19 20 21>;
283 brcm,function = <BCM2835_FSEL_ALT0>;
285 pcm_gpio28: pcm_gpio28 {
286 brcm,pins = <28 29 30 31>;
287 brcm,function = <BCM2835_FSEL_ALT2>;
290 pwm0_gpio12: pwm0_gpio12 {
292 brcm,function = <BCM2835_FSEL_ALT0>;
294 pwm0_gpio18: pwm0_gpio18 {
296 brcm,function = <BCM2835_FSEL_ALT5>;
298 pwm0_gpio40: pwm0_gpio40 {
300 brcm,function = <BCM2835_FSEL_ALT0>;
302 pwm1_gpio13: pwm1_gpio13 {
304 brcm,function = <BCM2835_FSEL_ALT0>;
306 pwm1_gpio19: pwm1_gpio19 {
308 brcm,function = <BCM2835_FSEL_ALT5>;
310 pwm1_gpio41: pwm1_gpio41 {
312 brcm,function = <BCM2835_FSEL_ALT0>;
314 pwm1_gpio45: pwm1_gpio45 {
316 brcm,function = <BCM2835_FSEL_ALT0>;
319 sdhost_gpio48: sdhost_gpio48 {
320 brcm,pins = <48 49 50 51 52 53>;
321 brcm,function = <BCM2835_FSEL_ALT0>;
324 spi0_gpio7: spi0_gpio7 {
325 brcm,pins = <7 8 9 10 11>;
326 brcm,function = <BCM2835_FSEL_ALT0>;
328 spi0_gpio35: spi0_gpio35 {
329 brcm,pins = <35 36 37 38 39>;
330 brcm,function = <BCM2835_FSEL_ALT0>;
332 spi1_gpio16: spi1_gpio16 {
333 brcm,pins = <16 17 18 19 20 21>;
334 brcm,function = <BCM2835_FSEL_ALT4>;
336 spi2_gpio40: spi2_gpio40 {
337 brcm,pins = <40 41 42 43 44 45>;
338 brcm,function = <BCM2835_FSEL_ALT4>;
341 uart0_gpio14: uart0_gpio14 {
343 brcm,function = <BCM2835_FSEL_ALT0>;
345 /* Separate from the uart0_gpio14 group
346 * because it conflicts with spi1_gpio16, and
347 * people often run uart0 on the two pins
348 * without flow control.
350 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
352 brcm,function = <BCM2835_FSEL_ALT3>;
354 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
356 brcm,function = <BCM2835_FSEL_ALT3>;
357 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
359 uart0_gpio32: uart0_gpio32 {
361 brcm,function = <BCM2835_FSEL_ALT3>;
362 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
364 uart0_gpio36: uart0_gpio36 {
366 brcm,function = <BCM2835_FSEL_ALT2>;
368 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
370 brcm,function = <BCM2835_FSEL_ALT2>;
373 uart1_gpio14: uart1_gpio14 {
375 brcm,function = <BCM2835_FSEL_ALT5>;
377 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
379 brcm,function = <BCM2835_FSEL_ALT5>;
381 uart1_gpio32: uart1_gpio32 {
383 brcm,function = <BCM2835_FSEL_ALT5>;
385 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
387 brcm,function = <BCM2835_FSEL_ALT5>;
389 uart1_gpio40: uart1_gpio40 {
391 brcm,function = <BCM2835_FSEL_ALT5>;
393 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
395 brcm,function = <BCM2835_FSEL_ALT5>;
399 uart0: serial@7e201000 {
400 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
401 reg = <0x7e201000 0x200>;
403 clocks = <&clocks BCM2835_CLOCK_UART>,
404 <&clocks BCM2835_CLOCK_VPU>;
405 clock-names = "uartclk", "apb_pclk";
406 arm,primecell-periphid = <0x00241011>;
409 sdhost: mmc@7e202000 {
410 compatible = "brcm,bcm2835-sdhost";
411 reg = <0x7e202000 0x100>;
413 clocks = <&clocks BCM2835_CLOCK_VPU>;
420 compatible = "brcm,bcm2835-i2s";
421 reg = <0x7e203000 0x24>;
422 clocks = <&clocks BCM2835_CLOCK_PCM>;
426 dma-names = "tx", "rx";
431 compatible = "brcm,bcm2835-spi";
432 reg = <0x7e204000 0x200>;
434 clocks = <&clocks BCM2835_CLOCK_VPU>;
435 dmas = <&dma 6>, <&dma 7>;
436 dma-names = "tx", "rx";
437 #address-cells = <1>;
443 compatible = "brcm,bcm2835-i2c";
444 reg = <0x7e205000 0x200>;
446 clocks = <&clocks BCM2835_CLOCK_VPU>;
447 #address-cells = <1>;
452 pixelvalve@7e206000 {
453 compatible = "brcm,bcm2835-pixelvalve0";
454 reg = <0x7e206000 0x100>;
455 interrupts = <2 13>; /* pwa0 */
458 pixelvalve@7e207000 {
459 compatible = "brcm,bcm2835-pixelvalve1";
460 reg = <0x7e207000 0x100>;
461 interrupts = <2 14>; /* pwa1 */
465 compatible = "brcm,bcm2835-dpi";
466 reg = <0x7e208000 0x8c>;
467 clocks = <&clocks BCM2835_CLOCK_VPU>,
468 <&clocks BCM2835_CLOCK_DPI>;
469 clock-names = "core", "pixel";
470 #address-cells = <1>;
476 compatible = "brcm,bcm2835-dsi0";
477 reg = <0x7e209000 0x78>;
479 #address-cells = <1>;
483 clocks = <&clocks BCM2835_PLLA_DSI0>,
484 <&clocks BCM2835_CLOCK_DSI0E>,
485 <&clocks BCM2835_CLOCK_DSI0P>;
486 clock-names = "phy", "escape", "pixel";
488 clock-output-names = "dsi0_byte",
495 thermal: thermal@7e212000 {
496 compatible = "brcm,bcm2835-thermal";
497 reg = <0x7e212000 0x8>;
498 clocks = <&clocks BCM2835_CLOCK_TSENS>;
499 #thermal-sensor-cells = <0>;
504 compatible = "brcm,bcm2835-aux";
506 reg = <0x7e215000 0x8>;
507 clocks = <&clocks BCM2835_CLOCK_VPU>;
510 uart1: serial@7e215040 {
511 compatible = "brcm,bcm2835-aux-uart";
512 reg = <0x7e215040 0x40>;
514 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
519 compatible = "brcm,bcm2835-aux-spi";
520 reg = <0x7e215080 0x40>;
522 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
523 #address-cells = <1>;
529 compatible = "brcm,bcm2835-aux-spi";
530 reg = <0x7e2150c0 0x40>;
532 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
533 #address-cells = <1>;
539 compatible = "brcm,bcm2835-pwm";
540 reg = <0x7e20c000 0x28>;
541 clocks = <&clocks BCM2835_CLOCK_PWM>;
542 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
543 assigned-clock-rates = <10000000>;
548 sdhci: sdhci@7e300000 {
549 compatible = "brcm,bcm2835-sdhci";
550 reg = <0x7e300000 0x100>;
552 clocks = <&clocks BCM2835_CLOCK_EMMC>;
557 compatible = "brcm,bcm2835-hvs";
558 reg = <0x7e400000 0x6000>;
563 compatible = "brcm,bcm2835-dsi1";
564 reg = <0x7e700000 0x8c>;
566 #address-cells = <1>;
570 clocks = <&clocks BCM2835_PLLD_DSI1>,
571 <&clocks BCM2835_CLOCK_DSI1E>,
572 <&clocks BCM2835_CLOCK_DSI1P>;
573 clock-names = "phy", "escape", "pixel";
575 clock-output-names = "dsi1_byte",
583 compatible = "brcm,bcm2835-i2c";
584 reg = <0x7e804000 0x1000>;
586 clocks = <&clocks BCM2835_CLOCK_VPU>;
587 #address-cells = <1>;
593 compatible = "brcm,bcm2835-i2c";
594 reg = <0x7e805000 0x1000>;
596 clocks = <&clocks BCM2835_CLOCK_VPU>;
597 #address-cells = <1>;
603 compatible = "brcm,bcm2835-vec";
604 reg = <0x7e806000 0x1000>;
605 clocks = <&clocks BCM2835_CLOCK_VEC>;
610 pixelvalve@7e807000 {
611 compatible = "brcm,bcm2835-pixelvalve2";
612 reg = <0x7e807000 0x100>;
613 interrupts = <2 10>; /* pixelvalve */
616 hdmi: hdmi@7e902000 {
617 compatible = "brcm,bcm2835-hdmi";
618 reg = <0x7e902000 0x600>,
620 interrupts = <2 8>, <2 9>;
622 clocks = <&clocks BCM2835_PLLH_PIX>,
623 <&clocks BCM2835_CLOCK_HSM>;
624 clock-names = "pixel", "hdmi";
626 dma-names = "audio-rx";
631 compatible = "brcm,bcm2835-usb";
632 reg = <0x7e980000 0x10000>;
634 #address-cells = <1>;
639 phy-names = "usb2-phy";
643 compatible = "brcm,bcm2835-v3d";
644 reg = <0x7ec00000 0x1000>;
646 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
650 compatible = "brcm,bcm2835-vc4";
655 compatible = "simple-bus";
656 #address-cells = <1>;
659 /* The oscillator is the root of the clock tree. */
661 compatible = "fixed-clock";
664 clock-output-names = "osc";
665 clock-frequency = <19200000>;
669 compatible = "fixed-clock";
672 clock-output-names = "otg";
673 clock-frequency = <480000000>;
678 compatible = "usb-nop-xceiv";