1 #include "bcm283x.dtsi"
4 compatible = "brcm,bcm2837";
7 ranges = <0x7e000000 0x3f000000 0x1000000>,
8 <0x40000000 0x40000000 0x00001000>;
9 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
11 local_intc: local_intc@40000000 {
12 compatible = "brcm,bcm2836-l1-intc";
13 reg = <0x40000000 0x100>;
15 #interrupt-cells = <1>;
16 interrupt-parent = <&local_intc>;
21 compatible = "arm,armv7-timer";
22 interrupt-parent = <&local_intc>;
23 interrupts = <0>, // PHYS_SECURE_PPI
24 <1>, // PHYS_NONSECURE_PPI
33 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
35 /* Source for d/i-cache-line-size and d/i-cache-sets
36 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
37 * /about-the-l1-memory-system?lang=en
39 * Source for d/i-cache-size
40 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
44 compatible = "arm,cortex-a53";
46 enable-method = "spin-table";
47 cpu-release-addr = <0x0 0x000000d8>;
48 d-cache-size = <0x8000>;
49 d-cache-line-size = <64>;
50 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
51 i-cache-size = <0x8000>;
52 i-cache-line-size = <64>;
53 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
54 next-level-cache = <&l2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "spin-table";
62 cpu-release-addr = <0x0 0x000000e0>;
63 d-cache-size = <0x8000>;
64 d-cache-line-size = <64>;
65 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
66 i-cache-size = <0x8000>;
67 i-cache-line-size = <64>;
68 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
69 next-level-cache = <&l2>;
74 compatible = "arm,cortex-a53";
76 enable-method = "spin-table";
77 cpu-release-addr = <0x0 0x000000e8>;
78 d-cache-size = <0x8000>;
79 d-cache-line-size = <64>;
80 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
81 i-cache-size = <0x8000>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
84 next-level-cache = <&l2>;
89 compatible = "arm,cortex-a53";
91 enable-method = "spin-table";
92 cpu-release-addr = <0x0 0x000000f0>;
93 d-cache-size = <0x8000>;
94 d-cache-line-size = <64>;
95 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
96 i-cache-size = <0x8000>;
97 i-cache-line-size = <64>;
98 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
99 next-level-cache = <&l2>;
102 /* Source for cache-line-size + cache-sets
103 * https://developer.arm.com/documentation/ddi0500
104 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
105 * Source for cache-size
106 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
109 compatible = "cache";
110 cache-size = <0x80000>;
111 cache-line-size = <64>;
112 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
118 /* Make the BCM2835-style global interrupt controller be a child of the
119 * CPU-local interrupt controller.
122 compatible = "brcm,bcm2836-armctrl-ic";
123 reg = <0x7e00b200 0x200>;
124 interrupt-parent = <&local_intc>;
129 coefficients = <(-538) 412000>;
132 /* enable thermal sensor with the correct compatible property set */
134 compatible = "brcm,bcm2837-thermal";