arch/arm/boot/dts/bcm2836.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "bcm283x.dtsi"
   3 #include "bcm2835-common.dtsi"
   4 #include "bcm2835-rpi-common.dtsi"
   5
   6 / {
   7         compatible = "brcm,bcm2836";
   8
   9         soc {
  10                 ranges = <0x7e000000 0x3f000000 0x1000000>,
  11                          <0x40000000 0x40000000 0x00001000>;
  12                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
  13
  14                 local_intc: local_intc@40000000 {
  15                         compatible = "brcm,bcm2836-l1-intc";
  16                         reg = <0x40000000 0x100>;
  17                         interrupt-controller;
  18                         #interrupt-cells = <2>;
  19                         interrupt-parent = <&local_intc>;
  20                 };
  21         };
  22
  23         arm-pmu {
  24                 compatible = "arm,cortex-a7-pmu";
  25                 interrupt-parent = <&local_intc>;
  26                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  27         };
  28
  29         timer {
  30                 compatible = "arm,armv7-timer";
  31                 interrupt-parent = <&local_intc>;
  32                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
  33                              <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
  34                              <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
  35                              <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
  36                 always-on;
  37         };
  38
  39         cpus: cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42                 enable-method = "brcm,bcm2836-smp";
  43
  44                 /* Source for d/i-cache-line-size and d/i-cache-sets
  45                  * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System
  46                  * /About-the-L1-memory-system?lang=en
  47                  *
  48                  * Source for d/i-cache-size
  49                  * https://forums.raspberrypi.com/viewtopic.php?t=98428
  50                  */
  51
  52                 v7_cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a7";
  55                         reg = <0xf00>;
  56                         clock-frequency = <800000000>;
  57                         d-cache-size = <0x8000>;
  58                         d-cache-line-size = <64>;
  59                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  60                         i-cache-size = <0x8000>;
  61                         i-cache-line-size = <32>;
  62                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
  63                         next-level-cache = <&l2>;
  64                 };
  65
  66                 v7_cpu1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a7";
  69                         reg = <0xf01>;
  70                         clock-frequency = <800000000>;
  71                         d-cache-size = <0x8000>;
  72                         d-cache-line-size = <64>;
  73                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  74                         i-cache-size = <0x8000>;
  75                         i-cache-line-size = <32>;
  76                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
  77                         next-level-cache = <&l2>;
  78                 };
  79
  80                 v7_cpu2: cpu@2 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a7";
  83                         reg = <0xf02>;
  84                         clock-frequency = <800000000>;
  85                         d-cache-size = <0x8000>;
  86                         d-cache-line-size = <64>;
  87                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
  88                         i-cache-size = <0x8000>;
  89                         i-cache-line-size = <32>;
  90                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
  91                         next-level-cache = <&l2>;
  92                 };
  93
  94                 v7_cpu3: cpu@3 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a7";
  97                         reg = <0xf03>;
  98                         clock-frequency = <800000000>;
  99                         d-cache-size = <0x8000>;
 100                         d-cache-line-size = <64>;
 101                         d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
 102                         i-cache-size = <0x8000>;
 103                         i-cache-line-size = <32>;
 104                         i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
 105                         next-level-cache = <&l2>;
 106                 };
 107
 108                 /* Source for cache-line-size + cache-sets
 109                  * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System
 110                  * /About-the-L2-Memory-system?lang=en
 111                  * Source for cache-size
 112                  * https://forums.raspberrypi.com/viewtopic.php?t=98428
 113                  */
 114                 l2: l2-cache0 {
 115                         compatible = "cache";
 116                         cache-size = <0x80000>;
 117                         cache-line-size = <64>;
 118                         cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
 119                         cache-level = <2>;
 120                 };
 121         };
 122 };
 123
 124 /* Make the BCM2835-style global interrupt controller be a child of the
 125  * CPU-local interrupt controller.
 126  */
 127 &intc {
 128         compatible = "brcm,bcm2836-armctrl-ic";
 129         reg = <0x7e00b200 0x200>;
 130         interrupt-parent = <&local_intc>;
 131         interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 132 };
 133
 134 &cpu_thermal {
 135         coefficients = <(-538)  407000>;
 136 };
 137
 138 /* enable thermal sensor with the correct compatible property set */
 139 &thermal {
 140         compatible = "brcm,bcm2836-thermal";
 141         status = "okay";
 142 };