1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
8 compatible = "brcm,bcm2711";
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
37 * Common BCM283x peripherals
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
49 * bringing up secondary cores.
51 local_intc: local_intc@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
53 reg = <0x40000000 0x100>;
56 gicv2: interrupt-controller@40041000 {
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
60 reg = <0x40041000 0x1000>,
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65 IRQ_TYPE_LEVEL_HIGH)>;
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
71 reg = <0x7d5d2000 0xf00>;
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
80 compatible = "brcm,bcm2835-dma";
81 reg = <0x7e007000 0xb00>;
82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "dma0",
106 brcm,dma-channel-mask = <0x07f5>;
109 pm: watchdog@7e100000 {
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
113 reg = <0x7e100000 0x114>,
116 reg-names = "pm", "asb", "rpivid_asb";
117 clocks = <&clocks BCM2835_CLOCK_V3D>,
118 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
119 <&clocks BCM2835_CLOCK_H264>,
120 <&clocks BCM2835_CLOCK_ISP>;
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
127 reg = <0x7e104000 0x28>;
130 uart2: serial@7e201400 {
131 compatible = "arm,pl011", "arm,primecell";
132 reg = <0x7e201400 0x200>;
133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clocks BCM2835_CLOCK_UART>,
135 <&clocks BCM2835_CLOCK_VPU>;
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00241011>;
141 uart3: serial@7e201600 {
142 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x7e201600 0x200>;
144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clocks BCM2835_CLOCK_UART>,
146 <&clocks BCM2835_CLOCK_VPU>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00241011>;
152 uart4: serial@7e201800 {
153 compatible = "arm,pl011", "arm,primecell";
154 reg = <0x7e201800 0x200>;
155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&clocks BCM2835_CLOCK_UART>,
157 <&clocks BCM2835_CLOCK_VPU>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00241011>;
163 uart5: serial@7e201a00 {
164 compatible = "arm,pl011", "arm,primecell";
165 reg = <0x7e201a00 0x200>;
166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&clocks BCM2835_CLOCK_UART>,
168 <&clocks BCM2835_CLOCK_VPU>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00241011>;
175 compatible = "brcm,bcm2835-spi";
176 reg = <0x7e204600 0x0200>;
177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clocks BCM2835_CLOCK_VPU>;
179 #address-cells = <1>;
185 compatible = "brcm,bcm2835-spi";
186 reg = <0x7e204800 0x0200>;
187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clocks BCM2835_CLOCK_VPU>;
189 #address-cells = <1>;
195 compatible = "brcm,bcm2835-spi";
196 reg = <0x7e204a00 0x0200>;
197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clocks BCM2835_CLOCK_VPU>;
199 #address-cells = <1>;
205 compatible = "brcm,bcm2835-spi";
206 reg = <0x7e204c00 0x0200>;
207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clocks BCM2835_CLOCK_VPU>;
209 #address-cells = <1>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
216 reg = <0x7e205600 0x200>;
217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clocks BCM2835_CLOCK_VPU>;
219 #address-cells = <1>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
226 reg = <0x7e205800 0x200>;
227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clocks BCM2835_CLOCK_VPU>;
229 #address-cells = <1>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
236 reg = <0x7e205a00 0x200>;
237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clocks BCM2835_CLOCK_VPU>;
239 #address-cells = <1>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
246 reg = <0x7e205c00 0x200>;
247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clocks BCM2835_CLOCK_VPU>;
249 #address-cells = <1>;
254 pixelvalve0: pixelvalve@7e206000 {
255 compatible = "brcm,bcm2711-pixelvalve0";
256 reg = <0x7e206000 0x100>;
257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
261 pixelvalve1: pixelvalve@7e207000 {
262 compatible = "brcm,bcm2711-pixelvalve1";
263 reg = <0x7e207000 0x100>;
264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
268 pixelvalve2: pixelvalve@7e20a000 {
269 compatible = "brcm,bcm2711-pixelvalve2";
270 reg = <0x7e20a000 0x100>;
271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
276 compatible = "brcm,bcm2835-pwm";
277 reg = <0x7e20c800 0x28>;
278 clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
285 pixelvalve4: pixelvalve@7e216000 {
286 compatible = "brcm,bcm2711-pixelvalve4";
287 reg = <0x7e216000 0x100>;
288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
293 compatible = "brcm,bcm2711-hvs";
294 reg = <0x7e400000 0x8000>;
295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
298 pixelvalve3: pixelvalve@7ec12000 {
299 compatible = "brcm,bcm2711-pixelvalve3";
300 reg = <0x7ec12000 0x100>;
301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
306 compatible = "brcm,bcm2711-vec";
307 reg = <0x7ec13000 0x1000>;
308 clocks = <&clocks BCM2835_CLOCK_VEC>;
309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
313 dvp: clock@7ef00000 {
314 compatible = "brcm,brcm2711-dvp";
315 reg = <0x7ef00000 0x10>;
316 clocks = <&clk_108MHz>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
323 reg = <0x7ef00100 0x30>;
324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-controller;
326 #interrupt-cells = <1>;
329 hdmi0: hdmi@7ef00700 {
330 compatible = "brcm,bcm2711-hdmi0";
331 reg = <0x7ef00700 0x300>,
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
352 interrupts = <0>, <1>, <2>,
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
370 hdmi1: hdmi@7ef05700 {
371 compatible = "brcm,bcm2711-hdmi1";
372 reg = <0x7ef05700 0x300>,
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
394 interrupts = <8>, <7>, <6>,
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
413 * emmc2 has different DMA constraints based on SoC revisions. It was
414 * moved into its own bus, so as for RPi4's firmware to update them.
415 * The firmware will find whether the emmc2bus alias is defined, and if
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
426 emmc2: mmc@7e340000 {
427 compatible = "brcm,bcm2711-emmc2";
428 reg = <0x0 0x7e340000 0x100>;
429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
447 IRQ_TYPE_LEVEL_LOW)>,
448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
449 IRQ_TYPE_LEVEL_LOW)>,
450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
451 IRQ_TYPE_LEVEL_LOW)>,
452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
453 IRQ_TYPE_LEVEL_LOW)>;
454 /* This only applies to the ARMv7 stub */
455 arm,cpu-registers-not-fw-configured;
459 #address-cells = <1>;
461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
463 /* Source for d/i-cache-line-size and d/i-cache-sets
464 * https://developer.arm.com/documentation/100095/0003
465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
466 * Source for d/i-cache-size
467 * https://www.raspberrypi.com/documentation/computers
468 * /processors.html#bcm2711
472 compatible = "arm,cortex-a72";
474 enable-method = "spin-table";
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
477 d-cache-line-size = <64>;
478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
479 i-cache-size = <0xc000>;
480 i-cache-line-size = <64>;
481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
482 next-level-cache = <&l2>;
487 compatible = "arm,cortex-a72";
489 enable-method = "spin-table";
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
492 d-cache-line-size = <64>;
493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
494 i-cache-size = <0xc000>;
495 i-cache-line-size = <64>;
496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
497 next-level-cache = <&l2>;
502 compatible = "arm,cortex-a72";
504 enable-method = "spin-table";
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
507 d-cache-line-size = <64>;
508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
509 i-cache-size = <0xc000>;
510 i-cache-line-size = <64>;
511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
512 next-level-cache = <&l2>;
517 compatible = "arm,cortex-a72";
519 enable-method = "spin-table";
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
522 d-cache-line-size = <64>;
523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
524 i-cache-size = <0xc000>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
527 next-level-cache = <&l2>;
530 /* Source for d/i-cache-line-size and d/i-cache-sets
531 * https://developer.arm.com/documentation/100095/0003
532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
533 * Source for d/i-cache-size
534 * https://www.raspberrypi.com/documentation/computers
535 * /processors.html#bcm2711
538 compatible = "cache";
539 cache-size = <0x100000>;
540 cache-line-size = <64>;
541 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
547 compatible = "simple-bus";
548 #address-cells = <2>;
551 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
552 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
554 pcie0: pcie@7d500000 {
555 compatible = "brcm,bcm2711-pcie";
556 reg = <0x0 0x7d500000 0x9310>;
558 #address-cells = <3>;
559 #interrupt-cells = <1>;
561 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
563 interrupt-names = "pcie", "msi";
564 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
565 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
566 IRQ_TYPE_LEVEL_HIGH>,
567 <0 0 0 2 &gicv2 GIC_SPI 144
568 IRQ_TYPE_LEVEL_HIGH>,
569 <0 0 0 3 &gicv2 GIC_SPI 145
570 IRQ_TYPE_LEVEL_HIGH>,
571 <0 0 0 4 &gicv2 GIC_SPI 146
572 IRQ_TYPE_LEVEL_HIGH>;
574 msi-parent = <&pcie0>;
576 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
579 * The wrapper around the PCIe block has a bug
580 * preventing it from accessing beyond the first 3GB of
583 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
588 genet: ethernet@7d580000 {
589 compatible = "brcm,bcm2711-genet-v5";
590 reg = <0x0 0x7d580000 0x10000>;
591 #address-cells = <0x1>;
593 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
597 genet_mdio: mdio@e14 {
598 compatible = "brcm,genet-mdio-v5";
601 #address-cells = <0x1>;
607 compatible = "brcm,2711-v3d";
608 reg = <0x0 0x7ec00000 0x4000>,
609 <0x0 0x7ec04000 0x4000>;
610 reg-names = "hub", "core0";
612 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
613 resets = <&pm BCM2835_RESET_V3D>;
614 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
620 clock-frequency = <54000000>;
624 compatible = "brcm,bcm2711-cprman";
628 coefficients = <(-487) 410040>;
629 thermal-sensors = <&thermal>;
633 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
637 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
638 compatible = "brcm,bcm2711-dsi1";
642 compatible = "brcm,bcm2711-gpio";
643 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
648 gpio-ranges = <&gpio 0 0 58>;
650 gpclk0_gpio49: gpclk0_gpio49 {
657 gpclk1_gpio50: gpclk1_gpio50 {
664 gpclk2_gpio51: gpclk2_gpio51 {
672 i2c0_gpio46: i2c0_gpio46 {
684 i2c1_gpio46: i2c1_gpio46 {
696 i2c3_gpio2: i2c3_gpio2 {
708 i2c3_gpio4: i2c3_gpio4 {
720 i2c4_gpio6: i2c4_gpio6 {
732 i2c4_gpio8: i2c4_gpio8 {
744 i2c5_gpio10: i2c5_gpio10 {
756 i2c5_gpio12: i2c5_gpio12 {
768 i2c6_gpio0: i2c6_gpio0 {
780 i2c6_gpio22: i2c6_gpio22 {
792 i2c_slave_gpio8: i2c_slave_gpio8 {
802 jtag_gpio48: jtag_gpio48 {
814 mii_gpio28: mii_gpio28 {
823 mii_gpio36: mii_gpio36 {
833 pcm_gpio50: pcm_gpio50 {
843 pwm0_0_gpio12: pwm0_0_gpio12 {
850 pwm0_0_gpio18: pwm0_0_gpio18 {
857 pwm1_0_gpio40: pwm1_0_gpio40 {
864 pwm0_1_gpio13: pwm0_1_gpio13 {
871 pwm0_1_gpio19: pwm0_1_gpio19 {
878 pwm1_1_gpio41: pwm1_1_gpio41 {
885 pwm0_1_gpio45: pwm0_1_gpio45 {
892 pwm0_0_gpio52: pwm0_0_gpio52 {
899 pwm0_1_gpio53: pwm0_1_gpio53 {
907 rgmii_gpio35: rgmii_gpio35 {
917 rgmii_irq_gpio34: rgmii_irq_gpio34 {
923 rgmii_irq_gpio39: rgmii_irq_gpio39 {
929 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
936 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
944 spi0_gpio46: spi0_gpio46 {
953 spi2_gpio46: spi2_gpio46 {
963 spi3_gpio0: spi3_gpio0 {
972 spi4_gpio4: spi4_gpio4 {
981 spi5_gpio12: spi5_gpio12 {
990 spi6_gpio18: spi6_gpio18 {
1000 uart2_gpio0: uart2_gpio0 {
1012 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1024 uart3_gpio4: uart3_gpio4 {
1036 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1048 uart4_gpio8: uart4_gpio8 {
1060 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1072 uart5_gpio12: uart5_gpio12 {
1084 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1099 #address-cells = <2>;
1104 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1105 * that's not good enough for the BCM2711 as some devices can
1106 * only address the lower 1G of memory (ZONE_DMA).
1108 alloc-ranges = <0x0 0x00000000 0x40000000>;
1112 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1117 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1118 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1122 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1130 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1134 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1138 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1142 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1146 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1157 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1169 compatible = "brcm,bcm2711-vec";
1170 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;