arch/arm/boot/dts/bcm2711.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "bcm283x.dtsi"
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/soc/bcm2835-pm.h>
   6
   7 / {
   8         compatible = "brcm,bcm2711";
   9
  10         #address-cells = <2>;
  11         #size-cells = <1>;
  12
  13         interrupt-parent = <&gicv2>;
  14
  15         vc4: gpu {
  16                 compatible = "brcm,bcm2711-vc5";
  17                 status = "disabled";
  18         };
  19
  20         clk_27MHz: clk-27M {
  21                 #clock-cells = <0>;
  22                 compatible = "fixed-clock";
  23                 clock-frequency = <27000000>;
  24                 clock-output-names = "27MHz-clock";
  25         };
  26
  27         clk_108MHz: clk-108M {
  28                 #clock-cells = <0>;
  29                 compatible = "fixed-clock";
  30                 clock-frequency = <108000000>;
  31                 clock-output-names = "108MHz-clock";
  32         };
  33
  34         soc {
  35                 /*
  36                  * Defined ranges:
  37                  *   Common BCM283x peripherals
  38                  *   BCM2711-specific peripherals
  39                  *   ARM-local peripherals
  40                  */
  41                 ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
  42                          <0x7c000000  0x0 0xfc000000  0x02000000>,
  43                          <0x40000000  0x0 0xff800000  0x00800000>;
  44                 /* Emulate a contiguous 30-bit address range for DMA */
  45                 dma-ranges = <0xc0000000  0x0 0x00000000  0x40000000>;
  46
  47                 /*
  48                  * This node is the provider for the enable-method for
  49                  * bringing up secondary cores.
  50                  */
  51                 local_intc: local_intc@40000000 {
  52                         compatible = "brcm,bcm2836-l1-intc";
  53                         reg = <0x40000000 0x100>;
  54                 };
  55
  56                 gicv2: interrupt-controller@40041000 {
  57                         interrupt-controller;
  58                         #interrupt-cells = <3>;
  59                         compatible = "arm,gic-400";
  60                         reg =   <0x40041000 0x1000>,
  61                                 <0x40042000 0x2000>,
  62                                 <0x40044000 0x2000>,
  63                                 <0x40046000 0x2000>;
  64                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  65                                                  IRQ_TYPE_LEVEL_HIGH)>;
  66                 };
  67
  68                 avs_monitor: avs-monitor@7d5d2000 {
  69                         compatible = "brcm,bcm2711-avs-monitor",
  70                                      "syscon", "simple-mfd";
  71                         reg = <0x7d5d2000 0xf00>;
  72
  73                         thermal: thermal {
  74                                 compatible = "brcm,bcm2711-thermal";
  75                                 #thermal-sensor-cells = <0>;
  76                         };
  77                 };
  78
  79                 dma: dma@7e007000 {
  80                         compatible = "brcm,bcm2835-dma";
  81                         reg = <0x7e007000 0xb00>;
  82                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
  86                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  87                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  89                                      /* DMA lite 7 - 10 */
  90                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  91                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  92                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  93                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  94                         interrupt-names = "dma0",
  95                                           "dma1",
  96                                           "dma2",
  97                                           "dma3",
  98                                           "dma4",
  99                                           "dma5",
 100                                           "dma6",
 101                                           "dma7",
 102                                           "dma8",
 103                                           "dma9",
 104                                           "dma10";
 105                         #dma-cells = <1>;
 106                         brcm,dma-channel-mask = <0x07f5>;
 107                 };
 108
 109                 pm: watchdog@7e100000 {
 110                         compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
 111                         #power-domain-cells = <1>;
 112                         #reset-cells = <1>;
 113                         reg = <0x7e100000 0x114>,
 114                               <0x7e00a000 0x24>,
 115                               <0x7ec11000 0x20>;
 116                         clocks = <&clocks BCM2835_CLOCK_V3D>,
 117                                  <&clocks BCM2835_CLOCK_PERI_IMAGE>,
 118                                  <&clocks BCM2835_CLOCK_H264>,
 119                                  <&clocks BCM2835_CLOCK_ISP>;
 120                         clock-names = "v3d", "peri_image", "h264", "isp";
 121                         system-power-controller;
 122                 };
 123
 124                 rng@7e104000 {
 125                         compatible = "brcm,bcm2711-rng200";
 126                         reg = <0x7e104000 0x28>;
 127                 };
 128
 129                 uart2: serial@7e201400 {
 130                         compatible = "arm,pl011", "arm,primecell";
 131                         reg = <0x7e201400 0x200>;
 132                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 133                         clocks = <&clocks BCM2835_CLOCK_UART>,
 134                                  <&clocks BCM2835_CLOCK_VPU>;
 135                         clock-names = "uartclk", "apb_pclk";
 136                         arm,primecell-periphid = <0x00241011>;
 137                         status = "disabled";
 138                 };
 139
 140                 uart3: serial@7e201600 {
 141                         compatible = "arm,pl011", "arm,primecell";
 142                         reg = <0x7e201600 0x200>;
 143                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 144                         clocks = <&clocks BCM2835_CLOCK_UART>,
 145                                  <&clocks BCM2835_CLOCK_VPU>;
 146                         clock-names = "uartclk", "apb_pclk";
 147                         arm,primecell-periphid = <0x00241011>;
 148                         status = "disabled";
 149                 };
 150
 151                 uart4: serial@7e201800 {
 152                         compatible = "arm,pl011", "arm,primecell";
 153                         reg = <0x7e201800 0x200>;
 154                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&clocks BCM2835_CLOCK_UART>,
 156                                  <&clocks BCM2835_CLOCK_VPU>;
 157                         clock-names = "uartclk", "apb_pclk";
 158                         arm,primecell-periphid = <0x00241011>;
 159                         status = "disabled";
 160                 };
 161
 162                 uart5: serial@7e201a00 {
 163                         compatible = "arm,pl011", "arm,primecell";
 164                         reg = <0x7e201a00 0x200>;
 165                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 166                         clocks = <&clocks BCM2835_CLOCK_UART>,
 167                                  <&clocks BCM2835_CLOCK_VPU>;
 168                         clock-names = "uartclk", "apb_pclk";
 169                         arm,primecell-periphid = <0x00241011>;
 170                         status = "disabled";
 171                 };
 172
 173                 spi3: spi@7e204600 {
 174                         compatible = "brcm,bcm2835-spi";
 175                         reg = <0x7e204600 0x0200>;
 176                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                         status = "disabled";
 181                 };
 182
 183                 spi4: spi@7e204800 {
 184                         compatible = "brcm,bcm2835-spi";
 185                         reg = <0x7e204800 0x0200>;
 186                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 187                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         status = "disabled";
 191                 };
 192
 193                 spi5: spi@7e204a00 {
 194                         compatible = "brcm,bcm2835-spi";
 195                         reg = <0x7e204a00 0x0200>;
 196                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         status = "disabled";
 201                 };
 202
 203                 spi6: spi@7e204c00 {
 204                         compatible = "brcm,bcm2835-spi";
 205                         reg = <0x7e204c00 0x0200>;
 206                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         status = "disabled";
 211                 };
 212
 213                 i2c3: i2c@7e205600 {
 214                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 215                         reg = <0x7e205600 0x200>;
 216                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 218                         #address-cells = <1>;
 219                         #size-cells = <0>;
 220                         status = "disabled";
 221                 };
 222
 223                 i2c4: i2c@7e205800 {
 224                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 225                         reg = <0x7e205800 0x200>;
 226                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 227                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         status = "disabled";
 231                 };
 232
 233                 i2c5: i2c@7e205a00 {
 234                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 235                         reg = <0x7e205a00 0x200>;
 236                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241                 };
 242
 243                 i2c6: i2c@7e205c00 {
 244                         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
 245                         reg = <0x7e205c00 0x200>;
 246                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         status = "disabled";
 251                 };
 252
 253                 pixelvalve0: pixelvalve@7e206000 {
 254                         compatible = "brcm,bcm2711-pixelvalve0";
 255                         reg = <0x7e206000 0x100>;
 256                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 257                         status = "disabled";
 258                 };
 259
 260                 pixelvalve1: pixelvalve@7e207000 {
 261                         compatible = "brcm,bcm2711-pixelvalve1";
 262                         reg = <0x7e207000 0x100>;
 263                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 264                         status = "disabled";
 265                 };
 266
 267                 pixelvalve2: pixelvalve@7e20a000 {
 268                         compatible = "brcm,bcm2711-pixelvalve2";
 269                         reg = <0x7e20a000 0x100>;
 270                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 271                         status = "disabled";
 272                 };
 273
 274                 pwm1: pwm@7e20c800 {
 275                         compatible = "brcm,bcm2835-pwm";
 276                         reg = <0x7e20c800 0x28>;
 277                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 278                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 279                         assigned-clock-rates = <10000000>;
 280                         #pwm-cells = <2>;
 281                         status = "disabled";
 282                 };
 283
 284                 pixelvalve4: pixelvalve@7e216000 {
 285                         compatible = "brcm,bcm2711-pixelvalve4";
 286                         reg = <0x7e216000 0x100>;
 287                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 288                         status = "disabled";
 289                 };
 290
 291                 hvs: hvs@7e400000 {
 292                         compatible = "brcm,bcm2711-hvs";
 293                         reg = <0x7e400000 0x8000>;
 294                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 295                 };
 296
 297                 pixelvalve3: pixelvalve@7ec12000 {
 298                         compatible = "brcm,bcm2711-pixelvalve3";
 299                         reg = <0x7ec12000 0x100>;
 300                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 301                         status = "disabled";
 302                 };
 303
 304                 vec: vec@7ec13000 {
 305                         compatible = "brcm,bcm2711-vec";
 306                         reg = <0x7ec13000 0x1000>;
 307                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 308                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 309                         status = "disabled";
 310                 };
 311
 312                 dvp: clock@7ef00000 {
 313                         compatible = "brcm,brcm2711-dvp";
 314                         reg = <0x7ef00000 0x10>;
 315                         clocks = <&clk_108MHz>;
 316                         #clock-cells = <1>;
 317                         #reset-cells = <1>;
 318                 };
 319
 320                 aon_intr: interrupt-controller@7ef00100 {
 321                         compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
 322                         reg = <0x7ef00100 0x30>;
 323                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 324                         interrupt-controller;
 325                         #interrupt-cells = <1>;
 326                 };
 327
 328                 hdmi0: hdmi@7ef00700 {
 329                         compatible = "brcm,bcm2711-hdmi0";
 330                         reg = <0x7ef00700 0x300>,
 331                               <0x7ef00300 0x200>,
 332                               <0x7ef00f00 0x80>,
 333                               <0x7ef00f80 0x80>,
 334                               <0x7ef01b00 0x200>,
 335                               <0x7ef01f00 0x400>,
 336                               <0x7ef00200 0x80>,
 337                               <0x7ef04300 0x100>,
 338                               <0x7ef20000 0x100>;
 339                         reg-names = "hdmi",
 340                                     "dvp",
 341                                     "phy",
 342                                     "rm",
 343                                     "packet",
 344                                     "metadata",
 345                                     "csc",
 346                                     "cec",
 347                                     "hd";
 348                         clock-names = "hdmi", "bvb", "audio", "cec";
 349                         resets = <&dvp 0>;
 350                         interrupt-parent = <&aon_intr>;
 351                         interrupts = <0>, <1>, <2>,
 352                                      <3>, <4>, <5>;
 353                         interrupt-names = "cec-tx", "cec-rx", "cec-low",
 354                                           "wakeup", "hpd-connected", "hpd-removed";
 355                         ddc = <&ddc0>;
 356                         dmas = <&dma 10>;
 357                         dma-names = "audio-rx";
 358                         status = "disabled";
 359                 };
 360
 361                 ddc0: i2c@7ef04500 {
 362                         compatible = "brcm,bcm2711-hdmi-i2c";
 363                         reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
 364                         reg-names = "bsc", "auto-i2c";
 365                         clock-frequency = <97500>;
 366                         status = "disabled";
 367                 };
 368
 369                 hdmi1: hdmi@7ef05700 {
 370                         compatible = "brcm,bcm2711-hdmi1";
 371                         reg = <0x7ef05700 0x300>,
 372                               <0x7ef05300 0x200>,
 373                               <0x7ef05f00 0x80>,
 374                               <0x7ef05f80 0x80>,
 375                               <0x7ef06b00 0x200>,
 376                               <0x7ef06f00 0x400>,
 377                               <0x7ef00280 0x80>,
 378                               <0x7ef09300 0x100>,
 379                               <0x7ef20000 0x100>;
 380                         reg-names = "hdmi",
 381                                     "dvp",
 382                                     "phy",
 383                                     "rm",
 384                                     "packet",
 385                                     "metadata",
 386                                     "csc",
 387                                     "cec",
 388                                     "hd";
 389                         ddc = <&ddc1>;
 390                         clock-names = "hdmi", "bvb", "audio", "cec";
 391                         resets = <&dvp 1>;
 392                         interrupt-parent = <&aon_intr>;
 393                         interrupts = <8>, <7>, <6>,
 394                                      <9>, <10>, <11>;
 395                         interrupt-names = "cec-tx", "cec-rx", "cec-low",
 396                                           "wakeup", "hpd-connected", "hpd-removed";
 397                         dmas = <&dma 17>;
 398                         dma-names = "audio-rx";
 399                         status = "disabled";
 400                 };
 401
 402                 ddc1: i2c@7ef09500 {
 403                         compatible = "brcm,bcm2711-hdmi-i2c";
 404                         reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
 405                         reg-names = "bsc", "auto-i2c";
 406                         clock-frequency = <97500>;
 407                         status = "disabled";
 408                 };
 409         };
 410
 411         /*
 412          * emmc2 has different DMA constraints based on SoC revisions. It was
 413          * moved into its own bus, so as for RPi4's firmware to update them.
 414          * The firmware will find whether the emmc2bus alias is defined, and if
 415          * so, it'll edit the dma-ranges property below accordingly.
 416          */
 417         emmc2bus: emmc2bus {
 418                 compatible = "simple-bus";
 419                 #address-cells = <2>;
 420                 #size-cells = <1>;
 421
 422                 ranges = <0x0 0x7e000000  0x0 0xfe000000  0x01800000>;
 423                 dma-ranges = <0x0 0xc0000000  0x0 0x00000000  0x40000000>;
 424
 425                 emmc2: mmc@7e340000 {
 426                         compatible = "brcm,bcm2711-emmc2";
 427                         reg = <0x0 0x7e340000 0x100>;
 428                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&clocks BCM2711_CLOCK_EMMC2>;
 430                         status = "disabled";
 431                 };
 432         };
 433
 434         arm-pmu {
 435                 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
 436                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 437                         <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 438                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 439                         <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 440                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 441         };
 442
 443         timer {
 444                 compatible = "arm,armv8-timer";
 445                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 446                                           IRQ_TYPE_LEVEL_LOW)>,
 447                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 448                                           IRQ_TYPE_LEVEL_LOW)>,
 449                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 450                                           IRQ_TYPE_LEVEL_LOW)>,
 451                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 452                                           IRQ_TYPE_LEVEL_LOW)>;
 453                 /* This only applies to the ARMv7 stub */
 454                 arm,cpu-registers-not-fw-configured;
 455         };
 456
 457         cpus: cpus {
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 461
 462                 cpu0: cpu@0 {
 463                         device_type = "cpu";
 464                         compatible = "arm,cortex-a72";
 465                         reg = <0>;
 466                         enable-method = "spin-table";
 467                         cpu-release-addr = <0x0 0x000000d8>;
 468                 };
 469
 470                 cpu1: cpu@1 {
 471                         device_type = "cpu";
 472                         compatible = "arm,cortex-a72";
 473                         reg = <1>;
 474                         enable-method = "spin-table";
 475                         cpu-release-addr = <0x0 0x000000e0>;
 476                 };
 477
 478                 cpu2: cpu@2 {
 479                         device_type = "cpu";
 480                         compatible = "arm,cortex-a72";
 481                         reg = <2>;
 482                         enable-method = "spin-table";
 483                         cpu-release-addr = <0x0 0x000000e8>;
 484                 };
 485
 486                 cpu3: cpu@3 {
 487                         device_type = "cpu";
 488                         compatible = "arm,cortex-a72";
 489                         reg = <3>;
 490                         enable-method = "spin-table";
 491                         cpu-release-addr = <0x0 0x000000f0>;
 492                 };
 493         };
 494
 495         scb {
 496                 compatible = "simple-bus";
 497                 #address-cells = <2>;
 498                 #size-cells = <1>;
 499
 500                 ranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,
 501                          <0x6 0x00000000  0x6 0x00000000  0x40000000>;
 502
 503                 pcie0: pcie@7d500000 {
 504                         compatible = "brcm,bcm2711-pcie";
 505                         reg = <0x0 0x7d500000 0x9310>;
 506                         device_type = "pci";
 507                         #address-cells = <3>;
 508                         #interrupt-cells = <1>;
 509                         #size-cells = <2>;
 510                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 511                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 512                         interrupt-names = "pcie", "msi";
 513                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 514                         interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
 515                                                         IRQ_TYPE_LEVEL_HIGH>,
 516                                         <0 0 0 2 &gicv2 GIC_SPI 144
 517                                                         IRQ_TYPE_LEVEL_HIGH>,
 518                                         <0 0 0 3 &gicv2 GIC_SPI 145
 519                                                         IRQ_TYPE_LEVEL_HIGH>,
 520                                         <0 0 0 4 &gicv2 GIC_SPI 146
 521                                                         IRQ_TYPE_LEVEL_HIGH>;
 522                         msi-controller;
 523                         msi-parent = <&pcie0>;
 524
 525                         ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
 526                                   0x0 0x04000000>;
 527                         /*
 528                          * The wrapper around the PCIe block has a bug
 529                          * preventing it from accessing beyond the first 3GB of
 530                          * memory.
 531                          */
 532                         dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
 533                                       0x0 0xc0000000>;
 534                         brcm,enable-ssc;
 535                 };
 536
 537                 genet: ethernet@7d580000 {
 538                         compatible = "brcm,bcm2711-genet-v5";
 539                         reg = <0x0 0x7d580000 0x10000>;
 540                         #address-cells = <0x1>;
 541                         #size-cells = <0x1>;
 542                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 544                         status = "disabled";
 545
 546                         genet_mdio: mdio@e14 {
 547                                 compatible = "brcm,genet-mdio-v5";
 548                                 reg = <0xe14 0x8>;
 549                                 reg-names = "mdio";
 550                                 #address-cells = <0x1>;
 551                                 #size-cells = <0x0>;
 552                         };
 553                 };
 554         };
 555 };
 556
 557 &clk_osc {
 558         clock-frequency = <54000000>;
 559 };
 560
 561 &clocks {
 562         compatible = "brcm,bcm2711-cprman";
 563 };
 564
 565 &cpu_thermal {
 566         coefficients = <(-487) 410040>;
 567         thermal-sensors = <&thermal>;
 568 };
 569
 570 &dsi0 {
 571         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 572 };
 573
 574 &dsi1 {
 575         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 576         compatible = "brcm,bcm2711-dsi1";
 577 };
 578
 579 &gpio {
 580         compatible = "brcm,bcm2711-gpio";
 581         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 582                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 583                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 584                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 585
 586         gpio-ranges = <&gpio 0 0 58>;
 587
 588         gpclk0_gpio49: gpclk0_gpio49 {
 589                 pin-gpclk {
 590                         pins = "gpio49";
 591                         function = "alt1";
 592                         bias-disable;
 593                 };
 594         };
 595         gpclk1_gpio50: gpclk1_gpio50 {
 596                 pin-gpclk {
 597                         pins = "gpio50";
 598                         function = "alt1";
 599                         bias-disable;
 600                 };
 601         };
 602         gpclk2_gpio51: gpclk2_gpio51 {
 603                 pin-gpclk {
 604                         pins = "gpio51";
 605                         function = "alt1";
 606                         bias-disable;
 607                 };
 608         };
 609
 610         i2c0_gpio46: i2c0_gpio46 {
 611                 pin-sda {
 612                         function = "alt0";
 613                         pins = "gpio46";
 614                         bias-pull-up;
 615                 };
 616                 pin-scl {
 617                         function = "alt0";
 618                         pins = "gpio47";
 619                         bias-disable;
 620                 };
 621         };
 622         i2c1_gpio46: i2c1_gpio46 {
 623                 pin-sda {
 624                         function = "alt1";
 625                         pins = "gpio46";
 626                         bias-pull-up;
 627                 };
 628                 pin-scl {
 629                         function = "alt1";
 630                         pins = "gpio47";
 631                         bias-disable;
 632                 };
 633         };
 634         i2c3_gpio2: i2c3_gpio2 {
 635                 pin-sda {
 636                         function = "alt5";
 637                         pins = "gpio2";
 638                         bias-pull-up;
 639                 };
 640                 pin-scl {
 641                         function = "alt5";
 642                         pins = "gpio3";
 643                         bias-disable;
 644                 };
 645         };
 646         i2c3_gpio4: i2c3_gpio4 {
 647                 pin-sda {
 648                         function = "alt5";
 649                         pins = "gpio4";
 650                         bias-pull-up;
 651                 };
 652                 pin-scl {
 653                         function = "alt5";
 654                         pins = "gpio5";
 655                         bias-disable;
 656                 };
 657         };
 658         i2c4_gpio6: i2c4_gpio6 {
 659                 pin-sda {
 660                         function = "alt5";
 661                         pins = "gpio6";
 662                         bias-pull-up;
 663                 };
 664                 pin-scl {
 665                         function = "alt5";
 666                         pins = "gpio7";
 667                         bias-disable;
 668                 };
 669         };
 670         i2c4_gpio8: i2c4_gpio8 {
 671                 pin-sda {
 672                         function = "alt5";
 673                         pins = "gpio8";
 674                         bias-pull-up;
 675                 };
 676                 pin-scl {
 677                         function = "alt5";
 678                         pins = "gpio9";
 679                         bias-disable;
 680                 };
 681         };
 682         i2c5_gpio10: i2c5_gpio10 {
 683                 pin-sda {
 684                         function = "alt5";
 685                         pins = "gpio10";
 686                         bias-pull-up;
 687                 };
 688                 pin-scl {
 689                         function = "alt5";
 690                         pins = "gpio11";
 691                         bias-disable;
 692                 };
 693         };
 694         i2c5_gpio12: i2c5_gpio12 {
 695                 pin-sda {
 696                         function = "alt5";
 697                         pins = "gpio12";
 698                         bias-pull-up;
 699                 };
 700                 pin-scl {
 701                         function = "alt5";
 702                         pins = "gpio13";
 703                         bias-disable;
 704                 };
 705         };
 706         i2c6_gpio0: i2c6_gpio0 {
 707                 pin-sda {
 708                         function = "alt5";
 709                         pins = "gpio0";
 710                         bias-pull-up;
 711                 };
 712                 pin-scl {
 713                         function = "alt5";
 714                         pins = "gpio1";
 715                         bias-disable;
 716                 };
 717         };
 718         i2c6_gpio22: i2c6_gpio22 {
 719                 pin-sda {
 720                         function = "alt5";
 721                         pins = "gpio22";
 722                         bias-pull-up;
 723                 };
 724                 pin-scl {
 725                         function = "alt5";
 726                         pins = "gpio23";
 727                         bias-disable;
 728                 };
 729         };
 730         i2c_slave_gpio8: i2c_slave_gpio8 {
 731                 pins-i2c-slave {
 732                         pins = "gpio8",
 733                                "gpio9",
 734                                "gpio10",
 735                                "gpio11";
 736                         function = "alt3";
 737                 };
 738         };
 739
 740         jtag_gpio48: jtag_gpio48 {
 741                 pins-jtag {
 742                         pins = "gpio48",
 743                                "gpio49",
 744                                "gpio50",
 745                                "gpio51",
 746                                "gpio52",
 747                                "gpio53";
 748                         function = "alt4";
 749                 };
 750         };
 751
 752         mii_gpio28: mii_gpio28 {
 753                 pins-mii {
 754                         pins = "gpio28",
 755                                "gpio29",
 756                                "gpio30",
 757                                "gpio31";
 758                         function = "alt4";
 759                 };
 760         };
 761         mii_gpio36: mii_gpio36 {
 762                 pins-mii {
 763                         pins = "gpio36",
 764                                "gpio37",
 765                                "gpio38",
 766                                "gpio39";
 767                         function = "alt5";
 768                 };
 769         };
 770
 771         pcm_gpio50: pcm_gpio50 {
 772                 pins-pcm {
 773                         pins = "gpio50",
 774                                "gpio51",
 775                                "gpio52",
 776                                "gpio53";
 777                         function = "alt2";
 778                 };
 779         };
 780
 781         pwm0_0_gpio12: pwm0_0_gpio12 {
 782                 pin-pwm {
 783                         pins = "gpio12";
 784                         function = "alt0";
 785                         bias-disable;
 786                 };
 787         };
 788         pwm0_0_gpio18: pwm0_0_gpio18 {
 789                 pin-pwm {
 790                         pins = "gpio18";
 791                         function = "alt5";
 792                         bias-disable;
 793                 };
 794         };
 795         pwm1_0_gpio40: pwm1_0_gpio40 {
 796                 pin-pwm {
 797                         pins = "gpio40";
 798                         function = "alt0";
 799                         bias-disable;
 800                 };
 801         };
 802         pwm0_1_gpio13: pwm0_1_gpio13 {
 803                 pin-pwm {
 804                         pins = "gpio13";
 805                         function = "alt0";
 806                         bias-disable;
 807                 };
 808         };
 809         pwm0_1_gpio19: pwm0_1_gpio19 {
 810                 pin-pwm {
 811                         pins = "gpio19";
 812                         function = "alt5";
 813                         bias-disable;
 814                 };
 815         };
 816         pwm1_1_gpio41: pwm1_1_gpio41 {
 817                 pin-pwm {
 818                         pins = "gpio41";
 819                         function = "alt0";
 820                         bias-disable;
 821                 };
 822         };
 823         pwm0_1_gpio45: pwm0_1_gpio45 {
 824                 pin-pwm {
 825                         pins = "gpio45";
 826                         function = "alt0";
 827                         bias-disable;
 828                 };
 829         };
 830         pwm0_0_gpio52: pwm0_0_gpio52 {
 831                 pin-pwm {
 832                         pins = "gpio52";
 833                         function = "alt1";
 834                         bias-disable;
 835                 };
 836         };
 837         pwm0_1_gpio53: pwm0_1_gpio53 {
 838                 pin-pwm {
 839                         pins = "gpio53";
 840                         function = "alt1";
 841                         bias-disable;
 842                 };
 843         };
 844
 845         rgmii_gpio35: rgmii_gpio35 {
 846                 pin-start-stop {
 847                         pins = "gpio35";
 848                         function = "alt4";
 849                 };
 850                 pin-rx-ok {
 851                         pins = "gpio36";
 852                         function = "alt4";
 853                 };
 854         };
 855         rgmii_irq_gpio34: rgmii_irq_gpio34 {
 856                 pin-irq {
 857                         pins = "gpio34";
 858                         function = "alt5";
 859                 };
 860         };
 861         rgmii_irq_gpio39: rgmii_irq_gpio39 {
 862                 pin-irq {
 863                         pins = "gpio39";
 864                         function = "alt4";
 865                 };
 866         };
 867         rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
 868                 pins-mdio {
 869                         pins = "gpio28",
 870                                "gpio29";
 871                         function = "alt5";
 872                 };
 873         };
 874         rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
 875                 pins-mdio {
 876                         pins = "gpio37",
 877                                "gpio38";
 878                         function = "alt4";
 879                 };
 880         };
 881
 882         spi0_gpio46: spi0_gpio46 {
 883                 pins-spi {
 884                         pins = "gpio46",
 885                                "gpio47",
 886                                "gpio48",
 887                                "gpio49";
 888                         function = "alt2";
 889                 };
 890         };
 891         spi2_gpio46: spi2_gpio46 {
 892                 pins-spi {
 893                         pins = "gpio46",
 894                                "gpio47",
 895                                "gpio48",
 896                                "gpio49",
 897                                "gpio50";
 898                         function = "alt5";
 899                 };
 900         };
 901         spi3_gpio0: spi3_gpio0 {
 902                 pins-spi {
 903                         pins = "gpio0",
 904                                "gpio1",
 905                                "gpio2",
 906                                "gpio3";
 907                         function = "alt3";
 908                 };
 909         };
 910         spi4_gpio4: spi4_gpio4 {
 911                 pins-spi {
 912                         pins = "gpio4",
 913                                "gpio5",
 914                                "gpio6",
 915                                "gpio7";
 916                         function = "alt3";
 917                 };
 918         };
 919         spi5_gpio12: spi5_gpio12 {
 920                 pins-spi {
 921                         pins = "gpio12",
 922                                "gpio13",
 923                                "gpio14",
 924                                "gpio15";
 925                         function = "alt3";
 926                 };
 927         };
 928         spi6_gpio18: spi6_gpio18 {
 929                 pins-spi {
 930                         pins = "gpio18",
 931                                "gpio19",
 932                                "gpio20",
 933                                "gpio21";
 934                         function = "alt3";
 935                 };
 936         };
 937
 938         uart2_gpio0: uart2_gpio0 {
 939                 pin-tx {
 940                         pins = "gpio0";
 941                         function = "alt4";
 942                         bias-disable;
 943                 };
 944                 pin-rx {
 945                         pins = "gpio1";
 946                         function = "alt4";
 947                         bias-pull-up;
 948                 };
 949         };
 950         uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
 951                 pin-cts {
 952                         pins = "gpio2";
 953                         function = "alt4";
 954                         bias-pull-up;
 955                 };
 956                 pin-rts {
 957                         pins = "gpio3";
 958                         function = "alt4";
 959                         bias-disable;
 960                 };
 961         };
 962         uart3_gpio4: uart3_gpio4 {
 963                 pin-tx {
 964                         pins = "gpio4";
 965                         function = "alt4";
 966                         bias-disable;
 967                 };
 968                 pin-rx {
 969                         pins = "gpio5";
 970                         function = "alt4";
 971                         bias-pull-up;
 972                 };
 973         };
 974         uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
 975                 pin-cts {
 976                         pins = "gpio6";
 977                         function = "alt4";
 978                         bias-pull-up;
 979                 };
 980                 pin-rts {
 981                         pins = "gpio7";
 982                         function = "alt4";
 983                         bias-disable;
 984                 };
 985         };
 986         uart4_gpio8: uart4_gpio8 {
 987                 pin-tx {
 988                         pins = "gpio8";
 989                         function = "alt4";
 990                         bias-disable;
 991                 };
 992                 pin-rx {
 993                         pins = "gpio9";
 994                         function = "alt4";
 995                         bias-pull-up;
 996                 };
 997         };
 998         uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
 999                 pin-cts {
1000                         pins = "gpio10";
1001                         function = "alt4";
1002                         bias-pull-up;
1003                 };
1004                 pin-rts {
1005                         pins = "gpio11";
1006                         function = "alt4";
1007                         bias-disable;
1008                 };
1009         };
1010         uart5_gpio12: uart5_gpio12 {
1011                 pin-tx {
1012                         pins = "gpio12";
1013                         function = "alt4";
1014                         bias-disable;
1015                 };
1016                 pin-rx {
1017                         pins = "gpio13";
1018                         function = "alt4";
1019                         bias-pull-up;
1020                 };
1021         };
1022         uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1023                 pin-cts {
1024                         pins = "gpio14";
1025                         function = "alt4";
1026                         bias-pull-up;
1027                 };
1028                 pin-rts {
1029                         pins = "gpio15";
1030                         function = "alt4";
1031                         bias-disable;
1032                 };
1033         };
1034 };
1035
1036 &rmem {
1037         #address-cells = <2>;
1038 };
1039
1040 &cma {
1041         /*
1042          * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1043          * that's not good enough for the BCM2711 as some devices can
1044          * only address the lower 1G of memory (ZONE_DMA).
1045          */
1046         alloc-ranges = <0x0 0x00000000 0x40000000>;
1047 };
1048
1049 &i2c0 {
1050         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1051         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1052 };
1053
1054 &i2c1 {
1055         compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1056         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1057 };
1058
1059 &mailbox {
1060         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1061 };
1062
1063 &sdhci {
1064         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1065 };
1066
1067 &sdhost {
1068         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1069 };
1070
1071 &spi {
1072         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1073 };
1074
1075 &spi1 {
1076         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1077 };
1078
1079 &spi2 {
1080         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1081 };
1082
1083 &system_timer {
1084         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1085                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1086                      <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1087                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1088 };
1089
1090 &txp {
1091         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1092 };
1093
1094 &uart0 {
1095         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1096 };
1097
1098 &uart1 {
1099         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1100 };
1101
1102 &usb {
1103         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1104 };
1105
1106 &vec {
1107         compatible = "brcm,bcm2711-vec";
1108         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1109 };