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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff0fec>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
78 a9pll: arm_clk@00000 {
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_EDGE_RISING)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011ba08>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0x20000 0x1000>;
198 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&iprocslow>;
208 clock-names = "apb_pclk";
212 amac0: ethernet@22000 {
213 compatible = "brcm,nsp-amac";
214 reg = <0x022000 0x1000>,
216 reg-names = "amac_base", "idm_base";
217 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
221 amac1: ethernet@23000 {
222 compatible = "brcm,nsp-amac";
223 reg = <0x023000 0x1000>,
225 reg-names = "amac_base", "idm_base";
226 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
231 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
232 reg = <0x026000 0x600>,
235 reg-names = "nand", "iproc-idm", "iproc-ext";
236 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
238 #address-cells = <1>;
245 compatible = "brcm,iproc-pwm";
246 reg = <0x31000 0x28>;
253 compatible = "brcm,bcm-nsp-rng";
254 reg = <0x33000 0x14>;
257 ccbtimer0: timer@34000 {
258 compatible = "arm,sp804";
259 reg = <0x34000 0x1000>;
260 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&iprocslow>;
263 clock-names = "apb_pclk";
266 ccbtimer1: timer@35000 {
267 compatible = "arm,sp804";
268 reg = <0x35000 0x1000>;
269 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&iprocslow>;
272 clock-names = "apb_pclk";
276 compatible = "brcm,nsp-srab";
277 reg = <0x36000 0x1000>;
278 #address-cells = <1>;
283 /* ports are defined in board DTS */
287 compatible = "brcm,iproc-i2c";
288 reg = <0x38000 0x50>;
289 #address-cells = <1>;
291 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
292 clock-frequency = <100000>;
296 compatible = "arm,sp805", "arm,primecell";
297 reg = <0x39000 0x1000>;
298 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&iprocslow>, <&iprocslow>;
300 clock-names = "wdogclk", "apb_pclk";
303 lcpll0: lcpll0@3f100 {
305 compatible = "brcm,nsp-lcpll0";
306 reg = <0x3f100 0x14>;
308 clock-output-names = "lcpll0", "pcie_phy", "sdio",
312 genpll: genpll@3f140 {
314 compatible = "brcm,nsp-genpll";
315 reg = <0x3f140 0x24>;
317 clock-output-names = "genpll", "phy", "ethernetclk",
318 "usbclk", "iprocfast", "sata1",
322 pinctrl: pinctrl@3f1c0 {
323 compatible = "brcm,nsp-pinmux";
324 reg = <0x3f1c0 0x04>,
329 sata_phy: sata_phy@40100 {
330 compatible = "brcm,iproc-nsp-sata-phy";
331 reg = <0x40100 0x340>;
333 #address-cells = <1>;
336 sata_phy0: sata-phy@0 {
342 sata_phy1: sata-phy@1 {
350 compatible = "brcm,bcm-nsp-ahci";
351 reg-names = "ahci", "top-ctrl";
352 reg = <0x41000 0x1000>, <0x40020 0x1c>;
353 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
361 phy-names = "sata-phy";
367 phy-names = "sata-phy";
372 pcie0: pcie@18012000 {
373 compatible = "brcm,iproc-pcie";
374 reg = <0x18012000 0x1000>;
376 #interrupt-cells = <1>;
377 interrupt-map-mask = <0 0 0 0>;
378 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
380 linux,pci-domain = <0>;
382 bus-range = <0x00 0xff>;
384 #address-cells = <3>;
388 /* Note: The HW does not support I/O resources. So,
389 * only the memory resource range is being specified.
391 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
395 msi-parent = <&msi0>;
397 compatible = "brcm,iproc-msi";
399 interrupt-parent = <&gic>;
400 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
408 pcie1: pcie@18013000 {
409 compatible = "brcm,iproc-pcie";
410 reg = <0x18013000 0x1000>;
412 #interrupt-cells = <1>;
413 interrupt-map-mask = <0 0 0 0>;
414 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
416 linux,pci-domain = <1>;
418 bus-range = <0x00 0xff>;
420 #address-cells = <3>;
424 /* Note: The HW does not support I/O resources. So,
425 * only the memory resource range is being specified.
427 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
431 msi-parent = <&msi1>;
433 compatible = "brcm,iproc-msi";
435 interrupt-parent = <&gic>;
436 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
444 pcie2: pcie@18014000 {
445 compatible = "brcm,iproc-pcie";
446 reg = <0x18014000 0x1000>;
448 #interrupt-cells = <1>;
449 interrupt-map-mask = <0 0 0 0>;
450 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
452 linux,pci-domain = <2>;
454 bus-range = <0x00 0xff>;
456 #address-cells = <3>;
460 /* Note: The HW does not support I/O resources. So,
461 * only the memory resource range is being specified.
463 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
467 msi-parent = <&msi2>;
469 compatible = "brcm,iproc-msi";
471 interrupt-parent = <&gic>;
472 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;