1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright 2019 IBM Corp.
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/ast2600-clock.h>
9 compatible = "aspeed,ast2600";
12 interrupt-parent = <&gic>;
22 enable-method = "aspeed,ast2600-smp";
25 compatible = "arm,cortex-a7";
31 compatible = "arm,cortex-a7";
38 compatible = "arm,armv7-timer";
39 interrupt-parent = <&gic>;
40 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
41 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
44 clocks = <&syscon ASPEED_CLK_HPLL>;
45 arm,cpu-registers-not-fw-configured;
49 compatible = "simple-bus";
55 gic: interrupt-controller@40461000 {
56 compatible = "arm,cortex-a7-gic";
57 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
58 #interrupt-cells = <3>;
60 interrupt-parent = <&gic>;
61 reg = <0x40461000 0x1000>,
67 mdio0: mdio@1e650000 {
68 compatible = "aspeed,ast2600-mdio";
69 reg = <0x1e650000 0x8>;
75 mdio1: mdio@1e650008 {
76 compatible = "aspeed,ast2600-mdio";
77 reg = <0x1e650008 0x8>;
83 mdio2: mdio@1e650010 {
84 compatible = "aspeed,ast2600-mdio";
85 reg = <0x1e650010 0x8>;
91 mdio3: mdio@1e650018 {
92 compatible = "aspeed,ast2600-mdio";
93 reg = <0x1e650018 0x8>;
99 mac0: ftgmac@1e660000 {
100 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
101 reg = <0x1e660000 0x180>;
102 #address-cells = <1>;
104 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
109 mac1: ftgmac@1e680000 {
110 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
111 reg = <0x1e680000 0x180>;
112 #address-cells = <1>;
114 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
119 mac2: ftgmac@1e670000 {
120 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
121 reg = <0x1e670000 0x180>;
122 #address-cells = <1>;
124 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
129 mac3: ftgmac@1e690000 {
130 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
131 reg = <0x1e690000 0x180>;
132 #address-cells = <1>;
134 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
140 compatible = "simple-bus";
141 #address-cells = <1>;
145 syscon: syscon@1e6e2000 {
146 compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
147 reg = <0x1e6e2000 0x1000>;
148 ranges = <0 0x1e6e2000 0x1000>;
149 #address-cells = <1>;
155 compatible = "aspeed,ast2600-pinctrl";
159 compatible = "aspeed,ast2600-smpmem";
164 rng: hwrng@1e6e2524 {
165 compatible = "timeriomem_rng";
166 reg = <0x1e6e2524 0x4>;
172 compatible = "aspeed,ast2600-rtc";
173 reg = <0x1e781000 0x18>;
174 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
178 uart5: serial@1e784000 {
179 compatible = "ns16550a";
180 reg = <0x1e784000 0x1000>;
182 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
187 wdt1: watchdog@1e785000 {
188 compatible = "aspeed,ast2600-wdt";
189 reg = <0x1e785000 0x40>;
192 wdt2: watchdog@1e785040 {
193 compatible = "aspeed,ast2600-wdt";
194 reg = <0x1e785040 0x40>;
198 wdt3: watchdog@1e785080 {
199 compatible = "aspeed,ast2600-wdt";
200 reg = <0x1e785080 0x40>;
204 wdt4: watchdog@1e7850C0 {
205 compatible = "aspeed,ast2600-wdt";
206 reg = <0x1e7850C0 0x40>;
211 compatible = "aspeed,ast2600-sd-controller";
212 reg = <0x1e740000 0x100>;
213 #address-cells = <1>;
215 ranges = <0 0x1e740000 0x10000>;
216 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
219 sdhci0: sdhci@1e740100 {
220 compatible = "aspeed,ast2600-sdhci", "sdhci";
222 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&syscon ASPEED_CLK_SDIO>;
228 sdhci1: sdhci@1e740200 {
229 compatible = "aspeed,ast2600-sdhci", "sdhci";
231 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&syscon ASPEED_CLK_SDIO>;
239 compatible = "aspeed,ast2600-sd-controller";
240 reg = <0x1e750000 0x100>;
241 #address-cells = <1>;
243 ranges = <0 0x1e750000 0x10000>;
244 clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
248 compatible = "aspeed,ast2600-sdhci";
251 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&syscon ASPEED_CLK_EMMC>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_emmc_default>;
261 #include "aspeed-g6-pinctrl.dtsi"