1 // SPDX-License-Identifier: GPL-2.0+
2 #include <dt-bindings/clock/aspeed-clock.h>
6 compatible = "aspeed,ast2400";
9 interrupt-parent = <&vic>;
39 compatible = "arm,arm926ej-s";
46 device_type = "memory";
51 compatible = "simple-bus";
56 fmc: flash-controller@1e620000 {
57 reg = < 0x1e620000 0x94
58 0x20000000 0x10000000 >;
61 compatible = "aspeed,ast2400-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
67 compatible = "jedec,spi-nor";
72 spi: flash-controller@1e630000 {
73 reg = < 0x1e630000 0x18
74 0x30000000 0x10000000 >;
77 compatible = "aspeed,ast2400-spi";
78 clocks = <&syscon ASPEED_CLK_AHB>;
82 compatible = "jedec,spi-nor";
87 vic: interrupt-controller@1e6c0080 {
88 compatible = "aspeed,ast2400-vic";
90 #interrupt-cells = <1>;
91 valid-sources = <0xffffffff 0x0007ffff>;
92 reg = <0x1e6c0080 0x80>;
95 cvic: copro-interrupt-controller@1e6c2000 {
96 compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
97 valid-sources = <0x7fffffff>;
98 reg = <0x1e6c2000 0x80>;
101 mac0: ethernet@1e660000 {
102 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
103 reg = <0x1e660000 0x180>;
105 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
109 mac1: ethernet@1e680000 {
110 compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
111 reg = <0x1e680000 0x180>;
113 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
117 ehci0: usb@1e6a1000 {
118 compatible = "aspeed,ast2400-ehci", "generic-ehci";
119 reg = <0x1e6a1000 0x100>;
121 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_usb2h_default>;
128 compatible = "aspeed,ast2400-uhci", "generic-uhci";
129 reg = <0x1e6b0000 0x100>;
132 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
135 * No default pinmux, it will follow EHCI, use an explicit pinmux
136 * override if you don't enable EHCI
140 vhub: usb-vhub@1e6a0000 {
141 compatible = "aspeed,ast2400-usb-vhub";
142 reg = <0x1e6a0000 0x300>;
144 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usb2d_default>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
156 syscon: syscon@1e6e2000 {
157 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
158 reg = <0x1e6e2000 0x1a8>;
159 #address-cells = <1>;
165 compatible = "aspeed,g4-pinctrl";
170 rng: hwrng@1e6e2078 {
171 compatible = "timeriomem_rng";
172 reg = <0x1e6e2078 0x4>;
178 compatible = "aspeed,ast2400-adc";
179 reg = <0x1e6e9000 0xb0>;
180 clocks = <&syscon ASPEED_CLK_APB>;
181 resets = <&syscon ASPEED_RESET_ADC>;
182 #io-channel-cells = <1>;
186 sram: sram@1e720000 {
187 compatible = "mmio-sram";
188 reg = <0x1e720000 0x8000>; // 32K
191 gpio: gpio@1e780000 {
194 compatible = "aspeed,ast2400-gpio";
195 reg = <0x1e780000 0x1000>;
197 gpio-ranges = <&pinctrl 0 0 220>;
198 clocks = <&syscon ASPEED_CLK_APB>;
199 interrupt-controller;
202 timer: timer@1e782000 {
203 /* This timer is a Faraday FTTMR010 derivative */
204 compatible = "aspeed,ast2400-timer";
205 reg = <0x1e782000 0x90>;
206 interrupts = <16 17 18 35 36 37 38 39>;
207 clocks = <&syscon ASPEED_CLK_APB>;
208 clock-names = "PCLK";
211 uart1: serial@1e783000 {
212 compatible = "ns16550a";
213 reg = <0x1e783000 0x20>;
216 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
217 resets = <&lpc_reset 4>;
222 uart5: serial@1e784000 {
223 compatible = "ns16550a";
224 reg = <0x1e784000 0x20>;
227 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
232 wdt1: watchdog@1e785000 {
233 compatible = "aspeed,ast2400-wdt";
234 reg = <0x1e785000 0x1c>;
235 clocks = <&syscon ASPEED_CLK_APB>;
238 wdt2: watchdog@1e785020 {
239 compatible = "aspeed,ast2400-wdt";
240 reg = <0x1e785020 0x1c>;
241 clocks = <&syscon ASPEED_CLK_APB>;
244 pwm_tacho: pwm-tacho-controller@1e786000 {
245 compatible = "aspeed,ast2400-pwm-tacho";
246 #address-cells = <1>;
248 reg = <0x1e786000 0x1000>;
249 clocks = <&syscon ASPEED_CLK_24M>;
250 resets = <&syscon ASPEED_RESET_PWM>;
254 vuart: serial@1e787000 {
255 compatible = "aspeed,ast2400-vuart";
256 reg = <0x1e787000 0x40>;
259 clocks = <&syscon ASPEED_CLK_APB>;
265 compatible = "aspeed,ast2400-lpc", "simple-mfd";
266 reg = <0x1e789000 0x1000>;
268 #address-cells = <1>;
270 ranges = <0x0 0x1e789000 0x1000>;
273 compatible = "aspeed,ast2400-lpc-bmc";
277 lpc_host: lpc-host@80 {
278 compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
282 #address-cells = <1>;
284 ranges = <0x0 0x80 0x1e0>;
286 lpc_ctrl: lpc-ctrl@0 {
287 compatible = "aspeed,ast2400-lpc-ctrl";
289 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
293 lpc_snoop: lpc-snoop@0 {
294 compatible = "aspeed,ast2400-lpc-snoop";
301 compatible = "aspeed,ast2400-lhc";
302 reg = <0x20 0x24 0x48 0x8>;
305 lpc_reset: reset-controller@18 {
306 compatible = "aspeed,ast2400-lpc-reset";
312 compatible = "aspeed,ast2400-ibt-bmc";
315 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
321 uart2: serial@1e78d000 {
322 compatible = "ns16550a";
323 reg = <0x1e78d000 0x20>;
326 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
327 resets = <&lpc_reset 5>;
332 uart3: serial@1e78e000 {
333 compatible = "ns16550a";
334 reg = <0x1e78e000 0x20>;
337 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
338 resets = <&lpc_reset 6>;
343 uart4: serial@1e78f000 {
344 compatible = "ns16550a";
345 reg = <0x1e78f000 0x20>;
348 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
349 resets = <&lpc_reset 7>;
355 compatible = "simple-bus";
356 #address-cells = <1>;
358 ranges = <0 0x1e78a000 0x1000>;
365 i2c_ic: interrupt-controller@0 {
366 #interrupt-cells = <1>;
367 compatible = "aspeed,ast2400-i2c-ic";
370 interrupt-controller;
374 #address-cells = <1>;
376 #interrupt-cells = <1>;
379 compatible = "aspeed,ast2400-i2c-bus";
380 clocks = <&syscon ASPEED_CLK_APB>;
381 resets = <&syscon ASPEED_RESET_I2C>;
382 bus-frequency = <100000>;
384 interrupt-parent = <&i2c_ic>;
386 /* Does not need pinctrl properties */
390 #address-cells = <1>;
392 #interrupt-cells = <1>;
395 compatible = "aspeed,ast2400-i2c-bus";
396 clocks = <&syscon ASPEED_CLK_APB>;
397 resets = <&syscon ASPEED_RESET_I2C>;
398 bus-frequency = <100000>;
400 interrupt-parent = <&i2c_ic>;
402 /* Does not need pinctrl properties */
406 #address-cells = <1>;
408 #interrupt-cells = <1>;
411 compatible = "aspeed,ast2400-i2c-bus";
412 clocks = <&syscon ASPEED_CLK_APB>;
413 resets = <&syscon ASPEED_RESET_I2C>;
414 bus-frequency = <100000>;
416 interrupt-parent = <&i2c_ic>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_i2c3_default>;
423 #address-cells = <1>;
425 #interrupt-cells = <1>;
428 compatible = "aspeed,ast2400-i2c-bus";
429 clocks = <&syscon ASPEED_CLK_APB>;
430 resets = <&syscon ASPEED_RESET_I2C>;
431 bus-frequency = <100000>;
433 interrupt-parent = <&i2c_ic>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_i2c4_default>;
440 #address-cells = <1>;
442 #interrupt-cells = <1>;
445 compatible = "aspeed,ast2400-i2c-bus";
446 clocks = <&syscon ASPEED_CLK_APB>;
447 resets = <&syscon ASPEED_RESET_I2C>;
448 bus-frequency = <100000>;
450 interrupt-parent = <&i2c_ic>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_i2c5_default>;
457 #address-cells = <1>;
459 #interrupt-cells = <1>;
462 compatible = "aspeed,ast2400-i2c-bus";
463 clocks = <&syscon ASPEED_CLK_APB>;
464 resets = <&syscon ASPEED_RESET_I2C>;
465 bus-frequency = <100000>;
467 interrupt-parent = <&i2c_ic>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_i2c6_default>;
474 #address-cells = <1>;
476 #interrupt-cells = <1>;
479 compatible = "aspeed,ast2400-i2c-bus";
480 clocks = <&syscon ASPEED_CLK_APB>;
481 resets = <&syscon ASPEED_RESET_I2C>;
482 bus-frequency = <100000>;
484 interrupt-parent = <&i2c_ic>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_i2c7_default>;
491 #address-cells = <1>;
493 #interrupt-cells = <1>;
496 compatible = "aspeed,ast2400-i2c-bus";
497 clocks = <&syscon ASPEED_CLK_APB>;
498 resets = <&syscon ASPEED_RESET_I2C>;
499 bus-frequency = <100000>;
501 interrupt-parent = <&i2c_ic>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_i2c8_default>;
508 #address-cells = <1>;
510 #interrupt-cells = <1>;
513 compatible = "aspeed,ast2400-i2c-bus";
514 clocks = <&syscon ASPEED_CLK_APB>;
515 resets = <&syscon ASPEED_RESET_I2C>;
516 bus-frequency = <100000>;
518 interrupt-parent = <&i2c_ic>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&pinctrl_i2c9_default>;
525 #address-cells = <1>;
527 #interrupt-cells = <1>;
530 compatible = "aspeed,ast2400-i2c-bus";
531 clocks = <&syscon ASPEED_CLK_APB>;
532 resets = <&syscon ASPEED_RESET_I2C>;
533 bus-frequency = <100000>;
535 interrupt-parent = <&i2c_ic>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_i2c10_default>;
542 #address-cells = <1>;
544 #interrupt-cells = <1>;
547 compatible = "aspeed,ast2400-i2c-bus";
548 clocks = <&syscon ASPEED_CLK_APB>;
549 resets = <&syscon ASPEED_RESET_I2C>;
550 bus-frequency = <100000>;
552 interrupt-parent = <&i2c_ic>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_i2c11_default>;
559 #address-cells = <1>;
561 #interrupt-cells = <1>;
564 compatible = "aspeed,ast2400-i2c-bus";
565 clocks = <&syscon ASPEED_CLK_APB>;
566 resets = <&syscon ASPEED_RESET_I2C>;
567 bus-frequency = <100000>;
569 interrupt-parent = <&i2c_ic>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_i2c12_default>;
576 #address-cells = <1>;
578 #interrupt-cells = <1>;
581 compatible = "aspeed,ast2400-i2c-bus";
582 clocks = <&syscon ASPEED_CLK_APB>;
583 resets = <&syscon ASPEED_RESET_I2C>;
584 bus-frequency = <100000>;
586 interrupt-parent = <&i2c_ic>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&pinctrl_i2c13_default>;
593 #address-cells = <1>;
595 #interrupt-cells = <1>;
598 compatible = "aspeed,ast2400-i2c-bus";
599 clocks = <&syscon ASPEED_CLK_APB>;
600 resets = <&syscon ASPEED_RESET_I2C>;
601 bus-frequency = <100000>;
603 interrupt-parent = <&i2c_ic>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_i2c14_default>;
611 pinctrl_acpi_default: acpi_default {
616 pinctrl_adc0_default: adc0_default {
621 pinctrl_adc1_default: adc1_default {
626 pinctrl_adc10_default: adc10_default {
631 pinctrl_adc11_default: adc11_default {
636 pinctrl_adc12_default: adc12_default {
641 pinctrl_adc13_default: adc13_default {
646 pinctrl_adc14_default: adc14_default {
651 pinctrl_adc15_default: adc15_default {
656 pinctrl_adc2_default: adc2_default {
661 pinctrl_adc3_default: adc3_default {
666 pinctrl_adc4_default: adc4_default {
671 pinctrl_adc5_default: adc5_default {
676 pinctrl_adc6_default: adc6_default {
681 pinctrl_adc7_default: adc7_default {
686 pinctrl_adc8_default: adc8_default {
691 pinctrl_adc9_default: adc9_default {
696 pinctrl_bmcint_default: bmcint_default {
701 pinctrl_ddcclk_default: ddcclk_default {
706 pinctrl_ddcdat_default: ddcdat_default {
711 pinctrl_extrst_default: extrst_default {
716 pinctrl_flack_default: flack_default {
721 pinctrl_flbusy_default: flbusy_default {
726 pinctrl_flwp_default: flwp_default {
731 pinctrl_gpid_default: gpid_default {
736 pinctrl_gpid0_default: gpid0_default {
741 pinctrl_gpid2_default: gpid2_default {
746 pinctrl_gpid4_default: gpid4_default {
751 pinctrl_gpid6_default: gpid6_default {
756 pinctrl_gpie0_default: gpie0_default {
761 pinctrl_gpie2_default: gpie2_default {
766 pinctrl_gpie4_default: gpie4_default {
771 pinctrl_gpie6_default: gpie6_default {
776 pinctrl_i2c10_default: i2c10_default {
781 pinctrl_i2c11_default: i2c11_default {
786 pinctrl_i2c12_default: i2c12_default {
791 pinctrl_i2c13_default: i2c13_default {
796 pinctrl_i2c14_default: i2c14_default {
801 pinctrl_i2c3_default: i2c3_default {
806 pinctrl_i2c4_default: i2c4_default {
811 pinctrl_i2c5_default: i2c5_default {
816 pinctrl_i2c6_default: i2c6_default {
821 pinctrl_i2c7_default: i2c7_default {
826 pinctrl_i2c8_default: i2c8_default {
831 pinctrl_i2c9_default: i2c9_default {
836 pinctrl_lpcpd_default: lpcpd_default {
841 pinctrl_lpcpme_default: lpcpme_default {
846 pinctrl_lpcrst_default: lpcrst_default {
851 pinctrl_lpcsmi_default: lpcsmi_default {
856 pinctrl_mac1link_default: mac1link_default {
857 function = "MAC1LINK";
861 pinctrl_mac2link_default: mac2link_default {
862 function = "MAC2LINK";
866 pinctrl_mdio1_default: mdio1_default {
871 pinctrl_mdio2_default: mdio2_default {
876 pinctrl_ncts1_default: ncts1_default {
881 pinctrl_ncts2_default: ncts2_default {
886 pinctrl_ncts3_default: ncts3_default {
891 pinctrl_ncts4_default: ncts4_default {
896 pinctrl_ndcd1_default: ndcd1_default {
901 pinctrl_ndcd2_default: ndcd2_default {
906 pinctrl_ndcd3_default: ndcd3_default {
911 pinctrl_ndcd4_default: ndcd4_default {
916 pinctrl_ndsr1_default: ndsr1_default {
921 pinctrl_ndsr2_default: ndsr2_default {
926 pinctrl_ndsr3_default: ndsr3_default {
931 pinctrl_ndsr4_default: ndsr4_default {
936 pinctrl_ndtr1_default: ndtr1_default {
941 pinctrl_ndtr2_default: ndtr2_default {
946 pinctrl_ndtr3_default: ndtr3_default {
951 pinctrl_ndtr4_default: ndtr4_default {
956 pinctrl_ndts4_default: ndts4_default {
961 pinctrl_nri1_default: nri1_default {
966 pinctrl_nri2_default: nri2_default {
971 pinctrl_nri3_default: nri3_default {
976 pinctrl_nri4_default: nri4_default {
981 pinctrl_nrts1_default: nrts1_default {
986 pinctrl_nrts2_default: nrts2_default {
991 pinctrl_nrts3_default: nrts3_default {
996 pinctrl_oscclk_default: oscclk_default {
1001 pinctrl_pwm0_default: pwm0_default {
1006 pinctrl_pwm1_default: pwm1_default {
1011 pinctrl_pwm2_default: pwm2_default {
1016 pinctrl_pwm3_default: pwm3_default {
1021 pinctrl_pwm4_default: pwm4_default {
1026 pinctrl_pwm5_default: pwm5_default {
1031 pinctrl_pwm6_default: pwm6_default {
1036 pinctrl_pwm7_default: pwm7_default {
1041 pinctrl_rgmii1_default: rgmii1_default {
1042 function = "RGMII1";
1046 pinctrl_rgmii2_default: rgmii2_default {
1047 function = "RGMII2";
1051 pinctrl_rmii1_default: rmii1_default {
1056 pinctrl_rmii2_default: rmii2_default {
1061 pinctrl_rom16_default: rom16_default {
1066 pinctrl_rom8_default: rom8_default {
1071 pinctrl_romcs1_default: romcs1_default {
1072 function = "ROMCS1";
1076 pinctrl_romcs2_default: romcs2_default {
1077 function = "ROMCS2";
1081 pinctrl_romcs3_default: romcs3_default {
1082 function = "ROMCS3";
1086 pinctrl_romcs4_default: romcs4_default {
1087 function = "ROMCS4";
1091 pinctrl_rxd1_default: rxd1_default {
1096 pinctrl_rxd2_default: rxd2_default {
1101 pinctrl_rxd3_default: rxd3_default {
1106 pinctrl_rxd4_default: rxd4_default {
1111 pinctrl_salt1_default: salt1_default {
1116 pinctrl_salt2_default: salt2_default {
1121 pinctrl_salt3_default: salt3_default {
1126 pinctrl_salt4_default: salt4_default {
1131 pinctrl_sd1_default: sd1_default {
1136 pinctrl_sd2_default: sd2_default {
1141 pinctrl_sgpmck_default: sgpmck_default {
1142 function = "SGPMCK";
1146 pinctrl_sgpmi_default: sgpmi_default {
1151 pinctrl_sgpmld_default: sgpmld_default {
1152 function = "SGPMLD";
1156 pinctrl_sgpmo_default: sgpmo_default {
1161 pinctrl_sgpsck_default: sgpsck_default {
1162 function = "SGPSCK";
1166 pinctrl_sgpsi0_default: sgpsi0_default {
1167 function = "SGPSI0";
1171 pinctrl_sgpsi1_default: sgpsi1_default {
1172 function = "SGPSI1";
1176 pinctrl_sgpsld_default: sgpsld_default {
1177 function = "SGPSLD";
1181 pinctrl_sioonctrl_default: sioonctrl_default {
1182 function = "SIOONCTRL";
1183 groups = "SIOONCTRL";
1186 pinctrl_siopbi_default: siopbi_default {
1187 function = "SIOPBI";
1191 pinctrl_siopbo_default: siopbo_default {
1192 function = "SIOPBO";
1196 pinctrl_siopwreq_default: siopwreq_default {
1197 function = "SIOPWREQ";
1198 groups = "SIOPWREQ";
1201 pinctrl_siopwrgd_default: siopwrgd_default {
1202 function = "SIOPWRGD";
1203 groups = "SIOPWRGD";
1206 pinctrl_sios3_default: sios3_default {
1211 pinctrl_sios5_default: sios5_default {
1216 pinctrl_siosci_default: siosci_default {
1217 function = "SIOSCI";
1221 pinctrl_spi1_default: spi1_default {
1226 pinctrl_spi1debug_default: spi1debug_default {
1227 function = "SPI1DEBUG";
1228 groups = "SPI1DEBUG";
1231 pinctrl_spi1passthru_default: spi1passthru_default {
1232 function = "SPI1PASSTHRU";
1233 groups = "SPI1PASSTHRU";
1236 pinctrl_spics1_default: spics1_default {
1237 function = "SPICS1";
1241 pinctrl_timer3_default: timer3_default {
1242 function = "TIMER3";
1246 pinctrl_timer4_default: timer4_default {
1247 function = "TIMER4";
1251 pinctrl_timer5_default: timer5_default {
1252 function = "TIMER5";
1256 pinctrl_timer6_default: timer6_default {
1257 function = "TIMER6";
1261 pinctrl_timer7_default: timer7_default {
1262 function = "TIMER7";
1266 pinctrl_timer8_default: timer8_default {
1267 function = "TIMER8";
1271 pinctrl_txd1_default: txd1_default {
1276 pinctrl_txd2_default: txd2_default {
1281 pinctrl_txd3_default: txd3_default {
1286 pinctrl_txd4_default: txd4_default {
1291 pinctrl_uart6_default: uart6_default {
1296 pinctrl_usbcki_default: usbcki_default {
1297 function = "USBCKI";
1301 pinctrl_usb2h_default: usb2h_default {
1302 function = "USB2H1";
1306 pinctrl_usb2d_default: usb2d_default {
1307 function = "USB2D1";
1311 pinctrl_vgabios_rom_default: vgabios_rom_default {
1312 function = "VGABIOS_ROM";
1313 groups = "VGABIOS_ROM";
1316 pinctrl_vgahs_default: vgahs_default {
1321 pinctrl_vgavs_default: vgavs_default {
1326 pinctrl_vpi18_default: vpi18_default {
1331 pinctrl_vpi24_default: vpi24_default {
1336 pinctrl_vpi30_default: vpi30_default {
1341 pinctrl_vpo12_default: vpo12_default {
1346 pinctrl_vpo24_default: vpo24_default {
1351 pinctrl_wdtrst1_default: wdtrst1_default {
1352 function = "WDTRST1";
1356 pinctrl_wdtrst2_default: wdtrst2_default {
1357 function = "WDTRST2";